Add PowerPC power-management state check callback.

[qemu] / hw / iommu.c

diff --git a/hw/iommu.c b/hw/iommu.c
index bd52454..55d39b9 100644 (file)
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -81,7 +81,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
-                                                 produced by this device as pure
+                                          produced by this device as pure
                                           physical. */
 #define IOMMU_SBCFG_MASK    0x00010003
 
@@ -98,7 +98,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
 
 #define PAGE_SHIFT      12
 #define PAGE_SIZE       (1 << PAGE_SHIFT)
-#define PAGE_MASK      (PAGE_SIZE - 1)
+#define PAGE_MASK       (PAGE_SIZE - 1)
 
 typedef struct IOMMUState {
     target_phys_addr_t addr;
@@ -114,9 +114,9 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
     saddr = (addr - s->addr) >> 2;
     switch (saddr) {
     default:
-       DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
-       return s->regs[saddr];
-       break;
+        DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
+        return s->regs[saddr];
+        break;
     }
     return 0;
 }
@@ -130,61 +130,61 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
     DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
     switch (saddr) {
     case IOMMU_CTRL:
-       switch (val & IOMMU_CTRL_RNGE) {
-       case IOMMU_RNGE_16MB:
-           s->iostart = 0xffffffffff000000ULL;
-           break;
-       case IOMMU_RNGE_32MB:
-           s->iostart = 0xfffffffffe000000ULL;
-           break;
-       case IOMMU_RNGE_64MB:
-           s->iostart = 0xfffffffffc000000ULL;
-           break;
-       case IOMMU_RNGE_128MB:
-           s->iostart = 0xfffffffff8000000ULL;
-           break;
-       case IOMMU_RNGE_256MB:
-           s->iostart = 0xfffffffff0000000ULL;
-           break;
-       case IOMMU_RNGE_512MB:
-           s->iostart = 0xffffffffe0000000ULL;
-           break;
-       case IOMMU_RNGE_1GB:
-           s->iostart = 0xffffffffc0000000ULL;
-           break;
-       default:
-       case IOMMU_RNGE_2GB:
-           s->iostart = 0xffffffff80000000ULL;
-           break;
-       }
-       DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
-       s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
-       break;
+        switch (val & IOMMU_CTRL_RNGE) {
+        case IOMMU_RNGE_16MB:
+            s->iostart = 0xffffffffff000000ULL;
+            break;
+        case IOMMU_RNGE_32MB:
+            s->iostart = 0xfffffffffe000000ULL;
+            break;
+        case IOMMU_RNGE_64MB:
+            s->iostart = 0xfffffffffc000000ULL;
+            break;
+        case IOMMU_RNGE_128MB:
+            s->iostart = 0xfffffffff8000000ULL;
+            break;
+        case IOMMU_RNGE_256MB:
+            s->iostart = 0xfffffffff0000000ULL;
+            break;
+        case IOMMU_RNGE_512MB:
+            s->iostart = 0xffffffffe0000000ULL;
+            break;
+        case IOMMU_RNGE_1GB:
+            s->iostart = 0xffffffffc0000000ULL;
+            break;
+        default:
+        case IOMMU_RNGE_2GB:
+            s->iostart = 0xffffffff80000000ULL;
+            break;
+        }
+        DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
+        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
+        break;
     case IOMMU_BASE:
-       s->regs[saddr] = val & IOMMU_BASE_MASK;
-       break;
+        s->regs[saddr] = val & IOMMU_BASE_MASK;
+        break;
     case IOMMU_TLBFLUSH:
-       DPRINTF("tlb flush %x\n", val);
-       s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
-       break;
+        DPRINTF("tlb flush %x\n", val);
+        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
+        break;
     case IOMMU_PGFLUSH:
-       DPRINTF("page flush %x\n", val);
-       s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
-       break;
+        DPRINTF("page flush %x\n", val);
+        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
+        break;
     case IOMMU_SBCFG0:
     case IOMMU_SBCFG1:
     case IOMMU_SBCFG2:
     case IOMMU_SBCFG3:
-       s->regs[saddr] = val & IOMMU_SBCFG_MASK;
-       break;
+        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
+        break;
     case IOMMU_ARBEN:
         // XXX implement SBus probing: fault when reading unmapped
         // addresses, fault cause and address stored to MMU/IOMMU
-       s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
-       break;
+        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
+        break;
     default:
-       s->regs[saddr] = val;
-       break;
+        s->regs[saddr] = val;
+        break;
     }
 }
 
@@ -202,7 +202,8 @@ static CPUWriteMemoryFunc *iommu_mem_write[3] = {
 
 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
 {
-    uint32_t iopte, ret;
+    uint32_t ret;
+    target_phys_addr_t iopte;
 #ifdef DEBUG_IOMMU
     target_phys_addr_t pa = addr;
 #endif
@@ -210,9 +211,10 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
     iopte = s->regs[IOMMU_BASE] << 4;
     addr &= ~s->iostart;
     iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
-    ret = ldl_phys(iopte);
-    DPRINTF("get flags addr " TARGET_FMT_plx " => pte %x, *ptes = %x\n", pa,
-            iopte, ret);
+    cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
+    tswap32s(&ret);
+    DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
+            ", *pte = %x\n", pa, iopte, ret);
 
     return ret;
 }
@@ -279,9 +281,9 @@ static void iommu_save(QEMUFile *f, void *opaque)
 {
     IOMMUState *s = opaque;
     int i;
-   
+
     for (i = 0; i < IOMMU_NREGS; i++)
-       qemu_put_be32s(f, &s->regs[i]);
+        qemu_put_be32s(f, &s->regs[i]);
     qemu_put_be64s(f, &s->iostart);
 }
 
@@ -289,7 +291,7 @@ static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 {
     IOMMUState *s = opaque;
     int i;
-   
+
     if (version_id != 2)
         return -EINVAL;
 
@@ -322,7 +324,7 @@ void *iommu_init(target_phys_addr_t addr)
 
     iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
     cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
-   
+
     register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
     qemu_register_reset(iommu_reset, s);
     return s;