Sparc32/64 CPU selection

[qemu] / hw / i8259.c

diff --git a/hw/i8259.c b/hw/i8259.c
index 1be40c9..f8b5a98 100644 (file)
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -55,6 +55,9 @@ struct PicState2 {
     PicState pics[2];
     IRQRequestFunc *irq_request;
     void *irq_request_opaque;
+    /* IOAPIC callback support */
+    SetIRQFunc *alt_irq_func;
+    void *alt_irq_opaque;
 };
 
 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
@@ -158,6 +161,13 @@ void pic_update_irq(PicState2 *s)
 #endif
         s->irq_request(s->irq_request_opaque, 1);
     }
+
+/* all targets should do this rather than acking the IRQ in the cpu */
+#if defined(TARGET_MIPS)
+    else {
+        s->irq_request(s->irq_request_opaque, 0);
+    }
+#endif
 }
 
 #ifdef DEBUG_IRQ_LATENCY
@@ -186,6 +196,9 @@ void pic_set_irq_new(void *opaque, int irq, int level)
     }
 #endif
     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
+    /* used for IOAPIC irqs */
+    if (s->alt_irq_func)
+        s->alt_irq_func(s->alt_irq_opaque, irq, level);
     pic_update_irq(s);
 }
 
@@ -265,7 +278,7 @@ static void pic_reset(void *opaque)
     s->rotate_on_auto_eoi = 0;
     s->special_fully_nested_mode = 0;
     s->init4 = 0;
-    s->elcr = 0;
+    /* Note: ELCR is not reset */
 }
 
 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
@@ -525,7 +538,7 @@ void irq_info(void)
     for (i = 0; i < 16; i++) {
         count = irq_count[i];
         if (count > 0)
-            term_printf("%2d: %lld\n", i, count);
+            term_printf("%2d: %" PRId64 "\n", i, count);
     }
 #endif
 }
@@ -546,3 +559,10 @@ PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
     s->pics[1].pics_state = s;
     return s;
 }
+
+void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
+                          void *alt_irq_opaque)
+{
+    s->alt_irq_func = alt_irq_func;
+    s->alt_irq_opaque = alt_irq_opaque;
+}