ne2000 savevm support (Johannes Schindelin)

[qemu] / hw / i8259.c

diff --git a/hw/i8259.c b/hw/i8259.c
index e09bc9f..221506b 100644 (file)
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -27,6 +27,7 @@
 //#define DEBUG_PIC
 
 //#define DEBUG_IRQ_LATENCY
+//#define DEBUG_IRQ_COUNT
 
 typedef struct PicState {
     uint8_t last_irr; /* edge detection */
@@ -49,7 +50,13 @@ typedef struct PicState {
 
 /* 0 is master pic, 1 is slave pic */
 static PicState pics[2];
-static int pic_irq_requested;
+
+#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
+static int irq_level[16];
+#endif
+#ifdef DEBUG_IRQ_COUNT
+static uint64_t irq_count[16];
+#endif
 
 /* set irq level. If an edge is detected, then the IRR is set to 1 */
 static inline void pic_set_irq1(PicState *s, int irq, int level)
@@ -130,13 +137,6 @@ static void pic_update_irq(void)
     /* look at requested irq */
     irq = pic_get_irq(&pics[0]);
     if (irq >= 0) {
-        if (irq == 2) {
-            /* from slave pic */
-            pic_irq_requested = 8 + irq2;
-        } else {
-            /* from master pic */
-            pic_irq_requested = irq;
-        }
 #if defined(DEBUG_PIC)
         {
             int i;
@@ -146,7 +146,7 @@ static void pic_update_irq(void)
                 
             }
         }
-        printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
+        printf("pic: cpu_interrupt\n");
 #endif
         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
     }
@@ -155,21 +155,24 @@ static void pic_update_irq(void)
 #ifdef DEBUG_IRQ_LATENCY
 int64_t irq_time[16];
 #endif
-#if defined(DEBUG_PIC)
-int irq_level[16];
-#endif
 
 void pic_set_irq(int irq, int level)
 {
-#if defined(DEBUG_PIC)
+#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
     if (level != irq_level[irq]) {
+#if defined(DEBUG_PIC)
         printf("pic_set_irq: irq=%d level=%d\n", irq, level);
+#endif
         irq_level[irq] = level;
+#ifdef DEBUG_IRQ_COUNT
+       if (level == 1)
+           irq_count[irq]++;
+#endif
     }
 #endif
 #ifdef DEBUG_IRQ_LATENCY
     if (level) {
-        irq_time[irq] = cpu_get_ticks();
+        irq_time[irq] = qemu_get_clock(vm_clock);
     }
 #endif
     pic_set_irq1(&pics[irq >> 3], irq & 7, level);
@@ -185,41 +188,65 @@ static inline void pic_intack(PicState *s, int irq)
     } else {
         s->isr |= (1 << irq);
     }
-    s->irr &= ~(1 << irq);
+    /* We don't clear a level sensitive interrupt here */
+    if (!(s->elcr & (1 << irq)))
+        s->irr &= ~(1 << irq);
 }
 
 int cpu_get_pic_interrupt(CPUState *env)
 {
     int irq, irq2, intno;
 
-    /* signal the pic that the irq was acked by the CPU */
-    irq = pic_irq_requested;
+    /* read the irq from the PIC */
+
+    irq = pic_get_irq(&pics[0]);
+    if (irq >= 0) {
+        pic_intack(&pics[0], irq);
+        if (irq == 2) {
+            irq2 = pic_get_irq(&pics[1]);
+            if (irq2 >= 0) {
+                pic_intack(&pics[1], irq2);
+            } else {
+                /* spurious IRQ on slave controller */
+                irq2 = 7;
+            }
+            intno = pics[1].irq_base + irq2;
+            irq = irq2 + 8;
+        } else {
+            intno = pics[0].irq_base + irq;
+        }
+    } else {
+        /* spurious IRQ on host controller */
+        irq = 7;
+        intno = pics[0].irq_base + irq;
+    }
+    pic_update_irq();
+        
 #ifdef DEBUG_IRQ_LATENCY
     printf("IRQ%d latency=%0.3fus\n", 
            irq, 
-           (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
+           (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 #endif
 #if defined(DEBUG_PIC)
     printf("pic_interrupt: irq=%d\n", irq);
 #endif
-
-    if (irq >= 8) {
-        irq2 = irq & 7;
-        pic_intack(&pics[1], irq2);
-        irq = 2;
-        intno = pics[1].irq_base + irq2;
-    } else {
-        intno = pics[0].irq_base + irq;
-    }
-    pic_intack(&pics[0], irq);
-    pic_update_irq();
     return intno;
 }
 
+static void pic_reset(void *opaque)
+{
+    PicState *s = opaque;
+    int tmp;
+
+    tmp = s->elcr_mask;
+    memset(s, 0, sizeof(PicState));
+    s->elcr_mask = tmp;
+}
+
 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
     PicState *s = opaque;
-    int priority, cmd, irq, tmp;
+    int priority, cmd, irq;
 
 #ifdef DEBUG_PIC
     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
@@ -228,9 +255,9 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
     if (addr == 0) {
         if (val & 0x10) {
             /* init */
-            tmp = s->elcr_mask;
-            memset(s, 0, sizeof(PicState));
-            s->elcr_mask = tmp;
+            pic_reset(s);
+            /* deassert a pending interrupt */
+            cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 
             s->init_state = 1;
             s->init4 = val & 1;
@@ -441,6 +468,7 @@ static void pic_init1(int io_addr, int elcr_addr, PicState *s)
         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
     }
     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
+    qemu_register_reset(pic_reset, s);
 }
 
 void pic_info(void)
@@ -450,12 +478,29 @@ void pic_info(void)
 
     for(i=0;i<2;i++) {
         s = &pics[i];
-        term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x\n",
+        term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
                     i, s->irr, s->imr, s->isr, s->priority_add, 
-                    s->irq_base, s->read_reg_select, s->elcr);
+                    s->irq_base, s->read_reg_select, s->elcr, 
+                    s->special_fully_nested_mode);
     }
 }
 
+void irq_info(void)
+{
+#ifndef DEBUG_IRQ_COUNT
+    term_printf("irq statistic code not compiled.\n");
+#else
+    int i;
+    int64_t count;
+
+    term_printf("IRQ statistics:\n");
+    for (i = 0; i < 16; i++) {
+        count = irq_count[i];
+        if (count > 0)
+            term_printf("%2d: %lld\n", i, count);
+    }
+#endif
+}
 
 void pic_init(void)
 {