* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include <stdlib.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <string.h>
-#include <getopt.h>
-#include <inttypes.h>
-#include <unistd.h>
-#include <sys/mman.h>
-#include <fcntl.h>
-#include <signal.h>
-#include <time.h>
-#include <sys/time.h>
-#include <malloc.h>
-#include <termios.h>
-#include <sys/poll.h>
-#include <errno.h>
-#include <sys/wait.h>
-#include <netinet/in.h>
-
-#include "cpu.h"
#include "vl.h"
/* debug PIC */
//#define DEBUG_PIC
//#define DEBUG_IRQ_LATENCY
+//#define DEBUG_IRQ_COUNT
typedef struct PicState {
uint8_t last_irr; /* edge detection */
uint8_t rotate_on_auto_eoi;
uint8_t special_fully_nested_mode;
uint8_t init4; /* true if 4 byte init */
+ uint8_t elcr; /* PIIX edge/trigger selection*/
+ uint8_t elcr_mask;
} PicState;
/* 0 is master pic, 1 is slave pic */
-PicState pics[2];
-int pic_irq_requested;
+static PicState pics[2];
+
+#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
+static int irq_level[16];
+#endif
+#ifdef DEBUG_IRQ_COUNT
+static uint64_t irq_count[16];
+#endif
/* set irq level. If an edge is detected, then the IRR is set to 1 */
static inline void pic_set_irq1(PicState *s, int irq, int level)
{
int mask;
mask = 1 << irq;
- if (level) {
- if ((s->last_irr & mask) == 0)
+ if (s->elcr & mask) {
+ /* level triggered */
+ if (level) {
s->irr |= mask;
- s->last_irr |= mask;
+ s->last_irr |= mask;
+ } else {
+ s->irr &= ~mask;
+ s->last_irr &= ~mask;
+ }
} else {
- s->last_irr &= ~mask;
+ /* edge triggered */
+ if (level) {
+ if ((s->last_irr & mask) == 0)
+ s->irr |= mask;
+ s->last_irr |= mask;
+ } else {
+ s->last_irr &= ~mask;
+ }
}
}
/* raise irq to CPU if necessary. must be called every time the active
irq may change */
-void pic_update_irq(void)
+static void pic_update_irq(void)
{
int irq2, irq;
/* look at requested irq */
irq = pic_get_irq(&pics[0]);
if (irq >= 0) {
- if (irq == 2) {
- /* from slave pic */
- pic_irq_requested = 8 + irq2;
- } else {
- /* from master pic */
- pic_irq_requested = irq;
- }
#if defined(DEBUG_PIC)
{
int i;
}
}
- printf("pic: cpu_interrupt req=%d\n", pic_irq_requested);
+ printf("pic: cpu_interrupt\n");
#endif
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
}
#ifdef DEBUG_IRQ_LATENCY
int64_t irq_time[16];
-int64_t cpu_get_ticks(void);
-#endif
-#if defined(DEBUG_PIC)
-int irq_level[16];
#endif
void pic_set_irq(int irq, int level)
{
-#if defined(DEBUG_PIC)
+#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
if (level != irq_level[irq]) {
+#if defined(DEBUG_PIC)
printf("pic_set_irq: irq=%d level=%d\n", irq, level);
+#endif
irq_level[irq] = level;
+#ifdef DEBUG_IRQ_COUNT
+ if (level == 1)
+ irq_count[irq]++;
+#endif
}
#endif
#ifdef DEBUG_IRQ_LATENCY
if (level) {
- irq_time[irq] = cpu_get_ticks();
+ irq_time[irq] = qemu_get_clock(vm_clock);
}
#endif
pic_set_irq1(&pics[irq >> 3], irq & 7, level);
} else {
s->isr |= (1 << irq);
}
- s->irr &= ~(1 << irq);
+ /* We don't clear a level sensitive interrupt here */
+ if (!(s->elcr & (1 << irq)))
+ s->irr &= ~(1 << irq);
}
-int cpu_x86_get_pic_interrupt(CPUState *env)
+int cpu_get_pic_interrupt(CPUState *env)
{
int irq, irq2, intno;
- /* signal the pic that the irq was acked by the CPU */
- irq = pic_irq_requested;
+ /* read the irq from the PIC */
+
+ irq = pic_get_irq(&pics[0]);
+ if (irq >= 0) {
+ pic_intack(&pics[0], irq);
+ if (irq == 2) {
+ irq2 = pic_get_irq(&pics[1]);
+ if (irq2 >= 0) {
+ pic_intack(&pics[1], irq2);
+ } else {
+ /* spurious IRQ on slave controller */
+ irq2 = 7;
+ }
+ intno = pics[1].irq_base + irq2;
+ irq = irq2 + 8;
+ } else {
+ intno = pics[0].irq_base + irq;
+ }
+ } else {
+ /* spurious IRQ on host controller */
+ irq = 7;
+ intno = pics[0].irq_base + irq;
+ }
+ pic_update_irq();
+
#ifdef DEBUG_IRQ_LATENCY
printf("IRQ%d latency=%0.3fus\n",
irq,
- (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
+ (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
#endif
#if defined(DEBUG_PIC)
printf("pic_interrupt: irq=%d\n", irq);
#endif
-
- if (irq >= 8) {
- irq2 = irq & 7;
- pic_intack(&pics[1], irq2);
- irq = 2;
- intno = pics[1].irq_base + irq2;
- } else {
- intno = pics[0].irq_base + irq;
- }
- pic_intack(&pics[0], irq);
return intno;
}
+static void pic_reset(void *opaque)
+{
+ PicState *s = opaque;
+ int tmp;
+
+ tmp = s->elcr_mask;
+ memset(s, 0, sizeof(PicState));
+ s->elcr_mask = tmp;
+}
+
static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
PicState *s = opaque;
if (addr == 0) {
if (val & 0x10) {
/* init */
- memset(s, 0, sizeof(PicState));
+ pic_reset(s);
+ /* deassert a pending interrupt */
+ cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
+
s->init_state = 1;
s->init4 = val & 1;
if (val & 0x02)
return ret;
}
+static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ PicState *s = opaque;
+ s->elcr = val & s->elcr_mask;
+}
+
+static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
+{
+ PicState *s = opaque;
+ return s->elcr;
+}
+
+static void pic_save(QEMUFile *f, void *opaque)
+{
+ PicState *s = opaque;
+
+ qemu_put_8s(f, &s->last_irr);
+ qemu_put_8s(f, &s->irr);
+ qemu_put_8s(f, &s->imr);
+ qemu_put_8s(f, &s->isr);
+ qemu_put_8s(f, &s->priority_add);
+ qemu_put_8s(f, &s->irq_base);
+ qemu_put_8s(f, &s->read_reg_select);
+ qemu_put_8s(f, &s->poll);
+ qemu_put_8s(f, &s->special_mask);
+ qemu_put_8s(f, &s->init_state);
+ qemu_put_8s(f, &s->auto_eoi);
+ qemu_put_8s(f, &s->rotate_on_auto_eoi);
+ qemu_put_8s(f, &s->special_fully_nested_mode);
+ qemu_put_8s(f, &s->init4);
+ qemu_put_8s(f, &s->elcr);
+}
+
+static int pic_load(QEMUFile *f, void *opaque, int version_id)
+{
+ PicState *s = opaque;
+
+ if (version_id != 1)
+ return -EINVAL;
+
+ qemu_get_8s(f, &s->last_irr);
+ qemu_get_8s(f, &s->irr);
+ qemu_get_8s(f, &s->imr);
+ qemu_get_8s(f, &s->isr);
+ qemu_get_8s(f, &s->priority_add);
+ qemu_get_8s(f, &s->irq_base);
+ qemu_get_8s(f, &s->read_reg_select);
+ qemu_get_8s(f, &s->poll);
+ qemu_get_8s(f, &s->special_mask);
+ qemu_get_8s(f, &s->init_state);
+ qemu_get_8s(f, &s->auto_eoi);
+ qemu_get_8s(f, &s->rotate_on_auto_eoi);
+ qemu_get_8s(f, &s->special_fully_nested_mode);
+ qemu_get_8s(f, &s->init4);
+ qemu_get_8s(f, &s->elcr);
+ return 0;
+}
+
+/* XXX: add generic master/slave system */
+static void pic_init1(int io_addr, int elcr_addr, PicState *s)
+{
+ register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
+ register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
+ if (elcr_addr >= 0) {
+ register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
+ register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
+ }
+ register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
+ qemu_register_reset(pic_reset, s);
+}
+
+void pic_info(void)
+{
+ int i;
+ PicState *s;
+
+ for(i=0;i<2;i++) {
+ s = &pics[i];
+ term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
+ i, s->irr, s->imr, s->isr, s->priority_add,
+ s->irq_base, s->read_reg_select, s->elcr,
+ s->special_fully_nested_mode);
+ }
+}
+
+void irq_info(void)
+{
+#ifndef DEBUG_IRQ_COUNT
+ term_printf("irq statistic code not compiled.\n");
+#else
+ int i;
+ int64_t count;
+
+ term_printf("IRQ statistics:\n");
+ for (i = 0; i < 16; i++) {
+ count = irq_count[i];
+ if (count > 0)
+ term_printf("%2d: %lld\n", i, count);
+ }
+#endif
+}
+
void pic_init(void)
{
- register_ioport_write(0x20, 2, 1, pic_ioport_write, &pics[0]);
- register_ioport_read(0x20, 2, 1, pic_ioport_read, &pics[0]);
- register_ioport_write(0xa0, 2, 1, pic_ioport_write, &pics[1]);
- register_ioport_read(0xa0, 2, 1, pic_ioport_read, &pics[1]);
+ pic_init1(0x20, 0x4d0, &pics[0]);
+ pic_init1(0xa0, 0x4d1, &pics[1]);
+ pics[0].elcr_mask = 0xf8;
+ pics[1].elcr_mask = 0xde;
}
projects / qemu / blobdiff