* QEMU GT64120 PCI host
*
* Copyright (c) 2006,2007 Aurelien Jarno
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
/* Update IO mapping */
if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
{
- /* Unmap old IO address */
+ /* Unmap old IO address */
if (s->PCI0IO_length)
{
- cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
}
/* Map new IO address */
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
GT64120State *s = opaque;
uint32_t saddr;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
+ if (!(s->regs[GT_PCI0_CMD] & 1))
+ val = bswap32(val);
saddr = (addr & 0xfff) >> 2;
switch (saddr) {
case GT_PCI0M0LD:
s->regs[GT_PCI0M0LD] = val & 0x00007fff;
s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
break;
case GT_PCI0M1LD:
s->regs[GT_PCI0M1LD] = val & 0x00007fff;
s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
break;
case GT_PCI1IOLD:
s->regs[GT_PCI1IOLD] = val & 0x00007fff;
s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
break;
case GT_PCI1M0LD:
s->regs[GT_PCI1M0LD] = val & 0x00007fff;
s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
break;
case GT_PCI1M1LD:
s->regs[GT_PCI1M1LD] = val & 0x00007fff;
s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
- gt64120_pci_mapping(s);
break;
case GT_PCI0IOHD:
+ s->regs[saddr] = val & 0x0000007f;
+ gt64120_pci_mapping(s);
+ break;
case GT_PCI0M0HD:
case GT_PCI0M1HD:
case GT_PCI1IOHD:
case GT_PCI1M0HD:
case GT_PCI1M1HD:
s->regs[saddr] = val & 0x0000007f;
- gt64120_pci_mapping(s);
break;
case GT_ISD:
s->regs[saddr] = val & 0x00007fff;
case GT_PCI1M0REMAP:
case GT_PCI1M1REMAP:
s->regs[saddr] = val & 0x000007ff;
- gt64120_pci_mapping(s);
break;
/* CPU Error Report */
s->pci->config_reg = val & 0x80fffffc;
break;
case GT_PCI0_CFGDATA:
- if (s->pci->config_reg & (1u << 31))
- pci_host_data_writel(s->pci, 0, val);
+ pci_host_data_writel(s->pci, 0, val);
break;
/* Interrupts */
uint32_t val;
uint32_t saddr;
- val = 0;
saddr = (addr & 0xfff) >> 2;
-
switch (saddr) {
/* CPU Configuration */
case GT_CPUERR_DATAHI:
case GT_CPUERR_PARITY:
/* Emulated memory has no error, always return the initial
- values */
+ values */
val = s->regs[saddr];
break;
/* Reading those register should empty all FIFO on the PCI
bus, which are not emulated. The return value should be
a random value that should be ignored. */
- val = 0xc000ffee;
+ val = 0xc000ffee;
break;
/* ECC */
case GT_ECC_CALC:
case GT_ECC_ERRADDR:
/* Emulated memory has no error, always return the initial
- values */
+ values */
val = s->regs[saddr];
break;
val = s->regs[saddr];
break;
case GT_PCI0_IACK:
- /* Read the IRQ number */
+ /* Read the IRQ number */
val = pic_read_irq(isa_pic);
break;
val = s->pci->config_reg;
break;
case GT_PCI0_CFGDATA:
- if (!(s->pci->config_reg & (1u << 31)))
- val = 0xffffffff;
- else
- val = pci_host_data_readl(s->pci, 0);
+ val = pci_host_data_readl(s->pci, 0);
break;
case GT_PCI0_CMD:
break;
}
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
+ if (!(s->regs[GT_PCI0_CMD] & 1))
+ val = bswap32(val);
+
return val;
}
static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
{
- uint32_t val = pci_default_read_config(d, address, len);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ return pci_default_read_config(d, address, len);
}
static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
int len)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
pci_default_write_config(d, address, val, len);
}