/* Update IO mapping */
if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
{
- /* Unmap old IO address */
+ /* Unmap old IO address */
if (s->PCI0IO_length)
{
- cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
}
/* Map new IO address */
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
GT64120State *s = opaque;
uint32_t saddr;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
+ if (!(s->regs[GT_PCI0_CMD] & 1))
+ val = bswap32(val);
saddr = (addr & 0xfff) >> 2;
switch (saddr) {
s->pci->config_reg = val & 0x80fffffc;
break;
case GT_PCI0_CFGDATA:
- if (s->pci->config_reg & (1u << 31))
- pci_host_data_writel(s->pci, 0, val);
+ pci_host_data_writel(s->pci, 0, val);
break;
/* Interrupts */
uint32_t val;
uint32_t saddr;
- val = 0;
saddr = (addr & 0xfff) >> 2;
-
switch (saddr) {
/* CPU Configuration */
val = s->pci->config_reg;
break;
case GT_PCI0_CFGDATA:
- if (!(s->pci->config_reg & (1u << 31)))
- val = 0xffffffff;
- else
- val = pci_host_data_readl(s->pci, 0);
+ val = pci_host_data_readl(s->pci, 0);
break;
case GT_PCI0_CMD:
break;
}
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
+ if (!(s->regs[GT_PCI0_CMD] & 1))
+ val = bswap32(val);
+
return val;
}
static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
{
- uint32_t val = pci_default_read_config(d, address, len);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ return pci_default_read_config(d, address, len);
}
static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
int len)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
pci_default_write_config(d, address, val, len);
}