typedef struct ESPState ESPState;
struct ESPState {
+ qemu_irq irq;
BlockDriverState **bd;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
s->rregs[4] = STAT_IN;
s->rregs[5] = INTR_DC;
s->rregs[6] = SEQ_0;
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
return 0;
}
s->current_dev = s->scsi_dev[target];
}
s->rregs[5] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD;
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
}
static void handle_satn(ESPState *s)
s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
s->rregs[5] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD;
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
}
}
s->ti_wptr = 0;
s->rregs[7] = 2;
}
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
}
static void esp_dma_done(ESPState *s)
s->rregs[7] = 0;
s->rregs[0] = 0;
s->rregs[1] = 0;
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
}
static void esp_do_dma(ESPState *s)
s->do_cmd = 0;
}
+static void parent_esp_reset(void *opaque, int irq, int level)
+{
+ if (level)
+ esp_reset(opaque);
+}
+
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
} else {
s->rregs[2] = s->ti_buf[s->ti_rptr++];
}
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
}
if (s->ti_size == 0) {
s->ti_rptr = 0;
// interrupt
// Clear interrupt/error status bits
s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
- espdma_clear_irq(s->dma_opaque);
+ qemu_irq_lower(s->irq);
break;
default:
break;
DPRINTF("Bus reset (%2.2x)\n", val);
s->rregs[5] = INTR_RST;
if (!(s->wregs[8] & 0x40)) {
- espdma_raise_irq(s->dma_opaque);
+ qemu_irq_raise(s->irq);
}
break;
case 0x10:
DPRINTF("Set ATN & stop (%2.2x)\n", val);
handle_satn_stop(s);
break;
+ case 0x44:
+ DPRINTF("Enable selection (%2.2x)\n", val);
+ break;
default:
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
break;
}
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
- void *dma_opaque)
+ void *dma_opaque, qemu_irq irq, qemu_irq *reset)
{
ESPState *s;
int esp_io_memory;
return NULL;
s->bd = bd;
+ s->irq = irq;
s->dma_opaque = dma_opaque;
- sparc32_dma_set_reset_data(dma_opaque, esp_reset, s);
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
cpu_register_physical_memory(espaddr, ESP_SIZE, esp_io_memory);
register_savevm("esp", espaddr, 3, esp_save, esp_load, s);
qemu_register_reset(esp_reset, s);
+ *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
+
return s;
}