* In addition to Crystal CS4231 there is a DMA controller on Sparc.
*/
#define CS_MAXADDR 0x3f
+#define CS_SIZE (CS_MAXADDR + 1)
#define CS_REGS 16
#define CS_DREGS 32
#define CS_MAXDREG (CS_DREGS - 1)
break;
}
DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
- break;
+ break;
default:
ret = s->regs[saddr];
DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
- break;
+ break;
}
return ret;
}
break;
default:
s->regs[saddr] = val;
- break;
+ break;
}
}
return;
cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
- cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);
+ cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
register_savevm("cs4231", base, 1, cs_save, cs_load, s);
qemu_register_reset(cs_reset, s);
cs_reset(s);