-/*
+/*
* ARM AMBA Generic/Distributed Interrupt Controller
*
* Copyright (c) 2006 CodeSourcery.
gic_state *s = (gic_state *)opaque;
/* The first external input line is internal interrupt 32. */
irq += 32;
- if (level == GIC_TEST_LEVEL(irq))
+ if (level == GIC_TEST_LEVEL(irq))
return;
if (level) {
case 0x18: /* Highest Pending Interrupt */
return s->current_pending;
default:
- cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "gic_cpu_read: Bad offset %x\n", offset);
return 0;
}
}
case 0x10: /* End Of Interrupt */
return gic_complete_irq(s, value & 0x3ff);
default:
- cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "gic_cpu_write: Bad offset %x\n", offset);
return;
}
gic_update(s);
if (base != 0xffffffff) {
iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
gic_cpu_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
+ cpu_register_physical_memory(base, 0x00001000, iomemtype);
iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
gic_dist_writefn, s);
- cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype);
+ cpu_register_physical_memory(base + 0x1000, 0x00001000, iomemtype);
s->base = base;
} else {
s->base = 0;