Add PowerPC power-management state check callback.

[qemu] / hw / apic.c

diff --git a/hw/apic.c b/hw/apic.c
index bbe44fa..3a442bf 100644 (file)
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -222,7 +222,7 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
             foreach_apic(apic_iter, deliver_bitmask,
                          apic_init_ipi(apic_iter) );
             return;
-   
+
         case APIC_DM_EXTINT:
             /* handled in I/O APIC code */
             break;
@@ -471,7 +471,7 @@ int apic_get_interrupt(CPUState *env)
         return -1;
     if (!(s->spurious_vec & APIC_SV_ENABLE))
         return -1;
-   
+
     /* XXX: spurious IRQ handling */
     intno = get_highest_priority_int(s->irr);
     if (intno < 0)
@@ -484,6 +484,25 @@ int apic_get_interrupt(CPUState *env)
     return intno;
 }
 
+int apic_accept_pic_intr(CPUState *env)
+{
+    APICState *s = env->apic_state;
+    uint32_t lvt0;
+
+    if (!s)
+        return -1;
+
+    lvt0 = s->lvt[APIC_LVT_LINT0];
+
+    if (s->id == 0 &&
+        ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
+         ((lvt0 & APIC_LVT_MASKED) == 0 &&
+          ((lvt0 >> 8) & 0x7) == APIC_DM_EXTINT)))
+        return 1;
+
+    return 0;
+}
+
 static uint32_t apic_get_current_count(APICState *s)
 {
     int64_t d;
@@ -505,7 +524,7 @@ static uint32_t apic_get_current_count(APICState *s)
 static void apic_timer_update(APICState *s, int64_t current_time)
 {
     int64_t next_time, d;
-   
+
     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
         d = (current_time - s->initial_count_load_time) >>
             s->count_shift;
@@ -790,6 +809,13 @@ static void apic_reset(void *opaque)
 {
     APICState *s = opaque;
     apic_init_ipi(s);
+
+    /*
+     * LINT0 delivery mode is set to ExtInt at initialization time
+     * typically by BIOS, so PIC interrupt can be delivered to the
+     * processor when local APIC is enabled.
+     */
+    s->lvt[APIC_LVT_LINT0] = 0x700;
 }
 
 static CPUReadMemoryFunc *apic_mem_read[3] = {
@@ -821,6 +847,13 @@ int apic_init(CPUState *env)
     s->apicbase = 0xfee00000 |
         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 
+    /*
+     * LINT0 delivery mode is set to ExtInt at initialization time
+     * typically by BIOS, so PIC interrupt can be delivered to the
+     * processor when local APIC is enabled.
+     */
+    s->lvt[APIC_LVT_LINT0] = 0x700;
+
     /* XXX: mapping more APICs at the same memory location */
     if (apic_io_memory == 0) {
         /* NOTE: the APIC is directly connected to the CPU - it is not
@@ -834,7 +867,7 @@ int apic_init(CPUState *env)
 
     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
     qemu_register_reset(apic_reset, s);
-   
+
     local_apics[s->id] = s;
     return 0;
 }
@@ -868,7 +901,7 @@ static void ioapic_service(IOAPICState *s)
                     vector = pic_read_irq(isa_pic);
                 else
                     vector = entry & 0xff;
-               
+
                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
                 apic_bus_deliver(deliver_bitmask, delivery_mode,
                                  vector, polarity, trig_mode);
@@ -1042,6 +1075,6 @@ IOAPICState *ioapic_init(void)
 
     register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
     qemu_register_reset(ioapic_reset, s);
-   
+
     return s;
 }