* QEMU Ultrasparc APB PCI host
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
};
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint32_t val)
{
//PCIBus *s = opaque;
case 0x18: // AFAR
case 0x20: // Diagnostic
case 0x28: // Target address space
- // XXX
+ // XXX
default:
- break;
+ break;
}
}
static uint32_t apb_config_readl (void *opaque,
- target_phys_addr_t addr)
+ target_phys_addr_t addr)
{
//PCIBus *s = opaque;
uint32_t val;
case 0x18: // AFAR
case 0x20: // Diagnostic
case 0x28: // Target address space
- // XXX
+ // XXX
default:
- val = 0;
- break;
+ val = 0;
+ break;
}
return val;
}
return bus_offset + irq_num;
}
-static void pci_apb_set_irq(void *pic, int irq_num, int level)
+static void pci_apb_set_irq(qemu_irq *pic, int irq_num, int level)
{
/* PCI IRQ map onto the first 32 INO. */
- pic_set_irq_new(pic, irq_num, level);
+ qemu_set_irq(pic[irq_num], level);
}
-PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
- void *pic)
+PCIBus *pci_apb_init(target_phys_addr_t special_base,
+ target_phys_addr_t mem_base,
+ qemu_irq *pic)
{
APBState *s;
PCIDevice *d;
int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
- PCIDevice *apb;
PCIBus *secondary;
s = qemu_mallocz(sizeof(APBState));
pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
pci_apb_config_write, s);
apb_config = cpu_register_io_memory(0, apb_config_read,
- apb_config_write, s);
+ apb_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
pci_apb_write, s);
pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
- d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
+ d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
0, NULL, NULL);
d->config[0x00] = 0x8e; // vendor_id : Sun
d->config[0x01] = 0x10;