extern FILE *logfile;
extern int loglevel;
+void muls64(int64_t *phigh, int64_t *plow, int64_t a, int64_t b);
+void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
+
int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
-#ifdef __powerpc__
+#if defined(__powerpc__)
static inline int testandset (int *p)
{
int ret;
: "cr0", "memory");
return ret;
}
-#endif
-
-#ifdef __i386__
+#elif defined(__i386__)
static inline int testandset (int *p)
{
long int readval = 0;
: "cc");
return readval;
}
-#endif
-
-#ifdef __x86_64__
+#elif defined(__x86_64__)
static inline int testandset (int *p)
{
long int readval = 0;
: "cc");
return readval;
}
-#endif
-
-#ifdef __s390__
+#elif defined(__s390__)
static inline int testandset (int *p)
{
int ret;
: "cc", "memory" );
return ret;
}
-#endif
-
-#ifdef __alpha__
+#elif defined(__alpha__)
static inline int testandset (int *p)
{
int ret;
: "m" (*p));
return ret;
}
-#endif
-
-#ifdef __sparc__
+#elif defined(__sparc__)
static inline int testandset (int *p)
{
int ret;
return (ret ? 1 : 0);
}
-#endif
-
-#ifdef __arm__
+#elif defined(__arm__)
static inline int testandset (int *spinlock)
{
register unsigned int ret;
return ret;
}
-#endif
-
-#ifdef __mc68000
+#elif defined(__mc68000)
static inline int testandset (int *p)
{
char ret;
: "cc","memory");
return ret;
}
-#endif
+#elif defined(__ia64)
-#ifdef __ia64
#include <ia64intrin.h>
static inline int testandset (int *p)
{
return __sync_lock_test_and_set (p, 1);
}
+#elif defined(__mips__)
+static inline int testandset (int *p)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ " .set push \n"
+ " .set noat \n"
+ " .set mips2 \n"
+ "1: li $1, 1 \n"
+ " ll %0, %1 \n"
+ " sc $1, %1 \n"
+ " beqz $1, 1b \n"
+ " .set pop "
+ : "=r" (ret), "+R" (*p)
+ :
+ : "memory");
+
+ return ret;
+}
+#else
+#error unimplemented CPU support
#endif
typedef int spinlock_t;
is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
#elif defined (TARGET_SH4)
is_user = ((env->sr & SR_MD) == 0);
+#elif defined (TARGET_ALPHA)
+ is_user = ((env->ps >> 3) & 3);
#else
#error unimplemented CPU
#endif
}
pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
- cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
+#ifdef TARGET_SPARC
+ do_unassigned_access(addr, 0, 1, 0);
+#else
+ cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
+#endif
}
return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif
-
#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))