projects
/
qemu
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Add PowerPC power-management state check callback.
[qemu]
/
hw
/
piix_pci.c
diff --git
a/hw/piix_pci.c
b/hw/piix_pci.c
index
095698c
..
3c04e3a
100644
(file)
--- a/
hw/piix_pci.c
+++ b/
hw/piix_pci.c
@@
-2,7
+2,7
@@
* QEMU i440FX/PIIX3 PCI Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
* QEMU i440FX/PIIX3 PCI Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@
-63,19
+63,19
@@
static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
switch(r) {
case 3:
/* RAM */
switch(r) {
case 3:
/* RAM */
- cpu_register_physical_memory(start, end - start,
+ cpu_register_physical_memory(start, end - start,
start);
break;
case 1:
/* ROM (XXX: not quite correct) */
start);
break;
case 1:
/* ROM (XXX: not quite correct) */
- cpu_register_physical_memory(start, end - start,
+ cpu_register_physical_memory(start, end - start,
start | IO_MEM_ROM);
break;
case 2:
case 0:
/* XXX: should distinguish read/write cases */
for(addr = start; addr < end; addr += 4096) {
start | IO_MEM_ROM);
break;
case 2:
case 0:
/* XXX: should distinguish read/write cases */
for(addr = start; addr < end; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
+ cpu_register_physical_memory(addr, 4096,
isa_page_descs[(addr - 0xa0000) >> 12]);
}
break;
isa_page_descs[(addr - 0xa0000) >> 12]);
}
break;
@@
-97,7
+97,7
@@
static void i440fx_update_memory_mappings(PCIDevice *d)
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
} else {
for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
} else {
for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
+ cpu_register_physical_memory(addr, 4096,
isa_page_descs[(addr - 0xa0000) >> 12]);
}
}
isa_page_descs[(addr - 0xa0000) >> 12]);
}
}
@@
-124,7
+124,7
@@
void i440fx_init_memory_mappings(PCIDevice *d)
}
}
}
}
-static void i440fx_write_config(PCIDevice *d,
+static void i440fx_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
/* XXX: implement SMRAM.D_LOCK */
uint32_t address, uint32_t val, int len)
{
/* XXX: implement SMRAM.D_LOCK */
@@
-175,7
+175,7
@@
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
- d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
+ d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
NULL, i440fx_write_config);
d->config[0x00] = 0x86; // vendor_id
NULL, i440fx_write_config);
d->config[0x00] = 0x86; // vendor_id
@@
-208,6
+208,7
@@
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
{
int i, pic_irq, pic_level;
{
int i, pic_irq, pic_level;
+ piix3_dev->config[0x60 + irq_num] &= ~0x80; // enable bit
pci_irq_levels[irq_num] = level;
/* now we change the pic irq level according to the piix irq mappings */
pci_irq_levels[irq_num] = level;
/* now we change the pic irq level according to the piix irq mappings */