2 * QEMU PC System Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
43 #include <sys/ioctl.h>
44 #include <sys/socket.h>
46 #include <linux/if_tun.h>
54 #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup"
55 #define BIOS_FILENAME "bios.bin"
56 #define VGABIOS_FILENAME "vgabios.bin"
58 //#define DEBUG_UNUSED_IOPORT
60 //#define DEBUG_IRQ_LATENCY
62 /* output Bochs bios info messages */
70 /* debug NE2000 card */
71 //#define DEBUG_NE2000
73 /* debug PC keyboard */
76 /* debug PC keyboard : only mouse */
79 //#define DEBUG_SERIAL
81 #define PHYS_RAM_BASE 0xac000000
82 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
84 #if defined (TARGET_I386)
85 #define KERNEL_LOAD_ADDR 0x00100000
86 #elif defined (TARGET_PPC)
87 //#define USE_OPEN_FIRMWARE
88 #if defined (USE_OPEN_FIRMWARE)
89 #define KERNEL_LOAD_ADDR 0x01000000
90 #define KERNEL_STACK_ADDR 0x01200000
92 #define KERNEL_LOAD_ADDR 0x00000000
93 #define KERNEL_STACK_ADDR 0x00400000
96 #define INITRD_LOAD_ADDR 0x00400000
97 #define KERNEL_PARAMS_ADDR 0x00090000
99 #define GUI_REFRESH_INTERVAL 30
101 /* from plex86 (BSD license) */
102 struct __attribute__ ((packed)) linux_params {
103 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
104 // I just padded out the VESA parts, rather than define them.
106 /* 0x000 */ uint8_t orig_x;
107 /* 0x001 */ uint8_t orig_y;
108 /* 0x002 */ uint16_t ext_mem_k;
109 /* 0x004 */ uint16_t orig_video_page;
110 /* 0x006 */ uint8_t orig_video_mode;
111 /* 0x007 */ uint8_t orig_video_cols;
112 /* 0x008 */ uint16_t unused1;
113 /* 0x00a */ uint16_t orig_video_ega_bx;
114 /* 0x00c */ uint16_t unused2;
115 /* 0x00e */ uint8_t orig_video_lines;
116 /* 0x00f */ uint8_t orig_video_isVGA;
117 /* 0x010 */ uint16_t orig_video_points;
118 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
119 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
120 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
121 // is calculated as 0x90000 + cl_offset, bu
122 // only if cl_magic == 0xA33F.
123 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
125 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
126 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
128 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
129 // Might be truncated?
130 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
131 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
133 // System description table truncated to 16 bytes
134 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
135 /* 0x0a0 */ uint16_t sys_description_len;
136 /* 0x0a2 */ uint8_t sys_description_table[14];
138 // [1] machine submodel id
142 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
143 /* 0x1e0 */ uint32_t alt_mem_k;
144 /* 0x1e4 */ uint8_t pad4[4];
145 /* 0x1e8 */ uint8_t e820map_entries;
146 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
147 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
148 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
149 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
150 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
151 // (b)zImage-file (in 16 byte units, rounded up)
152 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
153 /* 0x1f8 */ uint16_t ramdisk_flags;
154 /* 0x1fa */ uint16_t vga_mode; // (old one)
155 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
156 /* 0x1fe */ uint8_t pad6[1];
157 /* 0x1ff */ uint8_t aux_device_info;
158 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
159 // aka "reserved" field.
160 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
161 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
162 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
163 // boot loaders, look there.
164 /* 0x210 */ uint8_t loader_type;
169 // T=2: bootsect-loader
173 /* 0x211 */ uint8_t loadflags;
174 // bit0 = 1: kernel is loaded high (bzImage)
175 // bit7 = 1: Heap and pointer (see below) set by boot
177 /* 0x212 */ uint16_t setup_S_temp1;
178 /* 0x214 */ uint32_t kernel_start;
179 /* 0x218 */ uint32_t initrd_start;
180 /* 0x21c */ uint32_t initrd_size;
181 /* 0x220 */ uint8_t setup_S_temp2[4];
182 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
183 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
185 /* 0x2d0 : Int 15, ax=e820 memory map. */
186 // (linux/include/asm-i386/e820.h, 'struct e820entry')
189 #define E820_RESERVED 2
190 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
198 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
200 // BIOS Enhanced Disk Drive Services.
201 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
202 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
203 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
205 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
206 /* 0x800 */ uint8_t commandline[0x800];
209 uint64_t gdt_table[256];
210 uint64_t idt_table[48];
213 #define KERNEL_CS 0x10
214 #define KERNEL_DS 0x18
216 /* XXX: use a two level table to limit memory usage */
217 #define MAX_IOPORTS 65536
219 static const char *bios_dir = CONFIG_QEMU_SHAREDIR;
220 char phys_ram_file[1024];
221 CPUState *global_env;
222 CPUState *cpu_single_env;
223 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
224 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
225 BlockDriverState *bs_table[MAX_DISKS], *fd_table[MAX_FD];
227 static DisplayState display_state;
230 int64_t ticks_per_sec;
231 int boot_device = 'c';
233 /***********************************************************/
236 uint32_t default_ioport_readb(CPUState *env, uint32_t address)
238 #ifdef DEBUG_UNUSED_IOPORT
239 fprintf(stderr, "inb: port=0x%04x\n", address);
244 void default_ioport_writeb(CPUState *env, uint32_t address, uint32_t data)
246 #ifdef DEBUG_UNUSED_IOPORT
247 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
251 /* default is to make two byte accesses */
252 uint32_t default_ioport_readw(CPUState *env, uint32_t address)
255 data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
256 data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
260 void default_ioport_writew(CPUState *env, uint32_t address, uint32_t data)
262 ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
263 ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
266 uint32_t default_ioport_readl(CPUState *env, uint32_t address)
268 #ifdef DEBUG_UNUSED_IOPORT
269 fprintf(stderr, "inl: port=0x%04x\n", address);
274 void default_ioport_writel(CPUState *env, uint32_t address, uint32_t data)
276 #ifdef DEBUG_UNUSED_IOPORT
277 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
281 void init_ioports(void)
285 for(i = 0; i < MAX_IOPORTS; i++) {
286 ioport_read_table[0][i] = default_ioport_readb;
287 ioport_write_table[0][i] = default_ioport_writeb;
288 ioport_read_table[1][i] = default_ioport_readw;
289 ioport_write_table[1][i] = default_ioport_writew;
290 ioport_read_table[2][i] = default_ioport_readl;
291 ioport_write_table[2][i] = default_ioport_writel;
295 /* size is the word size in byte */
296 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
308 for(i = start; i < start + length; i += size)
309 ioport_read_table[bsize][i] = func;
313 /* size is the word size in byte */
314 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
326 for(i = start; i < start + length; i += size)
327 ioport_write_table[bsize][i] = func;
331 void pstrcpy(char *buf, int buf_size, const char *str)
341 if (c == 0 || q >= buf + buf_size - 1)
348 /* strcat and truncate. */
349 char *pstrcat(char *buf, int buf_size, const char *s)
354 pstrcpy(buf + len, buf_size - len, s);
358 int load_kernel(const char *filename, uint8_t *addr)
361 #if defined (TARGET_I386)
363 uint8_t bootsect[512];
366 printf("Load kernel at %p (0x%08x)\n", addr,
367 (uint32_t)addr - (uint32_t)phys_ram_base);
368 fd = open(filename, O_RDONLY);
371 #if defined (TARGET_I386)
372 if (read(fd, bootsect, 512) != 512)
374 setup_sects = bootsect[0x1F1];
377 /* skip 16 bit setup code */
378 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
380 size = read(fd, addr, 16 * 1024 * 1024);
390 /* return the size or -1 if error */
391 int load_image(const char *filename, uint8_t *addr)
394 fd = open(filename, O_RDONLY);
397 size = lseek(fd, 0, SEEK_END);
398 lseek(fd, 0, SEEK_SET);
399 if (read(fd, addr, size) != size) {
407 void cpu_outb(CPUState *env, int addr, int val)
409 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
412 void cpu_outw(CPUState *env, int addr, int val)
414 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
417 void cpu_outl(CPUState *env, int addr, int val)
419 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
422 int cpu_inb(CPUState *env, int addr)
424 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
427 int cpu_inw(CPUState *env, int addr)
429 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
432 int cpu_inl(CPUState *env, int addr)
434 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
437 /***********************************************************/
438 void ioport80_write(CPUState *env, uint32_t addr, uint32_t data)
442 void hw_error(const char *fmt, ...)
447 fprintf(stderr, "qemu: hardware error: ");
448 vfprintf(stderr, fmt, ap);
449 fprintf(stderr, "\n");
451 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
453 cpu_dump_state(global_env, stderr, 0);
459 /***********************************************************/
462 #if defined (TARGET_I386)
463 #define RTC_SECONDS 0
464 #define RTC_SECONDS_ALARM 1
465 #define RTC_MINUTES 2
466 #define RTC_MINUTES_ALARM 3
468 #define RTC_HOURS_ALARM 5
469 #define RTC_ALARM_DONT_CARE 0xC0
471 #define RTC_DAY_OF_WEEK 6
472 #define RTC_DAY_OF_MONTH 7
481 /* PC cmos mappings */
482 #define REG_EQUIPMENT_BYTE 0x14
483 #define REG_IBM_CENTURY_BYTE 0x32
485 uint8_t cmos_data[128];
488 void cmos_ioport_write(CPUState *env, uint32_t addr, uint32_t data)
491 cmos_index = data & 0x7f;
494 printf("cmos: write index=0x%02x val=0x%02x\n",
498 case RTC_SECONDS_ALARM:
499 case RTC_MINUTES_ALARM:
500 case RTC_HOURS_ALARM:
501 /* XXX: not supported */
502 cmos_data[cmos_index] = data;
507 case RTC_DAY_OF_WEEK:
508 case RTC_DAY_OF_MONTH:
511 cmos_data[cmos_index] = data;
515 cmos_data[cmos_index] = data;
519 /* cannot write to them */
522 cmos_data[cmos_index] = data;
528 uint32_t cmos_ioport_read(CPUState *env, uint32_t addr)
535 ret = cmos_data[cmos_index];
538 /* toggle update-in-progress bit for Linux (same hack as
540 cmos_data[RTC_REG_A] ^= 0x80;
544 cmos_data[RTC_REG_C] = 0x00;
548 printf("cmos: read index=0x%02x val=0x%02x\n",
556 static inline int to_bcd(int a)
558 return ((a / 10) << 4) | (a % 10);
569 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
570 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
571 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
572 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
573 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
574 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
575 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
577 cmos_data[RTC_REG_A] = 0x26;
578 cmos_data[RTC_REG_B] = 0x02;
579 cmos_data[RTC_REG_C] = 0x00;
580 cmos_data[RTC_REG_D] = 0x80;
582 /* various important CMOS locations needed by PC/Bochs bios */
583 cmos_data[REG_IBM_CENTURY_BYTE] = to_bcd((tm->tm_year / 100) + 19);
585 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
586 cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
589 val = (phys_ram_size / 1024) - 1024;
592 cmos_data[0x17] = val;
593 cmos_data[0x18] = val >> 8;
594 cmos_data[0x30] = val;
595 cmos_data[0x31] = val >> 8;
597 val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
600 cmos_data[0x34] = val;
601 cmos_data[0x35] = val >> 8;
603 switch(boot_device) {
606 cmos_data[0x3d] = 0x01; /* floppy boot */
610 cmos_data[0x3d] = 0x02; /* hard drive boot */
613 cmos_data[0x3d] = 0x03; /* CD-ROM boot */
617 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
618 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
621 void cmos_register_fd (uint8_t fd0, uint8_t fd1)
628 /* 1.44 Mb 3"5 drive */
629 cmos_data[0x10] |= 0x40;
632 /* 2.88 Mb 3"5 drive */
633 cmos_data[0x10] |= 0x60;
636 /* 1.2 Mb 5"5 drive */
637 cmos_data[0x10] |= 0x20;
642 /* 1.44 Mb 3"5 drive */
643 cmos_data[0x10] |= 0x04;
646 /* 2.88 Mb 3"5 drive */
647 cmos_data[0x10] |= 0x06;
650 /* 1.2 Mb 5"5 drive */
651 cmos_data[0x10] |= 0x02;
662 cmos_data[REG_EQUIPMENT_BYTE] |= 0x01; /* 1 drive, ready for boot */
665 cmos_data[REG_EQUIPMENT_BYTE] |= 0x41; /* 2 drives, ready for boot */
669 #endif /* TARGET_I386 */
671 /***********************************************************/
672 /* 8259 pic emulation */
674 typedef struct PicState {
675 uint8_t last_irr; /* edge detection */
676 uint8_t irr; /* interrupt request register */
677 uint8_t imr; /* interrupt mask register */
678 uint8_t isr; /* interrupt service register */
679 uint8_t priority_add; /* used to compute irq priority */
681 uint8_t read_reg_select;
683 uint8_t special_mask;
686 uint8_t rotate_on_autoeoi;
687 uint8_t init4; /* true if 4 byte init */
690 /* 0 is master pic, 1 is slave pic */
692 int pic_irq_requested;
694 /* set irq level. If an edge is detected, then the IRR is set to 1 */
695 static inline void pic_set_irq1(PicState *s, int irq, int level)
700 if ((s->last_irr & mask) == 0)
704 s->last_irr &= ~mask;
708 static inline int get_priority(PicState *s, int mask)
714 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
719 /* return the pic wanted interrupt. return -1 if none */
720 static int pic_get_irq(PicState *s)
722 int mask, cur_priority, priority;
724 mask = s->irr & ~s->imr;
725 priority = get_priority(s, mask);
728 /* compute current priority */
729 cur_priority = get_priority(s, s->isr);
730 if (priority > cur_priority) {
731 /* higher priority found: an irq should be generated */
738 /* raise irq to CPU if necessary. must be called every time the active
740 void pic_update_irq(void)
744 /* first look at slave pic */
745 irq2 = pic_get_irq(&pics[1]);
747 /* if irq request by slave pic, signal master PIC */
748 pic_set_irq1(&pics[0], 2, 1);
749 pic_set_irq1(&pics[0], 2, 0);
751 /* look at requested irq */
752 irq = pic_get_irq(&pics[0]);
756 pic_irq_requested = 8 + irq2;
758 /* from master pic */
759 pic_irq_requested = irq;
761 cpu_interrupt(global_env, CPU_INTERRUPT_HARD);
765 #ifdef DEBUG_IRQ_LATENCY
766 int64_t irq_time[16];
767 int64_t cpu_get_ticks(void);
769 #if defined(DEBUG_PIC)
773 void pic_set_irq(int irq, int level)
775 #if defined(DEBUG_PIC)
776 if (level != irq_level[irq]) {
777 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
778 irq_level[irq] = level;
781 #ifdef DEBUG_IRQ_LATENCY
783 irq_time[irq] = cpu_get_ticks();
786 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
790 int cpu_x86_get_pic_interrupt(CPUState *env)
792 int irq, irq2, intno;
794 /* signal the pic that the irq was acked by the CPU */
795 irq = pic_irq_requested;
796 #ifdef DEBUG_IRQ_LATENCY
797 printf("IRQ%d latency=%0.3fus\n",
799 (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
801 #if defined(DEBUG_PIC)
802 printf("pic_interrupt: irq=%d\n", irq);
807 pics[1].isr |= (1 << irq2);
808 pics[1].irr &= ~(1 << irq2);
810 intno = pics[1].irq_base + irq2;
812 intno = pics[0].irq_base + irq;
814 pics[0].isr |= (1 << irq);
815 pics[0].irr &= ~(1 << irq);
819 void pic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
825 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
827 s = &pics[addr >> 7];
832 memset(s, 0, sizeof(PicState));
836 hw_error("single mode not supported");
838 hw_error("level sensitive irq not supported");
839 } else if (val & 0x08) {
844 s->read_reg_select = val & 1;
846 s->special_mask = (val >> 5) & 1;
852 s->rotate_on_autoeoi = val >> 7;
854 case 0x20: /* end of interrupt */
856 priority = get_priority(s, s->isr);
858 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
861 s->priority_add = (s->priority_add + 1) & 7;
866 s->isr &= ~(1 << priority);
870 s->priority_add = (val + 1) & 7;
875 s->isr &= ~(1 << priority);
876 s->priority_add = (priority + 1) & 7;
882 switch(s->init_state) {
889 s->irq_base = val & 0xf8;
900 s->auto_eoi = (val >> 1) & 1;
907 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
911 ret = pic_get_irq(s);
914 pics[0].isr &= ~(1 << 2);
915 pics[0].irr &= ~(1 << 2);
917 s->irr &= ~(1 << ret);
918 s->isr &= ~(1 << ret);
919 if (addr1 >> 7 || ret != 2)
929 uint32_t pic_ioport_read(CPUState *env, uint32_t addr1)
936 s = &pics[addr >> 7];
939 ret = pic_poll_read(s, addr1);
943 if (s->read_reg_select)
952 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
957 /* memory mapped interrupt status */
958 uint32_t pic_intack_read(CPUState *env)
962 ret = pic_poll_read(&pics[0], 0x00);
964 ret = pic_poll_read(&pics[1], 0x80) + 8;
965 /* Prepare for ISR read */
966 pics[0].read_reg_select = 1;
973 #if defined (TARGET_I386) || defined (TARGET_PPC)
974 register_ioport_write(0x20, 2, pic_ioport_write, 1);
975 register_ioport_read(0x20, 2, pic_ioport_read, 1);
976 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
977 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
981 /***********************************************************/
982 /* 8253 PIT emulation */
984 #define PIT_FREQ 1193182
986 #define RW_STATE_LSB 0
987 #define RW_STATE_MSB 1
988 #define RW_STATE_WORD0 2
989 #define RW_STATE_WORD1 3
990 #define RW_STATE_LATCHED_WORD0 4
991 #define RW_STATE_LATCHED_WORD1 5
993 typedef struct PITChannelState {
994 int count; /* can be 65536 */
995 uint16_t latched_count;
998 uint8_t bcd; /* not supported */
999 uint8_t gate; /* timer start */
1000 int64_t count_load_time;
1001 int64_t count_last_edge_check_time;
1004 PITChannelState pit_channels[3];
1005 int speaker_data_on;
1006 int dummy_refresh_clock;
1007 int pit_min_timer_count = 0;
1010 #if defined(__powerpc__)
1012 static inline uint32_t get_tbl(void)
1015 asm volatile("mftb %0" : "=r" (tbl));
1019 static inline uint32_t get_tbu(void)
1022 asm volatile("mftbu %0" : "=r" (tbl));
1026 int64_t cpu_get_real_ticks(void)
1029 /* NOTE: we test if wrapping has occurred */
1035 return ((int64_t)h << 32) | l;
1038 #elif defined(__i386__)
1040 int64_t cpu_get_real_ticks(void)
1043 asm("rdtsc" : "=A" (val));
1048 #error unsupported CPU
1051 static int64_t cpu_ticks_offset;
1052 static int64_t cpu_ticks_last;
1054 int64_t cpu_get_ticks(void)
1056 return cpu_get_real_ticks() + cpu_ticks_offset;
1059 /* enable cpu_get_ticks() */
1060 void cpu_enable_ticks(void)
1062 cpu_ticks_offset = cpu_ticks_last - cpu_get_real_ticks();
1065 /* disable cpu_get_ticks() : the clock is stopped. You must not call
1066 cpu_get_ticks() after that. */
1067 void cpu_disable_ticks(void)
1069 cpu_ticks_last = cpu_get_ticks();
1072 int64_t get_clock(void)
1075 gettimeofday(&tv, NULL);
1076 return tv.tv_sec * 1000000LL + tv.tv_usec;
1079 void cpu_calibrate_ticks(void)
1081 int64_t usec, ticks;
1084 ticks = cpu_get_ticks();
1086 usec = get_clock() - usec;
1087 ticks = cpu_get_ticks() - ticks;
1088 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
1091 /* compute with 96 bit intermediate result: (a*b)/c */
1092 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
1097 #ifdef WORDS_BIGENDIAN
1107 rl = (uint64_t)u.l.low * (uint64_t)b;
1108 rh = (uint64_t)u.l.high * (uint64_t)b;
1110 res.l.high = rh / c;
1111 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
1115 static int pit_get_count(PITChannelState *s)
1120 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
1126 counter = (s->count - d) & 0xffff;
1129 /* XXX: may be incorrect for odd counts */
1130 counter = s->count - ((2 * d) % s->count);
1133 counter = s->count - (d % s->count);
1139 /* get pit output bit */
1140 static int pit_get_out(PITChannelState *s)
1145 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
1149 out = (d >= s->count);
1152 out = (d < s->count);
1155 if ((d % s->count) == 0 && d != 0)
1161 out = (d % s->count) < ((s->count + 1) >> 1);
1165 out = (d == s->count);
1171 /* get the number of 0 to 1 transitions we had since we call this
1173 /* XXX: maybe better to use ticks precision to avoid getting edges
1174 twice if checks are done at very small intervals */
1175 static int pit_get_out_edges(PITChannelState *s)
1181 ticks = cpu_get_ticks();
1182 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
1183 PIT_FREQ, ticks_per_sec);
1184 d2 = muldiv64(ticks - s->count_load_time,
1185 PIT_FREQ, ticks_per_sec);
1186 s->count_last_edge_check_time = ticks;
1190 if (d1 < s->count && d2 >= s->count)
1204 v = s->count - ((s->count + 1) >> 1);
1205 d1 = (d1 + v) / s->count;
1206 d2 = (d2 + v) / s->count;
1211 if (d1 < s->count && d2 >= s->count)
1220 /* val must be 0 or 1 */
1221 static inline void pit_set_gate(PITChannelState *s, int val)
1227 /* XXX: just disable/enable counting */
1231 if (s->gate < val) {
1232 /* restart counting on rising edge */
1233 s->count_load_time = cpu_get_ticks();
1234 s->count_last_edge_check_time = s->count_load_time;
1239 if (s->gate < val) {
1240 /* restart counting on rising edge */
1241 s->count_load_time = cpu_get_ticks();
1242 s->count_last_edge_check_time = s->count_load_time;
1244 /* XXX: disable/enable counting */
1250 static inline void pit_load_count(PITChannelState *s, int val)
1254 s->count_load_time = cpu_get_ticks();
1255 s->count_last_edge_check_time = s->count_load_time;
1257 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
1259 "\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
1260 PIT_FREQ / pit_min_timer_count);
1264 void pit_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1266 int channel, access;
1274 s = &pit_channels[channel];
1275 access = (val >> 4) & 3;
1278 s->latched_count = pit_get_count(s);
1279 s->rw_state = RW_STATE_LATCHED_WORD0;
1282 s->mode = (val >> 1) & 7;
1284 s->rw_state = access - 1 + RW_STATE_LSB;
1288 s = &pit_channels[addr];
1289 switch(s->rw_state) {
1291 pit_load_count(s, val);
1294 pit_load_count(s, val << 8);
1296 case RW_STATE_WORD0:
1297 case RW_STATE_WORD1:
1298 if (s->rw_state & 1) {
1299 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
1301 s->latched_count = val;
1309 uint32_t pit_ioport_read(CPUState *env, uint32_t addr)
1315 s = &pit_channels[addr];
1316 switch(s->rw_state) {
1319 case RW_STATE_WORD0:
1320 case RW_STATE_WORD1:
1321 count = pit_get_count(s);
1322 if (s->rw_state & 1)
1323 ret = (count >> 8) & 0xff;
1326 if (s->rw_state & 2)
1330 case RW_STATE_LATCHED_WORD0:
1331 case RW_STATE_LATCHED_WORD1:
1332 if (s->rw_state & 1)
1333 ret = s->latched_count >> 8;
1335 ret = s->latched_count & 0xff;
1342 #if defined (TARGET_I386)
1343 void speaker_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1345 speaker_data_on = (val >> 1) & 1;
1346 pit_set_gate(&pit_channels[2], val & 1);
1349 uint32_t speaker_ioport_read(CPUState *env, uint32_t addr)
1352 out = pit_get_out(&pit_channels[2]);
1353 dummy_refresh_clock ^= 1;
1354 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
1355 (dummy_refresh_clock << 4);
1364 cpu_calibrate_ticks();
1366 for(i = 0;i < 3; i++) {
1367 s = &pit_channels[i];
1370 pit_load_count(s, 0);
1373 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1374 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1376 #if defined (TARGET_I386)
1377 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1378 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1382 /***********************************************************/
1383 /* serial port emulation */
1387 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1389 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1390 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1391 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1392 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1394 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1395 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1397 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1398 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1399 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1400 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1403 * These are the definitions for the Modem Control Register
1405 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1406 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1407 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1408 #define UART_MCR_RTS 0x02 /* RTS complement */
1409 #define UART_MCR_DTR 0x01 /* DTR complement */
1412 * These are the definitions for the Modem Status Register
1414 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1415 #define UART_MSR_RI 0x40 /* Ring Indicator */
1416 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1417 #define UART_MSR_CTS 0x10 /* Clear to Send */
1418 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1419 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1420 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1421 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1422 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1424 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1425 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1426 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1427 #define UART_LSR_FE 0x08 /* Frame error indicator */
1428 #define UART_LSR_PE 0x04 /* Parity error indicator */
1429 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1430 #define UART_LSR_DR 0x01 /* Receiver data ready */
1432 typedef struct SerialState {
1434 uint8_t rbr; /* receive register */
1436 uint8_t iir; /* read only */
1439 uint8_t lsr; /* read only */
1442 /* NOTE: this hidden state is necessary for tx irq generation as
1443 it can be reset while reading iir */
1447 SerialState serial_ports[1];
1449 void serial_update_irq(void)
1451 SerialState *s = &serial_ports[0];
1453 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1454 s->iir = UART_IIR_RDI;
1455 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
1456 s->iir = UART_IIR_THRI;
1458 s->iir = UART_IIR_NO_INT;
1460 if (s->iir != UART_IIR_NO_INT) {
1461 pic_set_irq(UART_IRQ, 1);
1463 pic_set_irq(UART_IRQ, 0);
1467 void serial_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
1469 SerialState *s = &serial_ports[0];
1475 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
1480 if (s->lcr & UART_LCR_DLAB) {
1481 s->divider = (s->divider & 0xff00) | val;
1483 s->thr_ipending = 0;
1484 s->lsr &= ~UART_LSR_THRE;
1485 serial_update_irq();
1489 ret = write(1, &ch, 1);
1491 s->thr_ipending = 1;
1492 s->lsr |= UART_LSR_THRE;
1493 s->lsr |= UART_LSR_TEMT;
1494 serial_update_irq();
1498 if (s->lcr & UART_LCR_DLAB) {
1499 s->divider = (s->divider & 0x00ff) | (val << 8);
1502 serial_update_irq();
1524 uint32_t serial_ioport_read(CPUState *env, uint32_t addr)
1526 SerialState *s = &serial_ports[0];
1533 if (s->lcr & UART_LCR_DLAB) {
1534 ret = s->divider & 0xff;
1537 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1538 serial_update_irq();
1542 if (s->lcr & UART_LCR_DLAB) {
1543 ret = (s->divider >> 8) & 0xff;
1550 /* reset THR pending bit */
1551 if ((ret & 0x7) == UART_IIR_THRI)
1552 s->thr_ipending = 0;
1553 serial_update_irq();
1565 if (s->mcr & UART_MCR_LOOP) {
1566 /* in loopback, the modem output pins are connected to the
1568 ret = (s->mcr & 0x0c) << 4;
1569 ret |= (s->mcr & 0x02) << 3;
1570 ret |= (s->mcr & 0x01) << 5;
1580 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
1585 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1586 static int term_got_escape, term_command;
1587 static unsigned char term_cmd_buf[128];
1589 typedef struct term_cmd_t {
1590 const unsigned char *name;
1591 void (*handler)(unsigned char *params);
1594 static void do_change_cdrom (unsigned char *params);
1595 static void do_change_fd0 (unsigned char *params);
1596 static void do_change_fd1 (unsigned char *params);
1598 static term_cmd_t term_cmds[] = {
1599 { "changecd", &do_change_cdrom, },
1600 { "changefd0", &do_change_fd0, },
1601 { "changefd1", &do_change_fd1, },
1605 void term_print_help(void)
1608 "C-a h print this help\n"
1609 "C-a x exit emulatior\n"
1610 "C-a d switch on/off debug log\n"
1611 "C-a s save disk data back to file (if -snapshot)\n"
1612 "C-a b send break (magic sysrq)\n"
1613 "C-a c send qemu internal command\n"
1614 "C-a C-a send C-a\n"
1618 static void do_change_cdrom (unsigned char *params)
1620 /* Dunno how to do it... */
1623 static void do_change_fd (int fd, unsigned char *params)
1625 unsigned char *name_start, *name_end, *ros;
1628 for (name_start = params;
1629 isspace(*name_start); name_start++)
1631 if (*name_start == '\0')
1633 for (name_end = name_start;
1634 !isspace(*name_end) && *name_end != '\0'; name_end++)
1636 for (ros = name_end + 1; isspace(*ros); ros++)
1638 if (ros[0] == 'r' && ros[1] == 'o')
1643 printf("Change fd %d to %s (%s)\n", fd, name_start, params);
1644 fdctrl_disk_change(fd, name_start, ro);
1647 static void do_change_fd0 (unsigned char *params)
1649 do_change_fd(0, params);
1652 static void do_change_fd1 (unsigned char *params)
1654 do_change_fd(1, params);
1657 static void serial_treat_command ()
1659 unsigned char *cmd_start, *cmd_end;
1662 for (cmd_start = term_cmd_buf; isspace(*cmd_start); cmd_start++)
1664 for (cmd_end = cmd_start;
1665 !isspace(*cmd_end) && *cmd_end != '\0'; cmd_end++)
1667 for (i = 0; term_cmds[i].name != NULL; i++) {
1668 if (strlen(term_cmds[i].name) == (cmd_end - cmd_start) &&
1669 memcmp(term_cmds[i].name, cmd_start, cmd_end - cmd_start) == 0) {
1670 (*term_cmds[i].handler)(cmd_end + 1);
1675 printf("Unknown term command: %s\n", cmd_start);
1678 extern FILE *logfile;
1680 /* called when a char is received */
1681 void serial_received_byte(SerialState *s, int ch)
1684 if (ch == '\n' || ch == '\r' || term_command == 127) {
1686 serial_treat_command();
1689 if (ch == 0x7F || ch == 0x08) {
1690 if (term_command > 1) {
1691 term_cmd_buf[--term_command - 1] = '\0';
1694 printf("\r> %s", term_cmd_buf);
1696 } else if (ch > 0x1f) {
1697 term_cmd_buf[term_command++ - 1] = ch;
1698 term_cmd_buf[term_command - 1] = '\0';
1699 printf("\r> %s", term_cmd_buf);
1703 } else if (term_got_escape) {
1704 term_got_escape = 0;
1715 for (i = 0; i < MAX_DISKS; i++) {
1717 bdrv_commit(bs_table[i]);
1724 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1725 serial_update_irq();
1735 } else if (ch == TERM_ESCAPE) {
1736 term_got_escape = 1;
1740 s->lsr |= UART_LSR_DR;
1741 serial_update_irq();
1745 void serial_init(void)
1747 SerialState *s = &serial_ports[0];
1749 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1750 s->iir = UART_IIR_NO_INT;
1752 #if defined(TARGET_I386) || defined (TARGET_PPC)
1753 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1754 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1758 /***********************************************************/
1759 /* ne2000 emulation */
1761 #if defined (TARGET_I386)
1762 #define NE2000_IOPORT 0x300
1763 #define NE2000_IRQ 9
1765 #define MAX_ETH_FRAME_SIZE 1514
1767 #define E8390_CMD 0x00 /* The command register (for all pages) */
1768 /* Page 0 register offsets. */
1769 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1770 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1771 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1772 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1773 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1774 #define EN0_TSR 0x04 /* Transmit status reg RD */
1775 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1776 #define EN0_NCR 0x05 /* Number of collision reg RD */
1777 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1778 #define EN0_FIFO 0x06 /* FIFO RD */
1779 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1780 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1781 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1782 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1783 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1784 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1785 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1786 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1787 #define EN0_RSR 0x0c /* rx status reg RD */
1788 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1789 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1790 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1791 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1792 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1793 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1794 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1796 #define EN1_PHYS 0x11
1797 #define EN1_CURPAG 0x17
1798 #define EN1_MULT 0x18
1800 /* Register accessed at EN_CMD, the 8390 base addr. */
1801 #define E8390_STOP 0x01 /* Stop and reset the chip */
1802 #define E8390_START 0x02 /* Start the chip, clear reset */
1803 #define E8390_TRANS 0x04 /* Transmit a frame */
1804 #define E8390_RREAD 0x08 /* Remote read */
1805 #define E8390_RWRITE 0x10 /* Remote write */
1806 #define E8390_NODMA 0x20 /* Remote DMA */
1807 #define E8390_PAGE0 0x00 /* Select page chip registers */
1808 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1809 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1811 /* Bits in EN0_ISR - Interrupt status register */
1812 #define ENISR_RX 0x01 /* Receiver, no error */
1813 #define ENISR_TX 0x02 /* Transmitter, no error */
1814 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1815 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1816 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1817 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1818 #define ENISR_RDC 0x40 /* remote dma complete */
1819 #define ENISR_RESET 0x80 /* Reset completed */
1820 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1822 /* Bits in received packet status byte and EN0_RSR*/
1823 #define ENRSR_RXOK 0x01 /* Received a good packet */
1824 #define ENRSR_CRC 0x02 /* CRC error */
1825 #define ENRSR_FAE 0x04 /* frame alignment error */
1826 #define ENRSR_FO 0x08 /* FIFO overrun */
1827 #define ENRSR_MPA 0x10 /* missed pkt */
1828 #define ENRSR_PHY 0x20 /* physical/multicast address */
1829 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1830 #define ENRSR_DEF 0x80 /* deferring */
1832 /* Transmitted packet status, EN0_TSR. */
1833 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1834 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1835 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1836 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1837 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1838 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1839 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1840 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1842 #define NE2000_MEM_SIZE 32768
1844 typedef struct NE2000State {
1857 uint8_t phys[6]; /* mac address */
1859 uint8_t mult[8]; /* multicast mask array */
1860 uint8_t mem[NE2000_MEM_SIZE];
1863 NE2000State ne2000_state;
1865 char network_script[1024];
1867 void ne2000_reset(void)
1869 NE2000State *s = &ne2000_state;
1872 s->isr = ENISR_RESET;
1882 /* duplicate prom data */
1883 for(i = 15;i >= 0; i--) {
1884 s->mem[2 * i] = s->mem[i];
1885 s->mem[2 * i + 1] = s->mem[i];
1889 void ne2000_update_irq(NE2000State *s)
1892 isr = s->isr & s->imr;
1894 pic_set_irq(NE2000_IRQ, 1);
1896 pic_set_irq(NE2000_IRQ, 0);
1902 int fd, ret, pid, status;
1904 fd = open("/dev/net/tun", O_RDWR);
1906 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1909 memset(&ifr, 0, sizeof(ifr));
1910 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1911 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1912 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1914 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1918 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1919 fcntl(fd, F_SETFL, O_NONBLOCK);
1922 /* try to launch network init script */
1926 execl(network_script, network_script, ifr.ifr_name, NULL);
1929 while (waitpid(pid, &status, 0) != pid);
1930 if (!WIFEXITED(status) ||
1931 WEXITSTATUS(status) != 0) {
1932 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1933 network_script, ifr.ifr_name);
1939 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1942 printf("NE2000: sending packet size=%d\n", size);
1944 write(net_fd, buf, size);
1947 /* return true if the NE2000 can receive more data */
1948 int ne2000_can_receive(NE2000State *s)
1950 int avail, index, boundary;
1952 if (s->cmd & E8390_STOP)
1954 index = s->curpag << 8;
1955 boundary = s->boundary << 8;
1956 if (index < boundary)
1957 avail = boundary - index;
1959 avail = (s->stop - s->start) - (index - boundary);
1960 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1965 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1968 int total_len, next, avail, len, index;
1970 #if defined(DEBUG_NE2000)
1971 printf("NE2000: received len=%d\n", size);
1974 index = s->curpag << 8;
1975 /* 4 bytes for header */
1976 total_len = size + 4;
1977 /* address for next packet (4 bytes for CRC) */
1978 next = index + ((total_len + 4 + 255) & ~0xff);
1979 if (next >= s->stop)
1980 next -= (s->stop - s->start);
1981 /* prepare packet header */
1983 p[0] = ENRSR_RXOK; /* receive status */
1986 p[3] = total_len >> 8;
1989 /* write packet data */
1991 avail = s->stop - index;
1995 memcpy(s->mem + index, buf, len);
1998 if (index == s->stop)
2002 s->curpag = next >> 8;
2004 /* now we can signal we have receive something */
2006 ne2000_update_irq(s);
2009 void ne2000_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
2011 NE2000State *s = &ne2000_state;
2016 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
2018 if (addr == E8390_CMD) {
2019 /* control register */
2021 if (val & E8390_START) {
2022 /* test specific case: zero length transfert */
2023 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
2025 s->isr |= ENISR_RDC;
2026 ne2000_update_irq(s);
2028 if (val & E8390_TRANS) {
2029 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
2030 /* signal end of transfert */
2033 ne2000_update_irq(s);
2038 offset = addr | (page << 4);
2041 s->start = val << 8;
2051 ne2000_update_irq(s);
2057 s->tcnt = (s->tcnt & 0xff00) | val;
2060 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
2063 s->rsar = (s->rsar & 0xff00) | val;
2066 s->rsar = (s->rsar & 0x00ff) | (val << 8);
2069 s->rcnt = (s->rcnt & 0xff00) | val;
2072 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
2079 ne2000_update_irq(s);
2081 case EN1_PHYS ... EN1_PHYS + 5:
2082 s->phys[offset - EN1_PHYS] = val;
2087 case EN1_MULT ... EN1_MULT + 7:
2088 s->mult[offset - EN1_MULT] = val;
2094 uint32_t ne2000_ioport_read(CPUState *env, uint32_t addr)
2096 NE2000State *s = &ne2000_state;
2097 int offset, page, ret;
2100 if (addr == E8390_CMD) {
2104 offset = addr | (page << 4);
2115 case EN1_PHYS ... EN1_PHYS + 5:
2116 ret = s->phys[offset - EN1_PHYS];
2121 case EN1_MULT ... EN1_MULT + 7:
2122 ret = s->mult[offset - EN1_MULT];
2130 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
2135 void ne2000_asic_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
2137 NE2000State *s = &ne2000_state;
2141 printf("NE2000: asic write val=0x%04x\n", val);
2143 p = s->mem + s->rsar;
2144 if (s->dcfg & 0x01) {
2157 if (s->rsar == s->stop)
2160 /* signal end of transfert */
2161 s->isr |= ENISR_RDC;
2162 ne2000_update_irq(s);
2166 uint32_t ne2000_asic_ioport_read(CPUState *env, uint32_t addr)
2168 NE2000State *s = &ne2000_state;
2172 p = s->mem + s->rsar;
2173 if (s->dcfg & 0x01) {
2175 ret = p[0] | (p[1] << 8);
2185 if (s->rsar == s->stop)
2188 /* signal end of transfert */
2189 s->isr |= ENISR_RDC;
2190 ne2000_update_irq(s);
2193 printf("NE2000: asic read val=0x%04x\n", ret);
2198 void ne2000_reset_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
2200 /* nothing to do (end of reset pulse) */
2203 uint32_t ne2000_reset_ioport_read(CPUState *env, uint32_t addr)
2209 void ne2000_init(void)
2211 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
2212 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
2214 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
2215 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
2216 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
2217 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
2219 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
2220 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
2225 /***********************************************************/
2226 /* PC floppy disk controler emulation glue */
2227 #define PC_FDC_DMA 0x2
2228 #define PC_FDC_IRQ 0x6
2229 #define PC_FDC_BASE 0x3F0
2231 static void fdctrl_register (unsigned char **disknames, int ro,
2236 fdctrl_init(PC_FDC_IRQ, PC_FDC_DMA, 0, PC_FDC_BASE, boot_device);
2237 for (i = 0; i < MAX_FD; i++) {
2238 if (disknames[i] != NULL)
2239 fdctrl_disk_change(i, disknames[i], ro);
2243 /***********************************************************/
2244 /* keyboard emulation */
2246 /* Keyboard Controller Commands */
2247 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
2248 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
2249 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
2250 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
2251 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2252 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2253 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2254 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2255 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2256 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2257 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2258 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2259 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2260 #define KBD_CCMD_WRITE_OBUF 0xD2
2261 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2262 initiated by the auxiliary device */
2263 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
2264 #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */
2265 #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */
2266 #define KBD_CCMD_RESET 0xFE
2268 /* Keyboard Commands */
2269 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2270 #define KBD_CMD_ECHO 0xEE
2271 #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
2272 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2273 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2274 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2275 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2276 #define KBD_CMD_RESET 0xFF /* Reset */
2278 /* Keyboard Replies */
2279 #define KBD_REPLY_POR 0xAA /* Power on reset */
2280 #define KBD_REPLY_ACK 0xFA /* Command ACK */
2281 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2283 /* Status Register Bits */
2284 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2285 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2286 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2287 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2288 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2289 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2290 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2291 #define KBD_STAT_PERR 0x80 /* Parity error */
2293 /* Controller Mode Register Bits */
2294 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2295 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2296 #define KBD_MODE_SYS 0x04 /* The system flag (?) */
2297 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2298 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2299 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2300 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2301 #define KBD_MODE_RFU 0x80
2303 /* Mouse Commands */
2304 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2305 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
2306 #define AUX_SET_RES 0xE8 /* Set resolution */
2307 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2308 #define AUX_SET_STREAM 0xEA /* Set stream mode */
2309 #define AUX_POLL 0xEB /* Poll */
2310 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
2311 #define AUX_SET_WRAP 0xEE /* Set wrap mode */
2312 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
2313 #define AUX_GET_TYPE 0xF2 /* Get type */
2314 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2315 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2316 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
2317 #define AUX_SET_DEFAULT 0xF6
2318 #define AUX_RESET 0xFF /* Reset aux device */
2319 #define AUX_ACK 0xFA /* Command byte ACK. */
2321 #define MOUSE_STATUS_REMOTE 0x40
2322 #define MOUSE_STATUS_ENABLED 0x20
2323 #define MOUSE_STATUS_SCALE21 0x10
2325 #define KBD_QUEUE_SIZE 256
2328 uint8_t data[KBD_QUEUE_SIZE];
2329 int rptr, wptr, count;
2332 typedef struct KBDState {
2334 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
2337 /* keyboard state */
2341 int mouse_write_cmd;
2342 uint8_t mouse_status;
2343 uint8_t mouse_resolution;
2344 uint8_t mouse_sample_rate;
2346 uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
2347 uint8_t mouse_detect_state;
2348 int mouse_dx; /* current values, needed for 'poll' mode */
2351 uint8_t mouse_buttons;
2355 int reset_requested;
2357 /* update irq and KBD_STAT_[MOUSE_]OBF */
2358 /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
2359 incorrect, but it avoids having to simulate exact delays */
2360 static void kbd_update_irq(KBDState *s)
2362 int irq12_level, irq1_level;
2366 s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
2367 if (s->queues[0].count != 0 ||
2368 s->queues[1].count != 0) {
2369 s->status |= KBD_STAT_OBF;
2370 if (s->queues[1].count != 0) {
2371 s->status |= KBD_STAT_MOUSE_OBF;
2372 if (s->mode & KBD_MODE_MOUSE_INT)
2375 if ((s->mode & KBD_MODE_KBD_INT) &&
2376 !(s->mode & KBD_MODE_DISABLE_KBD))
2380 pic_set_irq(1, irq1_level);
2381 pic_set_irq(12, irq12_level);
2384 static void kbd_queue(KBDState *s, int b, int aux)
2386 KBDQueue *q = &kbd_state.queues[aux];
2388 #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2390 printf("mouse event: 0x%02x\n", b);
2393 printf("kbd event: 0x%02x\n", b);
2396 if (q->count >= KBD_QUEUE_SIZE)
2398 q->data[q->wptr] = b;
2399 if (++q->wptr == KBD_QUEUE_SIZE)
2405 void kbd_put_keycode(int keycode)
2407 KBDState *s = &kbd_state;
2408 kbd_queue(s, keycode, 0);
2411 uint32_t kbd_read_status(CPUState *env, uint32_t addr)
2413 KBDState *s = &kbd_state;
2416 #if defined(DEBUG_KBD)
2417 printf("kbd: read status=0x%02x\n", val);
2422 void kbd_write_command(CPUState *env, uint32_t addr, uint32_t val)
2424 KBDState *s = &kbd_state;
2427 printf("kbd: write cmd=0x%02x\n", val);
2430 case KBD_CCMD_READ_MODE:
2431 kbd_queue(s, s->mode, 0);
2433 case KBD_CCMD_WRITE_MODE:
2434 case KBD_CCMD_WRITE_OBUF:
2435 case KBD_CCMD_WRITE_AUX_OBUF:
2436 case KBD_CCMD_WRITE_MOUSE:
2437 case KBD_CCMD_WRITE_OUTPORT:
2440 case KBD_CCMD_MOUSE_DISABLE:
2441 s->mode |= KBD_MODE_DISABLE_MOUSE;
2443 case KBD_CCMD_MOUSE_ENABLE:
2444 s->mode &= ~KBD_MODE_DISABLE_MOUSE;
2446 case KBD_CCMD_TEST_MOUSE:
2447 kbd_queue(s, 0x00, 0);
2449 case KBD_CCMD_SELF_TEST:
2450 s->status |= KBD_STAT_SELFTEST;
2451 kbd_queue(s, 0x55, 0);
2453 case KBD_CCMD_KBD_TEST:
2454 kbd_queue(s, 0x00, 0);
2456 case KBD_CCMD_KBD_DISABLE:
2457 s->mode |= KBD_MODE_DISABLE_KBD;
2460 case KBD_CCMD_KBD_ENABLE:
2461 s->mode &= ~KBD_MODE_DISABLE_KBD;
2464 case KBD_CCMD_READ_INPORT:
2465 kbd_queue(s, 0x00, 0);
2467 case KBD_CCMD_READ_OUTPORT:
2468 /* XXX: check that */
2470 val = 0x01 | (a20_enabled << 1);
2474 if (s->status & KBD_STAT_OBF)
2476 if (s->status & KBD_STAT_MOUSE_OBF)
2478 kbd_queue(s, val, 0);
2481 case KBD_CCMD_ENABLE_A20:
2482 cpu_x86_set_a20(env, 1);
2484 case KBD_CCMD_DISABLE_A20:
2485 cpu_x86_set_a20(env, 0);
2488 case KBD_CCMD_RESET:
2489 reset_requested = 1;
2490 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
2493 /* ignore that - I don't know what is its use */
2496 fprintf(stderr, "qemu: unsupported keyboard cmd=0x%02x\n", val);
2501 uint32_t kbd_read_data(CPUState *env, uint32_t addr)
2503 KBDState *s = &kbd_state;
2507 q = &s->queues[0]; /* first check KBD data */
2509 q = &s->queues[1]; /* then check AUX data */
2510 if (q->count == 0) {
2511 /* NOTE: if no data left, we return the last keyboard one
2512 (needed for EMM386) */
2513 /* XXX: need a timer to do things correctly */
2515 index = q->rptr - 1;
2517 index = KBD_QUEUE_SIZE - 1;
2518 val = q->data[index];
2520 val = q->data[q->rptr];
2521 if (++q->rptr == KBD_QUEUE_SIZE)
2524 /* reading deasserts IRQ */
2525 if (q == &s->queues[0])
2530 /* reassert IRQs if data left */
2533 printf("kbd: read data=0x%02x\n", val);
2538 static void kbd_reset_keyboard(KBDState *s)
2540 s->scan_enabled = 1;
2543 static void kbd_write_keyboard(KBDState *s, int val)
2545 switch(s->kbd_write_cmd) {
2550 kbd_queue(s, KBD_REPLY_ACK, 0);
2553 kbd_queue(s, KBD_REPLY_RESEND, 0);
2555 case KBD_CMD_GET_ID:
2556 kbd_queue(s, KBD_REPLY_ACK, 0);
2557 kbd_queue(s, 0xab, 0);
2558 kbd_queue(s, 0x83, 0);
2561 kbd_queue(s, KBD_CMD_ECHO, 0);
2563 case KBD_CMD_ENABLE:
2564 s->scan_enabled = 1;
2565 kbd_queue(s, KBD_REPLY_ACK, 0);
2567 case KBD_CMD_SET_LEDS:
2568 case KBD_CMD_SET_RATE:
2569 s->kbd_write_cmd = val;
2570 kbd_queue(s, KBD_REPLY_ACK, 0);
2572 case KBD_CMD_RESET_DISABLE:
2573 kbd_reset_keyboard(s);
2574 s->scan_enabled = 0;
2575 kbd_queue(s, KBD_REPLY_ACK, 0);
2577 case KBD_CMD_RESET_ENABLE:
2578 kbd_reset_keyboard(s);
2579 s->scan_enabled = 1;
2580 kbd_queue(s, KBD_REPLY_ACK, 0);
2583 kbd_reset_keyboard(s);
2584 kbd_queue(s, KBD_REPLY_ACK, 0);
2585 kbd_queue(s, KBD_REPLY_POR, 0);
2588 kbd_queue(s, KBD_REPLY_ACK, 0);
2592 case KBD_CMD_SET_LEDS:
2593 kbd_queue(s, KBD_REPLY_ACK, 0);
2594 s->kbd_write_cmd = -1;
2596 case KBD_CMD_SET_RATE:
2597 kbd_queue(s, KBD_REPLY_ACK, 0);
2598 s->kbd_write_cmd = -1;
2603 static void kbd_mouse_send_packet(KBDState *s)
2611 /* XXX: increase range to 8 bits ? */
2614 else if (dx1 < -127)
2618 else if (dy1 < -127)
2620 b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
2622 kbd_queue(s, dx1 & 0xff, 1);
2623 kbd_queue(s, dy1 & 0xff, 1);
2624 /* extra byte for IMPS/2 or IMEX */
2625 switch(s->mouse_type) {
2631 else if (dz1 < -127)
2633 kbd_queue(s, dz1 & 0xff, 1);
2640 b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
2651 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
2653 KBDState *s = &kbd_state;
2655 /* check if deltas are recorded when disabled */
2656 if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
2662 s->mouse_buttons = buttons_state;
2664 if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
2665 (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
2667 /* if not remote, send event. Multiple events are sent if
2669 kbd_mouse_send_packet(s);
2670 if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
2676 static void kbd_write_mouse(KBDState *s, int val)
2679 printf("kbd: write mouse 0x%02x\n", val);
2681 switch(s->mouse_write_cmd) {
2685 if (s->mouse_wrap) {
2686 if (val == AUX_RESET_WRAP) {
2688 kbd_queue(s, AUX_ACK, 1);
2690 } else if (val != AUX_RESET) {
2691 kbd_queue(s, val, 1);
2696 case AUX_SET_SCALE11:
2697 s->mouse_status &= ~MOUSE_STATUS_SCALE21;
2698 kbd_queue(s, AUX_ACK, 1);
2700 case AUX_SET_SCALE21:
2701 s->mouse_status |= MOUSE_STATUS_SCALE21;
2702 kbd_queue(s, AUX_ACK, 1);
2704 case AUX_SET_STREAM:
2705 s->mouse_status &= ~MOUSE_STATUS_REMOTE;
2706 kbd_queue(s, AUX_ACK, 1);
2710 kbd_queue(s, AUX_ACK, 1);
2712 case AUX_SET_REMOTE:
2713 s->mouse_status |= MOUSE_STATUS_REMOTE;
2714 kbd_queue(s, AUX_ACK, 1);
2717 kbd_queue(s, AUX_ACK, 1);
2718 kbd_queue(s, s->mouse_type, 1);
2721 case AUX_SET_SAMPLE:
2722 s->mouse_write_cmd = val;
2723 kbd_queue(s, AUX_ACK, 1);
2726 kbd_queue(s, AUX_ACK, 1);
2727 kbd_queue(s, s->mouse_status, 1);
2728 kbd_queue(s, s->mouse_resolution, 1);
2729 kbd_queue(s, s->mouse_sample_rate, 1);
2732 kbd_queue(s, AUX_ACK, 1);
2733 kbd_mouse_send_packet(s);
2735 case AUX_ENABLE_DEV:
2736 s->mouse_status |= MOUSE_STATUS_ENABLED;
2737 kbd_queue(s, AUX_ACK, 1);
2739 case AUX_DISABLE_DEV:
2740 s->mouse_status &= ~MOUSE_STATUS_ENABLED;
2741 kbd_queue(s, AUX_ACK, 1);
2743 case AUX_SET_DEFAULT:
2744 s->mouse_sample_rate = 100;
2745 s->mouse_resolution = 2;
2746 s->mouse_status = 0;
2747 kbd_queue(s, AUX_ACK, 1);
2750 s->mouse_sample_rate = 100;
2751 s->mouse_resolution = 2;
2752 s->mouse_status = 0;
2753 kbd_queue(s, AUX_ACK, 1);
2754 kbd_queue(s, 0xaa, 1);
2755 kbd_queue(s, s->mouse_type, 1);
2761 case AUX_SET_SAMPLE:
2762 s->mouse_sample_rate = val;
2764 /* detect IMPS/2 or IMEX */
2765 switch(s->mouse_detect_state) {
2769 s->mouse_detect_state = 1;
2773 s->mouse_detect_state = 2;
2774 else if (val == 200)
2775 s->mouse_detect_state = 3;
2777 s->mouse_detect_state = 0;
2781 s->mouse_type = 3; /* IMPS/2 */
2782 s->mouse_detect_state = 0;
2786 s->mouse_type = 4; /* IMEX */
2787 s->mouse_detect_state = 0;
2791 kbd_queue(s, AUX_ACK, 1);
2792 s->mouse_write_cmd = -1;
2795 s->mouse_resolution = val;
2796 kbd_queue(s, AUX_ACK, 1);
2797 s->mouse_write_cmd = -1;
2802 void kbd_write_data(CPUState *env, uint32_t addr, uint32_t val)
2804 KBDState *s = &kbd_state;
2807 printf("kbd: write data=0x%02x\n", val);
2810 switch(s->write_cmd) {
2812 kbd_write_keyboard(s, val);
2814 case KBD_CCMD_WRITE_MODE:
2818 case KBD_CCMD_WRITE_OBUF:
2819 kbd_queue(s, val, 0);
2821 case KBD_CCMD_WRITE_AUX_OBUF:
2822 kbd_queue(s, val, 1);
2824 case KBD_CCMD_WRITE_OUTPORT:
2826 cpu_x86_set_a20(env, (val >> 1) & 1);
2829 reset_requested = 1;
2830 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
2833 case KBD_CCMD_WRITE_MOUSE:
2834 kbd_write_mouse(s, val);
2842 void kbd_reset(KBDState *s)
2847 s->kbd_write_cmd = -1;
2848 s->mouse_write_cmd = -1;
2849 s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
2850 s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
2851 for(i = 0; i < 2; i++) {
2861 kbd_reset(&kbd_state);
2862 #if defined (TARGET_I386) || defined (TARGET_PPC)
2863 register_ioport_read(0x60, 1, kbd_read_data, 1);
2864 register_ioport_write(0x60, 1, kbd_write_data, 1);
2865 register_ioport_read(0x64, 1, kbd_read_status, 1);
2866 register_ioport_write(0x64, 1, kbd_write_command, 1);
2870 /***********************************************************/
2871 /* Bochs BIOS debug ports */
2873 void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
2876 /* Bochs BIOS messages */
2879 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
2884 fprintf(stderr, "%c", val);
2888 /* LGPL'ed VGA BIOS messages */
2891 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
2896 fprintf(stderr, "%c", val);
2902 void bochs_bios_init(void)
2904 register_ioport_write(0x400, 1, bochs_bios_write, 2);
2905 register_ioport_write(0x401, 1, bochs_bios_write, 2);
2906 register_ioport_write(0x402, 1, bochs_bios_write, 1);
2907 register_ioport_write(0x403, 1, bochs_bios_write, 1);
2909 register_ioport_write(0x501, 1, bochs_bios_write, 2);
2910 register_ioport_write(0x502, 1, bochs_bios_write, 2);
2911 register_ioport_write(0x500, 1, bochs_bios_write, 1);
2912 register_ioport_write(0x503, 1, bochs_bios_write, 1);
2916 /***********************************************************/
2919 /* init terminal so that we can grab keys */
2920 static struct termios oldtty;
2922 static void term_exit(void)
2924 tcsetattr (0, TCSANOW, &oldtty);
2927 static void term_init(void)
2931 tcgetattr (0, &tty);
2934 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
2935 |INLCR|IGNCR|ICRNL|IXON);
2936 tty.c_oflag |= OPOST;
2937 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN);
2938 /* if graphical mode, we allow Ctrl-C handling */
2940 tty.c_lflag &= ~ISIG;
2941 tty.c_cflag &= ~(CSIZE|PARENB);
2944 tty.c_cc[VTIME] = 0;
2946 tcsetattr (0, TCSANOW, &tty);
2950 fcntl(0, F_SETFL, O_NONBLOCK);
2953 static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
2957 static void dumb_resize(DisplayState *ds, int w, int h)
2961 static void dumb_refresh(DisplayState *ds)
2963 vga_update_display();
2966 void dumb_display_init(DisplayState *ds)
2971 ds->dpy_update = dumb_update;
2972 ds->dpy_resize = dumb_resize;
2973 ds->dpy_refresh = dumb_refresh;
2976 #if !defined(CONFIG_SOFTMMU)
2977 /***********************************************************/
2978 /* cpu signal handler */
2979 static void host_segv_handler(int host_signum, siginfo_t *info,
2982 if (cpu_signal_handler(host_signum, info, puc))
2989 static int timer_irq_pending;
2990 static int timer_irq_count;
2992 static int timer_ms;
2993 static int gui_refresh_pending, gui_refresh_count;
2995 static void host_alarm_handler(int host_signum, siginfo_t *info,
2998 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2999 some drift between cpu_get_ticks() and the interrupt time. So
3000 we queue some interrupts to avoid missing some */
3001 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
3002 if (timer_irq_count) {
3003 if (timer_irq_count > 2)
3004 timer_irq_count = 2;
3006 timer_irq_pending = 1;
3008 gui_refresh_count += timer_ms;
3009 if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
3010 gui_refresh_count = 0;
3011 gui_refresh_pending = 1;
3014 /* XXX: seems dangerous to run that here. */
3018 if (gui_refresh_pending || timer_irq_pending) {
3019 /* just exit from the cpu to have a chance to handle timers */
3020 cpu_interrupt(global_env, CPU_INTERRUPT_EXIT);
3024 #ifdef CONFIG_SOFTMMU
3025 void *get_mmap_addr(unsigned long size)
3030 unsigned long mmap_addr = PHYS_RAM_BASE;
3032 void *get_mmap_addr(unsigned long size)
3036 mmap_addr += ((size + 4095) & ~4095) + 4096;
3037 return (void *)addr;
3041 /* main execution loop */
3043 CPUState *cpu_gdbstub_get_env(void *opaque)
3048 int main_loop(void *opaque)
3050 struct pollfd ufds[3], *pf, *serial_ufd, *gdb_ufd;
3051 #if defined (TARGET_I386)
3052 struct pollfd *net_ufd;
3054 int ret, n, timeout, serial_ok;
3056 CPUState *env = global_env;
3059 /* initialize terminal only there so that the user has a
3060 chance to stop QEMU with Ctrl-C before the gdb connection
3069 #if defined (DO_TB_FLUSH)
3072 ret = cpu_exec(env);
3073 if (reset_requested) {
3074 ret = EXCP_INTERRUPT;
3077 if (ret == EXCP_DEBUG) {
3081 /* if hlt instruction, we wait until the next IRQ */
3082 if (ret == EXCP_HLT)
3086 /* poll any events */
3089 if (serial_ok && !(serial_ports[0].lsr & UART_LSR_DR)) {
3092 pf->events = POLLIN;
3095 #if defined (TARGET_I386)
3097 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
3100 pf->events = POLLIN;
3105 if (gdbstub_fd > 0) {
3107 pf->fd = gdbstub_fd;
3108 pf->events = POLLIN;
3112 ret = poll(ufds, pf - ufds, timeout);
3114 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
3115 n = read(0, &ch, 1);
3117 serial_received_byte(&serial_ports[0], ch);
3119 /* Closed, stop polling. */
3123 #if defined (TARGET_I386)
3124 if (net_ufd && (net_ufd->revents & POLLIN)) {
3125 uint8_t buf[MAX_ETH_FRAME_SIZE];
3127 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
3130 memset(buf + n, 0, 60 - n);
3133 ne2000_receive(&ne2000_state, buf, n);
3137 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
3139 /* stop emulation if requested by gdb */
3140 n = read(gdbstub_fd, buf, 1);
3142 ret = EXCP_INTERRUPT;
3149 if (timer_irq_pending) {
3150 #if defined (TARGET_I386)
3153 timer_irq_pending = 0;
3155 if (cmos_data[RTC_REG_B] & 0x50) {
3162 if (gui_refresh_pending) {
3163 display_state.dpy_refresh(&display_state);
3164 gui_refresh_pending = 0;
3167 cpu_disable_ticks();
3173 printf("QEMU PC emulator version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
3174 "usage: %s [options] [disk_image]\n"
3176 "'disk_image' is a raw hard image image for IDE hard disk 0\n"
3178 "Standard options:\n"
3179 "-fda/-fdb file use 'file' as floppy disk 0/1 image\n"
3180 "-hda/-hdb file use 'file' as IDE hard disk 0/1 image\n"
3181 "-hdc/-hdd file use 'file' as IDE hard disk 2/3 image\n"
3182 "-cdrom file use 'file' as IDE cdrom 2 image\n"
3183 "-boot [c|d] boot on hard disk (c) or CD-ROM (d)\n"
3184 "-snapshot write to temporary files instead of disk image files\n"
3185 "-m megs set virtual RAM size to megs MB\n"
3186 "-n script set network init script [default=%s]\n"
3187 "-tun-fd fd this fd talks to tap/tun, use it.\n"
3188 "-nographic disable graphical output\n"
3190 "Linux boot specific (does not require PC BIOS):\n"
3191 "-kernel bzImage use 'bzImage' as kernel image\n"
3192 "-append cmdline use 'cmdline' as kernel command line\n"
3193 "-initrd file use 'file' as initial ram disk\n"
3195 "Debug/Expert options:\n"
3196 "-s wait gdb connection to port %d\n"
3197 "-p port change gdb connection port\n"
3198 "-d output log in /tmp/vl.log\n"
3199 "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
3200 "-L path set the directory for the BIOS and VGA BIOS\n"
3202 "During emulation, use C-a h to get terminal commands:\n",
3203 #ifdef CONFIG_SOFTMMU
3208 DEFAULT_NETWORK_SCRIPT,
3209 DEFAULT_GDBSTUB_PORT);
3211 #ifndef CONFIG_SOFTMMU
3213 "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
3214 "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
3220 struct option long_options[] = {
3221 { "initrd", 1, NULL, 0, },
3222 { "hda", 1, NULL, 0, },
3223 { "hdb", 1, NULL, 0, },
3224 { "snapshot", 0, NULL, 0, },
3225 { "hdachs", 1, NULL, 0, },
3226 { "nographic", 0, NULL, 0, },
3227 { "kernel", 1, NULL, 0, },
3228 { "append", 1, NULL, 0, },
3229 { "tun-fd", 1, NULL, 0, },
3230 { "hdc", 1, NULL, 0, },
3231 { "hdd", 1, NULL, 0, },
3232 { "cdrom", 1, NULL, 0, },
3233 { "boot", 1, NULL, 0, },
3234 { "fda", 1, NULL, 0, },
3235 { "fdb", 1, NULL, 0, },
3236 { NULL, 0, NULL, 0 },
3240 /* SDL use the pthreads and they modify sigaction. We don't
3242 #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2)
3243 extern void __libc_sigaction();
3244 #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
3246 extern void __sigaction();
3247 #define sigaction(sig, act, oact) __sigaction(sig, act, oact)
3249 #endif /* CONFIG_SDL */
3251 int main(int argc, char **argv)
3253 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
3254 int snapshot, linux_boot, total_ram_size;
3255 #if defined (TARGET_I386)
3256 struct linux_params *params;
3258 struct sigaction act;
3259 struct itimerval itv;
3261 const char *initrd_filename;
3262 const char *hd_filename[MAX_DISKS], *fd_filename[MAX_FD];
3263 const char *kernel_filename, *kernel_cmdline;
3264 DisplayState *ds = &display_state;
3266 /* we never want that malloc() uses mmap() */
3267 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
3268 initrd_filename = NULL;
3269 for(i = 0; i < MAX_FD; i++)
3270 fd_filename[i] = NULL;
3271 for(i = 0; i < MAX_DISKS; i++)
3272 hd_filename[i] = NULL;
3273 phys_ram_size = 32 * 1024 * 1024;
3274 vga_ram_size = VGA_RAM_SIZE;
3275 #if defined (TARGET_I386)
3276 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
3279 gdbstub_port = DEFAULT_GDBSTUB_PORT;
3282 kernel_filename = NULL;
3283 kernel_cmdline = "";
3285 c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
3290 switch(long_index) {
3292 initrd_filename = optarg;
3295 hd_filename[0] = optarg;
3298 hd_filename[1] = optarg;
3305 int cyls, heads, secs;
3308 cyls = strtol(p, (char **)&p, 0);
3312 heads = strtol(p, (char **)&p, 0);
3316 secs = strtol(p, (char **)&p, 0);
3319 ide_set_geometry(0, cyls, heads, secs);
3327 kernel_filename = optarg;
3330 kernel_cmdline = optarg;
3332 #if defined (TARGET_I386)
3334 net_fd = atoi(optarg);
3338 hd_filename[2] = optarg;
3341 hd_filename[3] = optarg;
3344 hd_filename[2] = optarg;
3345 ide_set_cdrom(2, 1);
3348 boot_device = optarg[0];
3349 if (boot_device != 'a' && boot_device != 'b' &&
3350 boot_device != 'c' && boot_device != 'd') {
3351 fprintf(stderr, "qemu: invalid boot device '%c'\n", boot_device);
3356 fd_filename[0] = optarg;
3359 fd_filename[1] = optarg;
3367 phys_ram_size = atoi(optarg) * 1024 * 1024;
3368 if (phys_ram_size <= 0)
3370 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
3371 fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
3372 PHYS_RAM_MAX_SIZE / (1024 * 1024));
3377 cpu_set_log(CPU_LOG_ALL);
3379 #if defined (TARGET_I386)
3381 pstrcpy(network_script, sizeof(network_script), optarg);
3388 gdbstub_port = atoi(optarg);
3396 if (optind < argc) {
3397 hd_filename[0] = argv[optind++];
3400 linux_boot = (kernel_filename != NULL);
3402 if (!linux_boot && hd_filename[0] == '\0' && hd_filename[2] == '\0' &&
3403 fd_filename[0] == '\0')
3406 /* boot to cd by default if no hard disk */
3407 if (hd_filename[0] == '\0' && boot_device == 'c')
3410 #if !defined(CONFIG_SOFTMMU)
3411 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
3413 static uint8_t stdout_buf[4096];
3414 setvbuf(stdout, stdout_buf, _IOLBF, sizeof(stdout_buf));
3417 setvbuf(stdout, NULL, _IOLBF, 0);
3420 /* init network tun interface */
3421 #if defined (TARGET_I386)
3426 /* init the memory */
3427 total_ram_size = phys_ram_size + vga_ram_size;
3429 #ifdef CONFIG_SOFTMMU
3430 phys_ram_base = malloc(total_ram_size);
3431 if (!phys_ram_base) {
3432 fprintf(stderr, "Could not allocate physical memory\n");
3436 /* as we must map the same page at several addresses, we must use
3441 tmpdir = getenv("QEMU_TMPDIR");
3444 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
3445 if (mkstemp(phys_ram_file) < 0) {
3446 fprintf(stderr, "Could not create temporary memory file '%s'\n",
3450 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
3451 if (phys_ram_fd < 0) {
3452 fprintf(stderr, "Could not open temporary memory file '%s'\n",
3456 ftruncate(phys_ram_fd, total_ram_size);
3457 unlink(phys_ram_file);
3458 phys_ram_base = mmap(get_mmap_addr(total_ram_size),
3460 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
3462 if (phys_ram_base == MAP_FAILED) {
3463 fprintf(stderr, "Could not map physical memory\n");
3469 /* open the virtual block devices */
3470 for(i = 0; i < MAX_DISKS; i++) {
3471 if (hd_filename[i]) {
3472 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
3474 fprintf(stderr, "qemu: could not open hard disk image '%s\n",
3481 /* init CPU state */
3484 cpu_single_env = env;
3489 cpu_register_physical_memory(0, phys_ram_size, 0);
3492 /* now we can load the kernel */
3493 ret = load_kernel(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
3495 fprintf(stderr, "qemu: could not load kernel '%s'\n",
3502 if (initrd_filename) {
3503 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
3504 if (initrd_size < 0) {
3505 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3511 /* init kernel params */
3513 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
3514 memset(params, 0, sizeof(struct linux_params));
3515 params->mount_root_rdonly = 0;
3516 stw_raw(¶ms->cl_magic, 0xA33F);
3517 stw_raw(¶ms->cl_offset, params->commandline - (uint8_t *)params);
3518 stl_raw(¶ms->alt_mem_k, (phys_ram_size / 1024) - 1024);
3519 pstrcat(params->commandline, sizeof(params->commandline), kernel_cmdline);
3520 params->loader_type = 0x01;
3521 if (initrd_size > 0) {
3522 stl_raw(¶ms->initrd_start, INITRD_LOAD_ADDR);
3523 stl_raw(¶ms->initrd_size, initrd_size);
3525 params->orig_video_lines = 25;
3526 params->orig_video_cols = 80;
3528 /* setup basic memory access */
3529 env->cr[0] = 0x00000033;
3530 env->hflags |= HF_PE_MASK;
3531 cpu_x86_init_mmu(env);
3533 memset(params->idt_table, 0, sizeof(params->idt_table));
3535 stq_raw(¶ms->gdt_table[2], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3536 stq_raw(¶ms->gdt_table[3], 0x00cf92000000ffffLL); /* KERNEL_DS */
3537 /* for newer kernels (2.6.0) CS/DS are at different addresses */
3538 stq_raw(¶ms->gdt_table[12], 0x00cf9a000000ffffLL); /* KERNEL_CS */
3539 stq_raw(¶ms->gdt_table[13], 0x00cf92000000ffffLL); /* KERNEL_DS */
3541 env->idt.base = (void *)((uint8_t *)params->idt_table - phys_ram_base);
3542 env->idt.limit = sizeof(params->idt_table) - 1;
3543 env->gdt.base = (void *)((uint8_t *)params->gdt_table - phys_ram_base);
3544 env->gdt.limit = sizeof(params->gdt_table) - 1;
3546 cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00);
3547 cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3548 cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3549 cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3550 cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3551 cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
3553 env->eip = KERNEL_LOAD_ADDR;
3554 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
3556 #elif defined (TARGET_PPC)
3557 cpu_x86_init_mmu(env);
3558 PPC_init_hw(env, phys_ram_size, KERNEL_LOAD_ADDR, ret,
3559 KERNEL_STACK_ADDR, boot_device);
3565 #if defined(TARGET_I386)
3567 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3568 ret = load_image(buf, phys_ram_base + 0x000f0000);
3569 if (ret != 0x10000) {
3570 fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
3575 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
3576 ret = load_image(buf, phys_ram_base + 0x000c0000);
3578 /* setup basic memory access */
3579 env->cr[0] = 0x60000010;
3580 cpu_x86_init_mmu(env);
3582 cpu_register_physical_memory(0xc0000, 0x10000, 0xc0000 | IO_MEM_ROM);
3583 cpu_register_physical_memory(0xf0000, 0x10000, 0xf0000 | IO_MEM_ROM);
3585 env->idt.limit = 0xffff;
3586 env->gdt.limit = 0xffff;
3587 env->ldt.limit = 0xffff;
3588 env->ldt.flags = DESC_P_MASK;
3589 env->tr.limit = 0xffff;
3590 env->tr.flags = DESC_P_MASK;
3592 /* not correct (CS base=0xffff0000) */
3593 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
3594 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
3595 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
3596 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
3597 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
3598 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
3601 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
3606 #elif defined(TARGET_PPC)
3607 cpu_x86_init_mmu(env);
3609 // snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
3610 snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME);
3611 printf("load BIOS at %p\n", phys_ram_base + 0x000f0000);
3612 ret = load_image(buf, phys_ram_base + 0x000f0000);
3613 if (ret != 0x10000) {
3614 fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
3623 dumb_display_init(ds);
3626 sdl_display_init(ds);
3628 dumb_display_init(ds);
3631 /* init basic PC hardware */
3632 register_ioport_write(0x80, 1, ioport80_write, 1);
3634 vga_initialize(ds, phys_ram_base + phys_ram_size, phys_ram_size,
3636 #if defined (TARGET_I386)
3642 #if defined (TARGET_I386)
3649 #if defined (TARGET_I386)
3652 #if defined (TARGET_PPC)
3655 fdctrl_register((unsigned char **)fd_filename, snapshot, boot_device);
3656 /* setup cpu signal handlers for MMU / self modifying code handling */
3657 sigfillset(&act.sa_mask);
3658 act.sa_flags = SA_SIGINFO;
3659 #if !defined(CONFIG_SOFTMMU)
3660 act.sa_sigaction = host_segv_handler;
3661 sigaction(SIGSEGV, &act, NULL);
3662 sigaction(SIGBUS, &act, NULL);
3665 act.sa_sigaction = host_alarm_handler;
3666 sigaction(SIGALRM, &act, NULL);
3668 itv.it_interval.tv_sec = 0;
3669 itv.it_interval.tv_usec = 1000;
3670 itv.it_value.tv_sec = 0;
3671 itv.it_value.tv_usec = 10 * 1000;
3672 setitimer(ITIMER_REAL, &itv, NULL);
3673 /* we probe the tick duration of the kernel to inform the user if
3674 the emulated kernel requested a too high timer frequency */
3675 getitimer(ITIMER_REAL, &itv);
3676 timer_ms = itv.it_interval.tv_usec / 1000;
3677 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
3681 cpu_gdbstub(NULL, main_loop, gdbstub_port);