4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
28 Optional alignment check
45 #define DYNAMIC_PC 1 /* dynamic pc value */
46 #define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
49 typedef struct DisasContext {
50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
55 struct TranslationBlock *tb;
58 static uint16_t *gen_opc_ptr;
59 static uint32_t *gen_opparam_ptr;
64 #define DEF(s,n,copy_size) INDEX_op_ ## s,
72 // This function uses non-native bit order
73 #define GET_FIELD(X, FROM, TO) \
74 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
76 // This function uses the order in the manuals, i.e. bit 0 is 2^0
77 #define GET_FIELD_SP(X, FROM, TO) \
78 GET_FIELD(X, 31 - (TO), 31 - (FROM))
80 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
81 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
84 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
89 #ifdef USE_DIRECT_JUMP
92 #define TBPARAM(x) (long)(x)
95 static int sign_extend(int x, int len)
98 return (x << len) >> len;
101 #define IS_IMM (insn & (1<<13))
103 static void disas_sparc_insn(DisasContext * dc);
105 static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
176 static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
281 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
287 // Sign extending version
288 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
294 #ifdef TARGET_SPARC64
295 #define GEN32(func, NAME) \
296 static GenOpFunc *NAME ## _table [64] = { \
297 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
298 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
299 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
300 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
301 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
302 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
303 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
304 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
305 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
306 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
307 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
308 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
310 static inline void func(int n) \
312 NAME ## _table[n](); \
315 #define GEN32(func, NAME) \
316 static GenOpFunc *NAME ## _table [32] = { \
317 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
318 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
319 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
320 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
321 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
322 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
323 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
324 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
326 static inline void func(int n) \
328 NAME ## _table[n](); \
332 /* floating point registers moves */
333 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
334 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
335 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
336 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
338 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
339 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
340 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
341 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
343 #ifdef TARGET_SPARC64
344 // 'a' versions allowed to user depending on asi
345 #if defined(CONFIG_USER_ONLY)
346 #define supervisor(dc) 0
347 #define gen_op_ldst(name) gen_op_##name##_raw()
348 #define OP_LD_TABLE(width) \
349 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
354 offset = GET_FIELD(insn, 25, 31); \
356 gen_op_ld_asi_reg(offset, size, sign); \
358 gen_op_st_asi_reg(offset, size, sign); \
361 asi = GET_FIELD(insn, 19, 26); \
363 case 0x80: /* Primary address space */ \
364 gen_op_##width##_raw(); \
372 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
373 #define OP_LD_TABLE(width) \
374 static GenOpFunc *gen_op_##width[] = { \
375 &gen_op_##width##_user, \
376 &gen_op_##width##_kernel, \
379 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
384 offset = GET_FIELD(insn, 25, 31); \
386 gen_op_ld_asi_reg(offset, size, sign); \
388 gen_op_st_asi_reg(offset, size, sign); \
391 asi = GET_FIELD(insn, 19, 26); \
393 gen_op_ld_asi(asi, size, sign); \
395 gen_op_st_asi(asi, size, sign); \
398 #define supervisor(dc) (dc->mem_idx == 1)
401 #if defined(CONFIG_USER_ONLY)
402 #define gen_op_ldst(name) gen_op_##name##_raw()
403 #define OP_LD_TABLE(width)
404 #define supervisor(dc) 0
406 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
407 #define OP_LD_TABLE(width) \
408 static GenOpFunc *gen_op_##width[] = { \
409 &gen_op_##width##_user, \
410 &gen_op_##width##_kernel, \
413 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
417 asi = GET_FIELD(insn, 19, 26); \
419 case 10: /* User data access */ \
420 gen_op_##width##_user(); \
422 case 11: /* Supervisor data access */ \
423 gen_op_##width##_kernel(); \
425 case 0x20 ... 0x2f: /* MMU passthrough */ \
427 gen_op_ld_asi(asi, size, sign); \
429 gen_op_st_asi(asi, size, sign); \
433 gen_op_ld_asi(asi, size, sign); \
435 gen_op_st_asi(asi, size, sign); \
440 #define supervisor(dc) (dc->mem_idx == 1)
461 #ifdef TARGET_SPARC64
469 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
471 gen_op_movl_TN_im[reg](imm);
474 static inline void gen_movl_imm_T1(uint32_t val)
476 gen_movl_imm_TN(1, val);
479 static inline void gen_movl_imm_T0(uint32_t val)
481 gen_movl_imm_TN(0, val);
484 static inline void gen_movl_simm_TN(int reg, int32_t imm)
486 gen_op_movl_TN_sim[reg](imm);
489 static inline void gen_movl_simm_T1(int32_t val)
491 gen_movl_simm_TN(1, val);
494 static inline void gen_movl_simm_T0(int32_t val)
496 gen_movl_simm_TN(0, val);
499 static inline void gen_movl_reg_TN(int reg, int t)
502 gen_op_movl_reg_TN[t][reg] ();
504 gen_movl_imm_TN(t, 0);
507 static inline void gen_movl_reg_T0(int reg)
509 gen_movl_reg_TN(reg, 0);
512 static inline void gen_movl_reg_T1(int reg)
514 gen_movl_reg_TN(reg, 1);
517 static inline void gen_movl_reg_T2(int reg)
519 gen_movl_reg_TN(reg, 2);
522 static inline void gen_movl_TN_reg(int reg, int t)
525 gen_op_movl_TN_reg[t][reg] ();
528 static inline void gen_movl_T0_reg(int reg)
530 gen_movl_TN_reg(reg, 0);
533 static inline void gen_movl_T1_reg(int reg)
535 gen_movl_TN_reg(reg, 1);
538 static inline void gen_jmp_im(target_ulong pc)
540 #ifdef TARGET_SPARC64
541 if (pc == (uint32_t)pc) {
544 gen_op_jmp_im64(pc >> 32, pc);
551 static inline void gen_movl_npc_im(target_ulong npc)
553 #ifdef TARGET_SPARC64
554 if (npc == (uint32_t)npc) {
555 gen_op_movl_npc_im(npc);
557 gen_op_movq_npc_im64(npc >> 32, npc);
560 gen_op_movl_npc_im(npc);
564 static inline void gen_goto_tb(DisasContext *s, int tb_num,
565 target_ulong pc, target_ulong npc)
567 TranslationBlock *tb;
570 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
571 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
572 /* jump to same page: we can use a direct jump */
574 gen_op_goto_tb0(TBPARAM(tb));
576 gen_op_goto_tb1(TBPARAM(tb));
578 gen_movl_npc_im(npc);
579 gen_op_movl_T0_im((long)tb + tb_num);
582 /* jump to another page: currently not optimized */
584 gen_movl_npc_im(npc);
590 static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
594 l1 = gen_new_label();
596 gen_op_jz_T2_label(l1);
598 gen_goto_tb(dc, 0, pc1, pc1 + 4);
601 gen_goto_tb(dc, 1, pc2, pc2 + 4);
604 static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
608 l1 = gen_new_label();
610 gen_op_jz_T2_label(l1);
612 gen_goto_tb(dc, 0, pc2, pc1);
615 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
618 static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
620 gen_goto_tb(dc, 0, pc, npc);
623 static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
627 l1 = gen_new_label();
628 l2 = gen_new_label();
629 gen_op_jz_T2_label(l1);
631 gen_movl_npc_im(npc1);
632 gen_op_jmp_label(l2);
635 gen_movl_npc_im(npc2);
639 /* call this function before using T2 as it may have been set for a jump */
640 static inline void flush_T2(DisasContext * dc)
642 if (dc->npc == JUMP_PC) {
643 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
644 dc->npc = DYNAMIC_PC;
648 static inline void save_npc(DisasContext * dc)
650 if (dc->npc == JUMP_PC) {
651 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
652 dc->npc = DYNAMIC_PC;
653 } else if (dc->npc != DYNAMIC_PC) {
654 gen_movl_npc_im(dc->npc);
658 static inline void save_state(DisasContext * dc)
664 static inline void gen_mov_pc_npc(DisasContext * dc)
666 if (dc->npc == JUMP_PC) {
667 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
670 } else if (dc->npc == DYNAMIC_PC) {
678 static GenOpFunc * const gen_cond[2][16] = {
698 #ifdef TARGET_SPARC64
719 static GenOpFunc * const gen_fcond[4][16] = {
738 #ifdef TARGET_SPARC64
741 gen_op_eval_fbne_fcc1,
742 gen_op_eval_fblg_fcc1,
743 gen_op_eval_fbul_fcc1,
744 gen_op_eval_fbl_fcc1,
745 gen_op_eval_fbug_fcc1,
746 gen_op_eval_fbg_fcc1,
747 gen_op_eval_fbu_fcc1,
749 gen_op_eval_fbe_fcc1,
750 gen_op_eval_fbue_fcc1,
751 gen_op_eval_fbge_fcc1,
752 gen_op_eval_fbuge_fcc1,
753 gen_op_eval_fble_fcc1,
754 gen_op_eval_fbule_fcc1,
755 gen_op_eval_fbo_fcc1,
759 gen_op_eval_fbne_fcc2,
760 gen_op_eval_fblg_fcc2,
761 gen_op_eval_fbul_fcc2,
762 gen_op_eval_fbl_fcc2,
763 gen_op_eval_fbug_fcc2,
764 gen_op_eval_fbg_fcc2,
765 gen_op_eval_fbu_fcc2,
767 gen_op_eval_fbe_fcc2,
768 gen_op_eval_fbue_fcc2,
769 gen_op_eval_fbge_fcc2,
770 gen_op_eval_fbuge_fcc2,
771 gen_op_eval_fble_fcc2,
772 gen_op_eval_fbule_fcc2,
773 gen_op_eval_fbo_fcc2,
777 gen_op_eval_fbne_fcc3,
778 gen_op_eval_fblg_fcc3,
779 gen_op_eval_fbul_fcc3,
780 gen_op_eval_fbl_fcc3,
781 gen_op_eval_fbug_fcc3,
782 gen_op_eval_fbg_fcc3,
783 gen_op_eval_fbu_fcc3,
785 gen_op_eval_fbe_fcc3,
786 gen_op_eval_fbue_fcc3,
787 gen_op_eval_fbge_fcc3,
788 gen_op_eval_fbuge_fcc3,
789 gen_op_eval_fble_fcc3,
790 gen_op_eval_fbule_fcc3,
791 gen_op_eval_fbo_fcc3,
798 #ifdef TARGET_SPARC64
799 static void gen_cond_reg(int cond)
825 /* XXX: potentially incorrect if dynamic npc */
826 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
828 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
829 target_ulong target = dc->pc + offset;
832 /* unconditional not taken */
834 dc->pc = dc->npc + 4;
835 dc->npc = dc->pc + 4;
838 dc->npc = dc->pc + 4;
840 } else if (cond == 0x8) {
841 /* unconditional taken */
844 dc->npc = dc->pc + 4;
851 gen_cond[cc][cond]();
853 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
857 dc->jump_pc[0] = target;
858 dc->jump_pc[1] = dc->npc + 4;
864 /* XXX: potentially incorrect if dynamic npc */
865 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
867 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
868 target_ulong target = dc->pc + offset;
871 /* unconditional not taken */
873 dc->pc = dc->npc + 4;
874 dc->npc = dc->pc + 4;
877 dc->npc = dc->pc + 4;
879 } else if (cond == 0x8) {
880 /* unconditional taken */
883 dc->npc = dc->pc + 4;
890 gen_fcond[cc][cond]();
892 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
896 dc->jump_pc[0] = target;
897 dc->jump_pc[1] = dc->npc + 4;
903 #ifdef TARGET_SPARC64
904 /* XXX: potentially incorrect if dynamic npc */
905 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
907 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
908 target_ulong target = dc->pc + offset;
913 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
917 dc->jump_pc[0] = target;
918 dc->jump_pc[1] = dc->npc + 4;
923 static GenOpFunc * const gen_fcmps[4] = {
930 static GenOpFunc * const gen_fcmpd[4] = {
938 /* before an instruction, dc->pc must be static */
939 static void disas_sparc_insn(DisasContext * dc)
941 unsigned int insn, opc, rs1, rs2, rd;
943 insn = ldl_code(dc->pc);
944 opc = GET_FIELD(insn, 0, 1);
946 rd = GET_FIELD(insn, 2, 6);
948 case 0: /* branches/sethi */
950 unsigned int xop = GET_FIELD(insn, 7, 9);
953 #ifdef TARGET_SPARC64
954 case 0x1: /* V9 BPcc */
958 target = GET_FIELD_SP(insn, 0, 18);
960 target = sign_extend(target, 18);
961 cc = GET_FIELD_SP(insn, 20, 21);
963 do_branch(dc, target, insn, 0);
965 do_branch(dc, target, insn, 1);
970 case 0x3: /* V9 BPr */
972 target = GET_FIELD_SP(insn, 0, 13) |
973 (GET_FIELD_SP(insn, 20, 21) >> 7);
975 target = sign_extend(target, 16);
976 rs1 = GET_FIELD(insn, 13, 17);
977 gen_movl_reg_T0(rs1);
978 do_branch_reg(dc, target, insn);
981 case 0x5: /* V9 FBPcc */
983 int cc = GET_FIELD_SP(insn, 20, 21);
984 #if !defined(CONFIG_USER_ONLY)
985 gen_op_trap_ifnofpu();
987 target = GET_FIELD_SP(insn, 0, 18);
989 target = sign_extend(target, 19);
990 do_fbranch(dc, target, insn, cc);
996 target = GET_FIELD(insn, 10, 31);
998 target = sign_extend(target, 22);
999 do_branch(dc, target, insn, 0);
1002 case 0x6: /* FBN+x */
1004 #if !defined(CONFIG_USER_ONLY)
1005 gen_op_trap_ifnofpu();
1007 target = GET_FIELD(insn, 10, 31);
1009 target = sign_extend(target, 22);
1010 do_fbranch(dc, target, insn, 0);
1013 case 0x4: /* SETHI */
1018 uint32_t value = GET_FIELD(insn, 10, 31);
1019 gen_movl_imm_T0(value << 10);
1020 gen_movl_T0_reg(rd);
1025 case 0x0: /* UNIMPL */
1034 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1036 #ifdef TARGET_SPARC64
1037 if (dc->pc == (uint32_t)dc->pc) {
1038 gen_op_movl_T0_im(dc->pc);
1040 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1043 gen_op_movl_T0_im(dc->pc);
1045 gen_movl_T0_reg(15);
1051 case 2: /* FPU & Logical Operations */
1053 unsigned int xop = GET_FIELD(insn, 7, 12);
1054 if (xop == 0x3a) { /* generate trap */
1057 rs1 = GET_FIELD(insn, 13, 17);
1058 gen_movl_reg_T0(rs1);
1060 rs2 = GET_FIELD(insn, 25, 31);
1064 gen_movl_simm_T1(rs2);
1070 rs2 = GET_FIELD(insn, 27, 31);
1074 gen_movl_reg_T1(rs2);
1081 cond = GET_FIELD(insn, 3, 6);
1086 } else if (cond != 0) {
1087 #ifdef TARGET_SPARC64
1089 int cc = GET_FIELD_SP(insn, 11, 12);
1091 gen_cond[0][cond]();
1093 gen_cond[1][cond]();
1097 gen_cond[0][cond]();
1101 } else if (xop == 0x28) {
1102 rs1 = GET_FIELD(insn, 13, 17);
1105 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1106 gen_movl_T0_reg(rd);
1108 case 15: /* stbar / V9 membar */
1109 break; /* no effect? */
1110 #ifdef TARGET_SPARC64
1111 case 0x2: /* V9 rdccr */
1113 gen_movl_T0_reg(rd);
1115 case 0x3: /* V9 rdasi */
1116 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1117 gen_movl_T0_reg(rd);
1119 case 0x4: /* V9 rdtick */
1121 gen_movl_T0_reg(rd);
1123 case 0x5: /* V9 rdpc */
1124 gen_op_movl_T0_im(dc->pc);
1125 gen_movl_T0_reg(rd);
1127 case 0x6: /* V9 rdfprs */
1128 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1129 gen_movl_T0_reg(rd);
1131 case 0x17: /* Tick compare */
1132 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1133 gen_movl_T0_reg(rd);
1135 case 0x18: /* System tick */
1136 gen_op_rdtick(); // XXX
1137 gen_movl_T0_reg(rd);
1139 case 0x19: /* System tick compare */
1140 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1141 gen_movl_T0_reg(rd);
1143 case 0x10: /* Performance Control */
1144 case 0x11: /* Performance Instrumentation Counter */
1145 case 0x12: /* Dispatch Control */
1146 case 0x13: /* Graphics Status */
1147 case 0x14: /* Softint set, WO */
1148 case 0x15: /* Softint clear, WO */
1149 case 0x16: /* Softint write */
1154 #if !defined(CONFIG_USER_ONLY)
1155 #ifndef TARGET_SPARC64
1156 } else if (xop == 0x29) { /* rdpsr / V9 unimp */
1157 if (!supervisor(dc))
1160 gen_movl_T0_reg(rd);
1163 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1164 if (!supervisor(dc))
1166 #ifdef TARGET_SPARC64
1167 rs1 = GET_FIELD(insn, 13, 17);
1185 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1191 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1194 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1200 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1202 case 11: // canrestore
1203 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1205 case 12: // cleanwin
1206 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1208 case 13: // otherwin
1209 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1212 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1215 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1222 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1224 gen_movl_T0_reg(rd);
1226 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1227 #ifdef TARGET_SPARC64
1230 if (!supervisor(dc))
1232 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1233 gen_movl_T0_reg(rd);
1237 } else if (xop == 0x34) { /* FPU Operations */
1238 #if !defined(CONFIG_USER_ONLY)
1239 gen_op_trap_ifnofpu();
1241 rs1 = GET_FIELD(insn, 13, 17);
1242 rs2 = GET_FIELD(insn, 27, 31);
1243 xop = GET_FIELD(insn, 18, 26);
1245 case 0x1: /* fmovs */
1246 gen_op_load_fpr_FT0(rs2);
1247 gen_op_store_FT0_fpr(rd);
1249 case 0x5: /* fnegs */
1250 gen_op_load_fpr_FT1(rs2);
1252 gen_op_store_FT0_fpr(rd);
1254 case 0x9: /* fabss */
1255 gen_op_load_fpr_FT1(rs2);
1257 gen_op_store_FT0_fpr(rd);
1259 case 0x29: /* fsqrts */
1260 gen_op_load_fpr_FT1(rs2);
1262 gen_op_store_FT0_fpr(rd);
1264 case 0x2a: /* fsqrtd */
1265 gen_op_load_fpr_DT1(DFPREG(rs2));
1267 gen_op_store_DT0_fpr(DFPREG(rd));
1269 case 0x2b: /* fsqrtq */
1272 gen_op_load_fpr_FT0(rs1);
1273 gen_op_load_fpr_FT1(rs2);
1275 gen_op_store_FT0_fpr(rd);
1278 gen_op_load_fpr_DT0(DFPREG(rs1));
1279 gen_op_load_fpr_DT1(DFPREG(rs2));
1281 gen_op_store_DT0_fpr(DFPREG(rd));
1283 case 0x43: /* faddq */
1286 gen_op_load_fpr_FT0(rs1);
1287 gen_op_load_fpr_FT1(rs2);
1289 gen_op_store_FT0_fpr(rd);
1292 gen_op_load_fpr_DT0(DFPREG(rs1));
1293 gen_op_load_fpr_DT1(DFPREG(rs2));
1295 gen_op_store_DT0_fpr(DFPREG(rd));
1297 case 0x47: /* fsubq */
1300 gen_op_load_fpr_FT0(rs1);
1301 gen_op_load_fpr_FT1(rs2);
1303 gen_op_store_FT0_fpr(rd);
1306 gen_op_load_fpr_DT0(DFPREG(rs1));
1307 gen_op_load_fpr_DT1(DFPREG(rs2));
1309 gen_op_store_DT0_fpr(rd);
1311 case 0x4b: /* fmulq */
1314 gen_op_load_fpr_FT0(rs1);
1315 gen_op_load_fpr_FT1(rs2);
1317 gen_op_store_FT0_fpr(rd);
1320 gen_op_load_fpr_DT0(DFPREG(rs1));
1321 gen_op_load_fpr_DT1(DFPREG(rs2));
1323 gen_op_store_DT0_fpr(DFPREG(rd));
1325 case 0x4f: /* fdivq */
1328 gen_op_load_fpr_FT0(rs1);
1329 gen_op_load_fpr_FT1(rs2);
1331 gen_op_store_DT0_fpr(DFPREG(rd));
1333 case 0x6e: /* fdmulq */
1336 gen_op_load_fpr_FT1(rs2);
1338 gen_op_store_FT0_fpr(rd);
1341 gen_op_load_fpr_DT1(DFPREG(rs2));
1343 gen_op_store_FT0_fpr(rd);
1345 case 0xc7: /* fqtos */
1348 gen_op_load_fpr_FT1(rs2);
1350 gen_op_store_DT0_fpr(DFPREG(rd));
1353 gen_op_load_fpr_FT1(rs2);
1355 gen_op_store_DT0_fpr(DFPREG(rd));
1357 case 0xcb: /* fqtod */
1359 case 0xcc: /* fitoq */
1361 case 0xcd: /* fstoq */
1363 case 0xce: /* fdtoq */
1366 gen_op_load_fpr_FT1(rs2);
1368 gen_op_store_FT0_fpr(rd);
1371 gen_op_load_fpr_DT1(rs2);
1373 gen_op_store_FT0_fpr(rd);
1375 case 0xd3: /* fqtoi */
1377 #ifdef TARGET_SPARC64
1378 case 0x2: /* V9 fmovd */
1379 gen_op_load_fpr_DT0(DFPREG(rs2));
1380 gen_op_store_DT0_fpr(DFPREG(rd));
1382 case 0x6: /* V9 fnegd */
1383 gen_op_load_fpr_DT1(DFPREG(rs2));
1385 gen_op_store_DT0_fpr(DFPREG(rd));
1387 case 0xa: /* V9 fabsd */
1388 gen_op_load_fpr_DT1(DFPREG(rs2));
1390 gen_op_store_DT0_fpr(DFPREG(rd));
1392 case 0x81: /* V9 fstox */
1393 gen_op_load_fpr_FT1(rs2);
1395 gen_op_store_DT0_fpr(DFPREG(rd));
1397 case 0x82: /* V9 fdtox */
1398 gen_op_load_fpr_DT1(DFPREG(rs2));
1400 gen_op_store_DT0_fpr(DFPREG(rd));
1402 case 0x84: /* V9 fxtos */
1403 gen_op_load_fpr_DT1(DFPREG(rs2));
1405 gen_op_store_FT0_fpr(rd);
1407 case 0x88: /* V9 fxtod */
1408 gen_op_load_fpr_DT1(DFPREG(rs2));
1410 gen_op_store_DT0_fpr(DFPREG(rd));
1412 case 0x3: /* V9 fmovq */
1413 case 0x7: /* V9 fnegq */
1414 case 0xb: /* V9 fabsq */
1415 case 0x83: /* V9 fqtox */
1416 case 0x8c: /* V9 fxtoq */
1422 } else if (xop == 0x35) { /* FPU Operations */
1423 #ifdef TARGET_SPARC64
1426 #if !defined(CONFIG_USER_ONLY)
1427 gen_op_trap_ifnofpu();
1429 rs1 = GET_FIELD(insn, 13, 17);
1430 rs2 = GET_FIELD(insn, 27, 31);
1431 xop = GET_FIELD(insn, 18, 26);
1432 #ifdef TARGET_SPARC64
1433 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1434 cond = GET_FIELD_SP(insn, 14, 17);
1435 gen_op_load_fpr_FT0(rd);
1436 gen_op_load_fpr_FT1(rs2);
1437 rs1 = GET_FIELD(insn, 13, 17);
1438 gen_movl_reg_T0(rs1);
1442 gen_op_store_FT0_fpr(rd);
1444 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1445 cond = GET_FIELD_SP(insn, 14, 17);
1446 gen_op_load_fpr_DT0(rd);
1447 gen_op_load_fpr_DT1(rs2);
1449 rs1 = GET_FIELD(insn, 13, 17);
1450 gen_movl_reg_T0(rs1);
1453 gen_op_store_DT0_fpr(rd);
1455 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1460 #ifdef TARGET_SPARC64
1461 case 0x001: /* V9 fmovscc %fcc0 */
1462 cond = GET_FIELD_SP(insn, 14, 17);
1463 gen_op_load_fpr_FT0(rd);
1464 gen_op_load_fpr_FT1(rs2);
1466 gen_fcond[0][cond]();
1468 gen_op_store_FT0_fpr(rd);
1470 case 0x002: /* V9 fmovdcc %fcc0 */
1471 cond = GET_FIELD_SP(insn, 14, 17);
1472 gen_op_load_fpr_DT0(rd);
1473 gen_op_load_fpr_DT1(rs2);
1475 gen_fcond[0][cond]();
1477 gen_op_store_DT0_fpr(rd);
1479 case 0x003: /* V9 fmovqcc %fcc0 */
1481 case 0x041: /* V9 fmovscc %fcc1 */
1482 cond = GET_FIELD_SP(insn, 14, 17);
1483 gen_op_load_fpr_FT0(rd);
1484 gen_op_load_fpr_FT1(rs2);
1486 gen_fcond[1][cond]();
1488 gen_op_store_FT0_fpr(rd);
1490 case 0x042: /* V9 fmovdcc %fcc1 */
1491 cond = GET_FIELD_SP(insn, 14, 17);
1492 gen_op_load_fpr_DT0(rd);
1493 gen_op_load_fpr_DT1(rs2);
1495 gen_fcond[1][cond]();
1497 gen_op_store_DT0_fpr(rd);
1499 case 0x043: /* V9 fmovqcc %fcc1 */
1501 case 0x081: /* V9 fmovscc %fcc2 */
1502 cond = GET_FIELD_SP(insn, 14, 17);
1503 gen_op_load_fpr_FT0(rd);
1504 gen_op_load_fpr_FT1(rs2);
1506 gen_fcond[2][cond]();
1508 gen_op_store_FT0_fpr(rd);
1510 case 0x082: /* V9 fmovdcc %fcc2 */
1511 cond = GET_FIELD_SP(insn, 14, 17);
1512 gen_op_load_fpr_DT0(rd);
1513 gen_op_load_fpr_DT1(rs2);
1515 gen_fcond[2][cond]();
1517 gen_op_store_DT0_fpr(rd);
1519 case 0x083: /* V9 fmovqcc %fcc2 */
1521 case 0x0c1: /* V9 fmovscc %fcc3 */
1522 cond = GET_FIELD_SP(insn, 14, 17);
1523 gen_op_load_fpr_FT0(rd);
1524 gen_op_load_fpr_FT1(rs2);
1526 gen_fcond[3][cond]();
1528 gen_op_store_FT0_fpr(rd);
1530 case 0x0c2: /* V9 fmovdcc %fcc3 */
1531 cond = GET_FIELD_SP(insn, 14, 17);
1532 gen_op_load_fpr_DT0(rd);
1533 gen_op_load_fpr_DT1(rs2);
1535 gen_fcond[3][cond]();
1537 gen_op_store_DT0_fpr(rd);
1539 case 0x0c3: /* V9 fmovqcc %fcc3 */
1541 case 0x101: /* V9 fmovscc %icc */
1542 cond = GET_FIELD_SP(insn, 14, 17);
1543 gen_op_load_fpr_FT0(rd);
1544 gen_op_load_fpr_FT1(rs2);
1546 gen_cond[0][cond]();
1548 gen_op_store_FT0_fpr(rd);
1550 case 0x102: /* V9 fmovdcc %icc */
1551 cond = GET_FIELD_SP(insn, 14, 17);
1552 gen_op_load_fpr_DT0(rd);
1553 gen_op_load_fpr_DT1(rs2);
1555 gen_cond[0][cond]();
1557 gen_op_store_DT0_fpr(rd);
1559 case 0x103: /* V9 fmovqcc %icc */
1561 case 0x181: /* V9 fmovscc %xcc */
1562 cond = GET_FIELD_SP(insn, 14, 17);
1563 gen_op_load_fpr_FT0(rd);
1564 gen_op_load_fpr_FT1(rs2);
1566 gen_cond[1][cond]();
1568 gen_op_store_FT0_fpr(rd);
1570 case 0x182: /* V9 fmovdcc %xcc */
1571 cond = GET_FIELD_SP(insn, 14, 17);
1572 gen_op_load_fpr_DT0(rd);
1573 gen_op_load_fpr_DT1(rs2);
1575 gen_cond[1][cond]();
1577 gen_op_store_DT0_fpr(rd);
1579 case 0x183: /* V9 fmovqcc %xcc */
1582 case 0x51: /* V9 %fcc */
1583 gen_op_load_fpr_FT0(rs1);
1584 gen_op_load_fpr_FT1(rs2);
1585 #ifdef TARGET_SPARC64
1586 gen_fcmps[rd & 3]();
1591 case 0x52: /* V9 %fcc */
1592 gen_op_load_fpr_DT0(DFPREG(rs1));
1593 gen_op_load_fpr_DT1(DFPREG(rs2));
1594 #ifdef TARGET_SPARC64
1595 gen_fcmpd[rd & 3]();
1600 case 0x53: /* fcmpq */
1602 case 0x55: /* fcmpes, V9 %fcc */
1603 gen_op_load_fpr_FT0(rs1);
1604 gen_op_load_fpr_FT1(rs2);
1605 #ifdef TARGET_SPARC64
1606 gen_fcmps[rd & 3]();
1608 gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */
1611 case 0x56: /* fcmped, V9 %fcc */
1612 gen_op_load_fpr_DT0(DFPREG(rs1));
1613 gen_op_load_fpr_DT1(DFPREG(rs2));
1614 #ifdef TARGET_SPARC64
1615 gen_fcmpd[rd & 3]();
1617 gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */
1620 case 0x57: /* fcmpeq */
1626 } else if (xop == 0x2) {
1629 rs1 = GET_FIELD(insn, 13, 17);
1631 // or %g0, x, y -> mov T1, x; mov y, T1
1632 if (IS_IMM) { /* immediate */
1633 rs2 = GET_FIELDs(insn, 19, 31);
1634 gen_movl_simm_T1(rs2);
1635 } else { /* register */
1636 rs2 = GET_FIELD(insn, 27, 31);
1637 gen_movl_reg_T1(rs2);
1639 gen_movl_T1_reg(rd);
1641 gen_movl_reg_T0(rs1);
1642 if (IS_IMM) { /* immediate */
1643 // or x, #0, y -> mov T1, x; mov y, T1
1644 rs2 = GET_FIELDs(insn, 19, 31);
1646 gen_movl_simm_T1(rs2);
1649 } else { /* register */
1650 // or x, %g0, y -> mov T1, x; mov y, T1
1651 rs2 = GET_FIELD(insn, 27, 31);
1653 gen_movl_reg_T1(rs2);
1657 gen_movl_T0_reg(rd);
1660 #ifdef TARGET_SPARC64
1661 } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
1662 rs1 = GET_FIELD(insn, 13, 17);
1663 gen_movl_reg_T0(rs1);
1664 if (IS_IMM) { /* immediate */
1665 rs2 = GET_FIELDs(insn, 20, 31);
1666 gen_movl_simm_T1(rs2);
1667 } else { /* register */
1668 rs2 = GET_FIELD(insn, 27, 31);
1669 gen_movl_reg_T1(rs2);
1672 gen_movl_T0_reg(rd);
1673 } else if (xop == 0x26) { /* srl, V9 srlx */
1674 rs1 = GET_FIELD(insn, 13, 17);
1675 gen_movl_reg_T0(rs1);
1676 if (IS_IMM) { /* immediate */
1677 rs2 = GET_FIELDs(insn, 20, 31);
1678 gen_movl_simm_T1(rs2);
1679 } else { /* register */
1680 rs2 = GET_FIELD(insn, 27, 31);
1681 gen_movl_reg_T1(rs2);
1683 if (insn & (1 << 12))
1687 gen_movl_T0_reg(rd);
1688 } else if (xop == 0x27) { /* sra, V9 srax */
1689 rs1 = GET_FIELD(insn, 13, 17);
1690 gen_movl_reg_T0(rs1);
1691 if (IS_IMM) { /* immediate */
1692 rs2 = GET_FIELDs(insn, 20, 31);
1693 gen_movl_simm_T1(rs2);
1694 } else { /* register */
1695 rs2 = GET_FIELD(insn, 27, 31);
1696 gen_movl_reg_T1(rs2);
1698 if (insn & (1 << 12))
1702 gen_movl_T0_reg(rd);
1704 } else if (xop < 0x38) {
1705 rs1 = GET_FIELD(insn, 13, 17);
1706 gen_movl_reg_T0(rs1);
1707 if (IS_IMM) { /* immediate */
1708 rs2 = GET_FIELDs(insn, 19, 31);
1709 gen_movl_simm_T1(rs2);
1710 } else { /* register */
1711 rs2 = GET_FIELD(insn, 27, 31);
1712 gen_movl_reg_T1(rs2);
1715 switch (xop & ~0x10) {
1718 gen_op_add_T1_T0_cc();
1725 gen_op_logic_T0_cc();
1730 gen_op_logic_T0_cc();
1735 gen_op_logic_T0_cc();
1739 gen_op_sub_T1_T0_cc();
1744 gen_op_andn_T1_T0();
1746 gen_op_logic_T0_cc();
1751 gen_op_logic_T0_cc();
1754 gen_op_xnor_T1_T0();
1756 gen_op_logic_T0_cc();
1760 gen_op_addx_T1_T0_cc();
1762 gen_op_addx_T1_T0();
1765 gen_op_umul_T1_T0();
1767 gen_op_logic_T0_cc();
1770 gen_op_smul_T1_T0();
1772 gen_op_logic_T0_cc();
1776 gen_op_subx_T1_T0_cc();
1778 gen_op_subx_T1_T0();
1781 gen_op_udiv_T1_T0();
1786 gen_op_sdiv_T1_T0();
1793 gen_movl_T0_reg(rd);
1796 #ifdef TARGET_SPARC64
1797 case 0x9: /* V9 mulx */
1798 gen_op_mulx_T1_T0();
1799 gen_movl_T0_reg(rd);
1801 case 0xd: /* V9 udivx */
1802 gen_op_udivx_T1_T0();
1803 gen_movl_T0_reg(rd);
1806 case 0x20: /* taddcc */
1807 case 0x21: /* tsubcc */
1808 case 0x22: /* taddcctv */
1809 case 0x23: /* tsubcctv */
1811 case 0x24: /* mulscc */
1812 gen_op_mulscc_T1_T0();
1813 gen_movl_T0_reg(rd);
1815 #ifndef TARGET_SPARC64
1816 case 0x25: /* sll */
1818 gen_movl_T0_reg(rd);
1820 case 0x26: /* srl */
1822 gen_movl_T0_reg(rd);
1824 case 0x27: /* sra */
1826 gen_movl_T0_reg(rd);
1834 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1836 #ifdef TARGET_SPARC64
1837 case 0x2: /* V9 wrccr */
1840 case 0x3: /* V9 wrasi */
1841 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1843 case 0x6: /* V9 wrfprs */
1844 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1846 case 0xf: /* V9 sir, nop if user */
1847 #if !defined(CONFIG_USER_ONLY)
1852 case 0x17: /* Tick compare */
1853 #if !defined(CONFIG_USER_ONLY)
1854 if (!supervisor(dc))
1857 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1859 case 0x18: /* System tick */
1860 #if !defined(CONFIG_USER_ONLY)
1861 if (!supervisor(dc))
1864 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1866 case 0x19: /* System tick compare */
1867 #if !defined(CONFIG_USER_ONLY)
1868 if (!supervisor(dc))
1871 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
1874 case 0x10: /* Performance Control */
1875 case 0x11: /* Performance Instrumentation Counter */
1876 case 0x12: /* Dispatch Control */
1877 case 0x13: /* Graphics Status */
1878 case 0x14: /* Softint set */
1879 case 0x15: /* Softint clear */
1880 case 0x16: /* Softint write */
1887 #if !defined(CONFIG_USER_ONLY)
1888 case 0x31: /* wrpsr, V9 saved, restored */
1890 if (!supervisor(dc))
1892 #ifdef TARGET_SPARC64
1914 case 0x32: /* wrwim, V9 wrpr */
1916 if (!supervisor(dc))
1919 #ifdef TARGET_SPARC64
1937 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
1943 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1946 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1952 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1954 case 11: // canrestore
1955 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1957 case 12: // cleanwin
1958 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1960 case 13: // otherwin
1961 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1964 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1970 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1974 #ifndef TARGET_SPARC64
1975 case 0x33: /* wrtbr, V9 unimp */
1977 if (!supervisor(dc))
1980 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
1985 #ifdef TARGET_SPARC64
1986 case 0x2c: /* V9 movcc */
1988 int cc = GET_FIELD_SP(insn, 11, 12);
1989 int cond = GET_FIELD_SP(insn, 14, 17);
1990 if (IS_IMM) { /* immediate */
1991 rs2 = GET_FIELD_SPs(insn, 0, 10);
1992 gen_movl_simm_T1(rs2);
1995 rs2 = GET_FIELD_SP(insn, 0, 4);
1996 gen_movl_reg_T1(rs2);
1998 gen_movl_reg_T0(rd);
2000 if (insn & (1 << 18)) {
2002 gen_cond[0][cond]();
2004 gen_cond[1][cond]();
2008 gen_fcond[cc][cond]();
2011 gen_movl_T0_reg(rd);
2014 case 0x2d: /* V9 sdivx */
2015 gen_op_sdivx_T1_T0();
2016 gen_movl_T0_reg(rd);
2018 case 0x2e: /* V9 popc */
2020 if (IS_IMM) { /* immediate */
2021 rs2 = GET_FIELD_SPs(insn, 0, 12);
2022 gen_movl_simm_T1(rs2);
2023 // XXX optimize: popc(constant)
2026 rs2 = GET_FIELD_SP(insn, 0, 4);
2027 gen_movl_reg_T1(rs2);
2030 gen_movl_T0_reg(rd);
2032 case 0x2f: /* V9 movr */
2034 int cond = GET_FIELD_SP(insn, 10, 12);
2035 rs1 = GET_FIELD(insn, 13, 17);
2037 gen_movl_reg_T0(rs1);
2039 if (IS_IMM) { /* immediate */
2040 rs2 = GET_FIELD_SPs(insn, 0, 10);
2041 gen_movl_simm_T1(rs2);
2044 rs2 = GET_FIELD_SP(insn, 0, 4);
2045 gen_movl_reg_T1(rs2);
2047 gen_movl_reg_T0(rd);
2049 gen_movl_T0_reg(rd);
2052 case 0x36: /* UltraSparc shutdown, VIS */
2061 #ifdef TARGET_SPARC64
2062 } else if (xop == 0x39) { /* V9 return */
2063 rs1 = GET_FIELD(insn, 13, 17);
2064 gen_movl_reg_T0(rs1);
2065 if (IS_IMM) { /* immediate */
2066 rs2 = GET_FIELDs(insn, 19, 31);
2070 gen_movl_simm_T1(rs2);
2075 } else { /* register */
2076 rs2 = GET_FIELD(insn, 27, 31);
2080 gen_movl_reg_T1(rs2);
2088 gen_op_movl_npc_T0();
2089 dc->npc = DYNAMIC_PC;
2093 rs1 = GET_FIELD(insn, 13, 17);
2094 gen_movl_reg_T0(rs1);
2095 if (IS_IMM) { /* immediate */
2096 rs2 = GET_FIELDs(insn, 19, 31);
2100 gen_movl_simm_T1(rs2);
2105 } else { /* register */
2106 rs2 = GET_FIELD(insn, 27, 31);
2110 gen_movl_reg_T1(rs2);
2117 case 0x38: /* jmpl */
2120 gen_op_movl_T1_im(dc->pc);
2121 gen_movl_T1_reg(rd);
2124 gen_op_movl_npc_T0();
2125 dc->npc = DYNAMIC_PC;
2128 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2129 case 0x39: /* rett, V9 return */
2131 if (!supervisor(dc))
2134 gen_op_movl_npc_T0();
2135 dc->npc = DYNAMIC_PC;
2140 case 0x3b: /* flush */
2143 case 0x3c: /* save */
2146 gen_movl_T0_reg(rd);
2148 case 0x3d: /* restore */
2151 gen_movl_T0_reg(rd);
2153 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2154 case 0x3e: /* V9 done/retry */
2158 if (!supervisor(dc))
2160 dc->npc = DYNAMIC_PC;
2161 dc->pc = DYNAMIC_PC;
2165 if (!supervisor(dc))
2167 dc->npc = DYNAMIC_PC;
2168 dc->pc = DYNAMIC_PC;
2184 case 3: /* load/store instructions */
2186 unsigned int xop = GET_FIELD(insn, 7, 12);
2187 rs1 = GET_FIELD(insn, 13, 17);
2188 gen_movl_reg_T0(rs1);
2189 if (IS_IMM) { /* immediate */
2190 rs2 = GET_FIELDs(insn, 19, 31);
2194 gen_movl_simm_T1(rs2);
2199 } else { /* register */
2200 rs2 = GET_FIELD(insn, 27, 31);
2204 gen_movl_reg_T1(rs2);
2210 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2211 (xop > 0x17 && xop < 0x1d ) || \
2212 (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
2214 case 0x0: /* load word */
2217 case 0x1: /* load unsigned byte */
2220 case 0x2: /* load unsigned halfword */
2223 case 0x3: /* load double word */
2225 gen_movl_T0_reg(rd + 1);
2227 case 0x9: /* load signed byte */
2230 case 0xa: /* load signed halfword */
2233 case 0xd: /* ldstub -- XXX: should be atomically */
2234 gen_op_ldst(ldstub);
2236 case 0x0f: /* swap register with memory. Also atomically */
2237 gen_movl_reg_T1(rd);
2240 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2241 case 0x10: /* load word alternate */
2242 #ifndef TARGET_SPARC64
2243 if (!supervisor(dc))
2246 gen_op_lda(insn, 1, 4, 0);
2248 case 0x11: /* load unsigned byte alternate */
2249 #ifndef TARGET_SPARC64
2250 if (!supervisor(dc))
2253 gen_op_lduba(insn, 1, 1, 0);
2255 case 0x12: /* load unsigned halfword alternate */
2256 #ifndef TARGET_SPARC64
2257 if (!supervisor(dc))
2260 gen_op_lduha(insn, 1, 2, 0);
2262 case 0x13: /* load double word alternate */
2263 #ifndef TARGET_SPARC64
2264 if (!supervisor(dc))
2267 gen_op_ldda(insn, 1, 8, 0);
2268 gen_movl_T0_reg(rd + 1);
2270 case 0x19: /* load signed byte alternate */
2271 #ifndef TARGET_SPARC64
2272 if (!supervisor(dc))
2275 gen_op_ldsba(insn, 1, 1, 1);
2277 case 0x1a: /* load signed halfword alternate */
2278 #ifndef TARGET_SPARC64
2279 if (!supervisor(dc))
2282 gen_op_ldsha(insn, 1, 2 ,1);
2284 case 0x1d: /* ldstuba -- XXX: should be atomically */
2285 #ifndef TARGET_SPARC64
2286 if (!supervisor(dc))
2289 gen_op_ldstuba(insn, 1, 1, 0);
2291 case 0x1f: /* swap reg with alt. memory. Also atomically */
2292 #ifndef TARGET_SPARC64
2293 if (!supervisor(dc))
2296 gen_movl_reg_T1(rd);
2297 gen_op_swapa(insn, 1, 4, 0);
2300 #ifndef TARGET_SPARC64
2301 /* avoid warnings */
2302 (void) &gen_op_stfa;
2303 (void) &gen_op_stdfa;
2304 (void) &gen_op_ldfa;
2305 (void) &gen_op_lddfa;
2307 #if !defined(CONFIG_USER_ONLY)
2309 (void) &gen_op_casx;
2313 #ifdef TARGET_SPARC64
2314 case 0x08: /* V9 ldsw */
2317 case 0x0b: /* V9 ldx */
2320 case 0x18: /* V9 ldswa */
2321 gen_op_ldswa(insn, 1, 4, 1);
2323 case 0x1b: /* V9 ldxa */
2324 gen_op_ldxa(insn, 1, 8, 0);
2326 case 0x2d: /* V9 prefetch, no effect */
2328 case 0x30: /* V9 ldfa */
2329 gen_op_ldfa(insn, 1, 8, 0); // XXX
2331 case 0x33: /* V9 lddfa */
2332 gen_op_lddfa(insn, 1, 8, 0); // XXX
2335 case 0x3d: /* V9 prefetcha, no effect */
2337 case 0x32: /* V9 ldqfa */
2343 gen_movl_T1_reg(rd);
2344 #ifdef TARGET_SPARC64
2347 } else if (xop >= 0x20 && xop < 0x24) {
2348 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2349 gen_op_trap_ifnofpu();
2352 case 0x20: /* load fpreg */
2354 gen_op_store_FT0_fpr(rd);
2356 case 0x21: /* load fsr */
2360 case 0x22: /* load quad fpreg */
2362 case 0x23: /* load double fpreg */
2364 gen_op_store_DT0_fpr(DFPREG(rd));
2369 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2370 xop == 0xe || xop == 0x1e) {
2371 gen_movl_reg_T1(rd);
2384 gen_movl_reg_T2(rd + 1);
2387 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2389 #ifndef TARGET_SPARC64
2390 if (!supervisor(dc))
2393 gen_op_sta(insn, 0, 4, 0);
2396 #ifndef TARGET_SPARC64
2397 if (!supervisor(dc))
2400 gen_op_stba(insn, 0, 1, 0);
2403 #ifndef TARGET_SPARC64
2404 if (!supervisor(dc))
2407 gen_op_stha(insn, 0, 2, 0);
2410 #ifndef TARGET_SPARC64
2411 if (!supervisor(dc))
2415 gen_movl_reg_T2(rd + 1);
2416 gen_op_stda(insn, 0, 8, 0);
2419 #ifdef TARGET_SPARC64
2420 case 0x0e: /* V9 stx */
2423 case 0x1e: /* V9 stxa */
2424 gen_op_stxa(insn, 0, 8, 0); // XXX
2430 } else if (xop > 0x23 && xop < 0x28) {
2431 #if !defined(CONFIG_USER_ONLY)
2432 gen_op_trap_ifnofpu();
2436 gen_op_load_fpr_FT0(rd);
2439 case 0x25: /* stfsr, V9 stxfsr */
2443 case 0x26: /* stdfq */
2446 gen_op_load_fpr_DT0(DFPREG(rd));
2452 } else if (xop > 0x33 && xop < 0x3f) {
2453 #ifdef TARGET_SPARC64
2455 case 0x34: /* V9 stfa */
2456 gen_op_stfa(insn, 0, 0, 0); // XXX
2458 case 0x37: /* V9 stdfa */
2459 gen_op_stdfa(insn, 0, 0, 0); // XXX
2461 case 0x3c: /* V9 casa */
2462 gen_op_casa(insn, 0, 4, 0); // XXX
2464 case 0x3e: /* V9 casxa */
2465 gen_op_casxa(insn, 0, 8, 0); // XXX
2467 case 0x36: /* V9 stqfa */
2481 /* default case for non jump instructions */
2482 if (dc->npc == DYNAMIC_PC) {
2483 dc->pc = DYNAMIC_PC;
2485 } else if (dc->npc == JUMP_PC) {
2486 /* we can do a static jump */
2487 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
2491 dc->npc = dc->npc + 4;
2497 gen_op_exception(TT_ILL_INSN);
2500 #if !defined(CONFIG_USER_ONLY)
2503 gen_op_exception(TT_PRIV_INSN);
2509 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2513 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
2514 int spc, CPUSPARCState *env)
2516 target_ulong pc_start, last_pc;
2517 uint16_t *gen_opc_end;
2518 DisasContext dc1, *dc = &dc1;
2521 memset(dc, 0, sizeof(DisasContext));
2526 dc->npc = (target_ulong) tb->cs_base;
2527 #if defined(CONFIG_USER_ONLY)
2530 dc->mem_idx = ((env->psrs) != 0);
2532 gen_opc_ptr = gen_opc_buf;
2533 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2534 gen_opparam_ptr = gen_opparam_buf;
2538 if (env->nb_breakpoints > 0) {
2539 for(j = 0; j < env->nb_breakpoints; j++) {
2540 if (env->breakpoints[j] == dc->pc) {
2541 if (dc->pc != pc_start)
2553 fprintf(logfile, "Search PC...\n");
2554 j = gen_opc_ptr - gen_opc_buf;
2558 gen_opc_instr_start[lj++] = 0;
2559 gen_opc_pc[lj] = dc->pc;
2560 gen_opc_npc[lj] = dc->npc;
2561 gen_opc_instr_start[lj] = 1;
2565 disas_sparc_insn(dc);
2569 /* if the next PC is different, we abort now */
2570 if (dc->pc != (last_pc + 4))
2572 /* if we reach a page boundary, we stop generation so that the
2573 PC of a TT_TFAULT exception is always in the right page */
2574 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2576 /* if single step mode, we generate only one instruction and
2577 generate an exception */
2578 if (env->singlestep_enabled) {
2584 } while ((gen_opc_ptr < gen_opc_end) &&
2585 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
2589 if (dc->pc != DYNAMIC_PC &&
2590 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2591 /* static PC and NPC: we can use direct chaining */
2592 gen_branch(dc, (long)tb, dc->pc, dc->npc);
2594 if (dc->pc != DYNAMIC_PC)
2601 *gen_opc_ptr = INDEX_op_end;
2603 j = gen_opc_ptr - gen_opc_buf;
2606 gen_opc_instr_start[lj++] = 0;
2613 gen_opc_jump_pc[0] = dc->jump_pc[0];
2614 gen_opc_jump_pc[1] = dc->jump_pc[1];
2616 tb->size = last_pc + 4 - pc_start;
2619 if (loglevel & CPU_LOG_TB_IN_ASM) {
2620 fprintf(logfile, "--------------\n");
2621 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2622 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
2623 fprintf(logfile, "\n");
2624 if (loglevel & CPU_LOG_TB_OP) {
2625 fprintf(logfile, "OP:\n");
2626 dump_ops(gen_opc_buf, gen_opparam_buf);
2627 fprintf(logfile, "\n");
2634 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
2636 return gen_intermediate_code_internal(tb, 0, env);
2639 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
2641 return gen_intermediate_code_internal(tb, 1, env);
2644 extern int ram_size;
2646 void cpu_reset(CPUSPARCState *env)
2648 memset(env, 0, sizeof(*env));
2652 env->regwptr = env->regbase + (env->cwp * 16);
2653 #if defined(CONFIG_USER_ONLY)
2654 env->user_mode_only = 1;
2658 env->gregs[1] = ram_size;
2659 #ifdef TARGET_SPARC64
2660 env->pstate = PS_PRIV;
2661 env->version = GET_VER(env);
2662 env->pc = 0x1fff0000000ULL;
2664 env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
2665 env->pc = 0xffd00000;
2667 env->npc = env->pc + 4;
2671 CPUSPARCState *cpu_sparc_init(void)
2675 env = qemu_mallocz(sizeof(CPUSPARCState));
2683 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2685 void cpu_dump_state(CPUState *env, FILE *f,
2686 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2691 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
2692 cpu_fprintf(f, "General Registers:\n");
2693 for (i = 0; i < 4; i++)
2694 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
2695 cpu_fprintf(f, "\n");
2697 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
2698 cpu_fprintf(f, "\nCurrent Register Window:\n");
2699 for (x = 0; x < 3; x++) {
2700 for (i = 0; i < 4; i++)
2701 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
2702 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2703 env->regwptr[i + x * 8]);
2704 cpu_fprintf(f, "\n");
2706 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
2707 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2708 env->regwptr[i + x * 8]);
2709 cpu_fprintf(f, "\n");
2711 cpu_fprintf(f, "\nFloating Point Registers:\n");
2712 for (i = 0; i < 32; i++) {
2714 cpu_fprintf(f, "%%f%02d:", i);
2715 cpu_fprintf(f, " %016lf", env->fpr[i]);
2717 cpu_fprintf(f, "\n");
2719 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
2720 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2721 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
2722 env->psrs?'S':'-', env->psrps?'P':'-',
2723 env->psret?'E':'-', env->wim);
2724 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
2727 #if defined(CONFIG_USER_ONLY)
2728 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
2734 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2735 int *access_index, target_ulong address, int rw,
2738 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
2740 target_phys_addr_t phys_addr;
2741 int prot, access_index;
2743 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
2749 void helper_flush(target_ulong addr)
2752 tb_invalidate_page_range(addr, addr + 8);