4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
43 #define DYNAMIC_PC 1 /* dynamic pc value */
44 #define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
47 typedef struct DisasContext {
48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
54 struct TranslationBlock *tb;
58 const unsigned char *name;
59 target_ulong iu_version;
64 static uint16_t *gen_opc_ptr;
65 static uint32_t *gen_opparam_ptr;
70 #define DEF(s,n,copy_size) INDEX_op_ ## s,
78 // This function uses non-native bit order
79 #define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
82 // This function uses the order in the manuals, i.e. bit 0 is 2^0
83 #define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
86 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
87 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
90 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
92 #define DFPREG(r) (r & 0x1e)
95 #ifdef USE_DIRECT_JUMP
98 #define TBPARAM(x) (long)(x)
101 static int sign_extend(int x, int len)
104 return (x << len) >> len;
107 #define IS_IMM (insn & (1<<13))
109 static void disas_sparc_insn(DisasContext * dc);
111 static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
182 static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
287 static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
293 // Sign extending version
294 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
300 #ifdef TARGET_SPARC64
301 #define GEN32(func, NAME) \
302 static GenOpFunc * const NAME ## _table [64] = { \
303 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
316 static inline void func(int n) \
318 NAME ## _table[n](); \
321 #define GEN32(func, NAME) \
322 static GenOpFunc *const NAME ## _table [32] = { \
323 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
332 static inline void func(int n) \
334 NAME ## _table[n](); \
338 /* floating point registers moves */
339 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
341 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
344 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
346 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
349 #ifdef ALIGN_7_BUGS_FIXED
351 #ifndef CONFIG_USER_ONLY
352 #define gen_op_check_align_T0_7()
357 #ifdef CONFIG_USER_ONLY
358 #define supervisor(dc) 0
359 #ifdef TARGET_SPARC64
360 #define hypervisor(dc) 0
362 #define gen_op_ldst(name) gen_op_##name##_raw()
364 #define supervisor(dc) (dc->mem_idx == 1)
365 #ifdef TARGET_SPARC64
366 #define hypervisor(dc) (dc->mem_idx == 2)
368 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
369 #define OP_LD_TABLE(width) \
370 static GenOpFunc * const gen_op_##width[] = { \
371 &gen_op_##width##_user, \
372 &gen_op_##width##_kernel, \
376 #ifndef CONFIG_USER_ONLY
394 #ifdef TARGET_SPARC64
403 #ifdef TARGET_SPARC64
404 static inline void gen_ld_asi(int insn, int size, int sign)
409 offset = GET_FIELD(insn, 25, 31);
410 gen_op_ld_asi_reg(offset, size, sign);
412 asi = GET_FIELD(insn, 19, 26);
413 gen_op_ld_asi(asi, size, sign);
417 static inline void gen_st_asi(int insn, int size)
422 offset = GET_FIELD(insn, 25, 31);
423 gen_op_st_asi_reg(offset, size);
425 asi = GET_FIELD(insn, 19, 26);
426 gen_op_st_asi(asi, size);
430 static inline void gen_ldf_asi(int insn, int size)
434 rd = DFPREG(GET_FIELD(insn, 2, 6));
436 offset = GET_FIELD(insn, 25, 31);
437 gen_op_ldf_asi_reg(offset, size, rd);
439 asi = GET_FIELD(insn, 19, 26);
440 gen_op_ldf_asi(asi, size, rd);
444 static inline void gen_stf_asi(int insn, int size)
448 rd = DFPREG(GET_FIELD(insn, 2, 6));
450 offset = GET_FIELD(insn, 25, 31);
451 gen_op_stf_asi_reg(offset, size, rd);
453 asi = GET_FIELD(insn, 19, 26);
454 gen_op_stf_asi(asi, size, rd);
458 static inline void gen_swap_asi(int insn)
463 offset = GET_FIELD(insn, 25, 31);
464 gen_op_swap_asi_reg(offset);
466 asi = GET_FIELD(insn, 19, 26);
467 gen_op_swap_asi(asi);
471 static inline void gen_ldstub_asi(int insn)
476 offset = GET_FIELD(insn, 25, 31);
477 gen_op_ldstub_asi_reg(offset);
479 asi = GET_FIELD(insn, 19, 26);
480 gen_op_ldstub_asi(asi);
484 static inline void gen_ldda_asi(int insn)
489 offset = GET_FIELD(insn, 25, 31);
490 gen_op_ldda_asi_reg(offset);
492 asi = GET_FIELD(insn, 19, 26);
493 gen_op_ldda_asi(asi);
497 static inline void gen_stda_asi(int insn)
502 offset = GET_FIELD(insn, 25, 31);
503 gen_op_stda_asi_reg(offset);
505 asi = GET_FIELD(insn, 19, 26);
506 gen_op_stda_asi(asi);
510 static inline void gen_cas_asi(int insn)
515 offset = GET_FIELD(insn, 25, 31);
516 gen_op_cas_asi_reg(offset);
518 asi = GET_FIELD(insn, 19, 26);
523 static inline void gen_casx_asi(int insn)
528 offset = GET_FIELD(insn, 25, 31);
529 gen_op_casx_asi_reg(offset);
531 asi = GET_FIELD(insn, 19, 26);
532 gen_op_casx_asi(asi);
536 #elif !defined(CONFIG_USER_ONLY)
538 static inline void gen_ld_asi(int insn, int size, int sign)
542 asi = GET_FIELD(insn, 19, 26);
543 gen_op_ld_asi(asi, size, sign);
546 static inline void gen_st_asi(int insn, int size)
550 asi = GET_FIELD(insn, 19, 26);
551 gen_op_st_asi(asi, size);
554 static inline void gen_ldstub_asi(int insn)
558 asi = GET_FIELD(insn, 19, 26);
559 gen_op_ldstub_asi(asi);
562 static inline void gen_swap_asi(int insn)
566 asi = GET_FIELD(insn, 19, 26);
567 gen_op_swap_asi(asi);
570 static inline void gen_ldda_asi(int insn)
574 asi = GET_FIELD(insn, 19, 26);
575 gen_op_ld_asi(asi, 8, 0);
578 static inline void gen_stda_asi(int insn)
582 asi = GET_FIELD(insn, 19, 26);
583 gen_op_st_asi(asi, 8);
587 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
589 gen_op_movl_TN_im[reg](imm);
592 static inline void gen_movl_imm_T1(uint32_t val)
594 gen_movl_imm_TN(1, val);
597 static inline void gen_movl_imm_T0(uint32_t val)
599 gen_movl_imm_TN(0, val);
602 static inline void gen_movl_simm_TN(int reg, int32_t imm)
604 gen_op_movl_TN_sim[reg](imm);
607 static inline void gen_movl_simm_T1(int32_t val)
609 gen_movl_simm_TN(1, val);
612 static inline void gen_movl_simm_T0(int32_t val)
614 gen_movl_simm_TN(0, val);
617 static inline void gen_movl_reg_TN(int reg, int t)
620 gen_op_movl_reg_TN[t][reg] ();
622 gen_movl_imm_TN(t, 0);
625 static inline void gen_movl_reg_T0(int reg)
627 gen_movl_reg_TN(reg, 0);
630 static inline void gen_movl_reg_T1(int reg)
632 gen_movl_reg_TN(reg, 1);
635 static inline void gen_movl_reg_T2(int reg)
637 gen_movl_reg_TN(reg, 2);
640 static inline void gen_movl_TN_reg(int reg, int t)
643 gen_op_movl_TN_reg[t][reg] ();
646 static inline void gen_movl_T0_reg(int reg)
648 gen_movl_TN_reg(reg, 0);
651 static inline void gen_movl_T1_reg(int reg)
653 gen_movl_TN_reg(reg, 1);
656 static inline void gen_jmp_im(target_ulong pc)
658 #ifdef TARGET_SPARC64
659 if (pc == (uint32_t)pc) {
662 gen_op_jmp_im64(pc >> 32, pc);
669 static inline void gen_movl_npc_im(target_ulong npc)
671 #ifdef TARGET_SPARC64
672 if (npc == (uint32_t)npc) {
673 gen_op_movl_npc_im(npc);
675 gen_op_movq_npc_im64(npc >> 32, npc);
678 gen_op_movl_npc_im(npc);
682 static inline void gen_goto_tb(DisasContext *s, int tb_num,
683 target_ulong pc, target_ulong npc)
685 TranslationBlock *tb;
688 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
689 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
690 /* jump to same page: we can use a direct jump */
692 gen_op_goto_tb0(TBPARAM(tb));
694 gen_op_goto_tb1(TBPARAM(tb));
696 gen_movl_npc_im(npc);
697 gen_op_movl_T0_im((long)tb + tb_num);
700 /* jump to another page: currently not optimized */
702 gen_movl_npc_im(npc);
708 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
713 l1 = gen_new_label();
715 gen_op_jz_T2_label(l1);
717 gen_goto_tb(dc, 0, pc1, pc1 + 4);
720 gen_goto_tb(dc, 1, pc2, pc2 + 4);
723 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
728 l1 = gen_new_label();
730 gen_op_jz_T2_label(l1);
732 gen_goto_tb(dc, 0, pc2, pc1);
735 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
738 static inline void gen_branch(DisasContext *dc, target_ulong pc,
741 gen_goto_tb(dc, 0, pc, npc);
744 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
748 l1 = gen_new_label();
749 l2 = gen_new_label();
750 gen_op_jz_T2_label(l1);
752 gen_movl_npc_im(npc1);
753 gen_op_jmp_label(l2);
756 gen_movl_npc_im(npc2);
760 /* call this function before using T2 as it may have been set for a jump */
761 static inline void flush_T2(DisasContext * dc)
763 if (dc->npc == JUMP_PC) {
764 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
765 dc->npc = DYNAMIC_PC;
769 static inline void save_npc(DisasContext * dc)
771 if (dc->npc == JUMP_PC) {
772 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
773 dc->npc = DYNAMIC_PC;
774 } else if (dc->npc != DYNAMIC_PC) {
775 gen_movl_npc_im(dc->npc);
779 static inline void save_state(DisasContext * dc)
785 static inline void gen_mov_pc_npc(DisasContext * dc)
787 if (dc->npc == JUMP_PC) {
788 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
791 } else if (dc->npc == DYNAMIC_PC) {
799 static GenOpFunc * const gen_cond[2][16] = {
819 #ifdef TARGET_SPARC64
840 static GenOpFunc * const gen_fcond[4][16] = {
859 #ifdef TARGET_SPARC64
862 gen_op_eval_fbne_fcc1,
863 gen_op_eval_fblg_fcc1,
864 gen_op_eval_fbul_fcc1,
865 gen_op_eval_fbl_fcc1,
866 gen_op_eval_fbug_fcc1,
867 gen_op_eval_fbg_fcc1,
868 gen_op_eval_fbu_fcc1,
870 gen_op_eval_fbe_fcc1,
871 gen_op_eval_fbue_fcc1,
872 gen_op_eval_fbge_fcc1,
873 gen_op_eval_fbuge_fcc1,
874 gen_op_eval_fble_fcc1,
875 gen_op_eval_fbule_fcc1,
876 gen_op_eval_fbo_fcc1,
880 gen_op_eval_fbne_fcc2,
881 gen_op_eval_fblg_fcc2,
882 gen_op_eval_fbul_fcc2,
883 gen_op_eval_fbl_fcc2,
884 gen_op_eval_fbug_fcc2,
885 gen_op_eval_fbg_fcc2,
886 gen_op_eval_fbu_fcc2,
888 gen_op_eval_fbe_fcc2,
889 gen_op_eval_fbue_fcc2,
890 gen_op_eval_fbge_fcc2,
891 gen_op_eval_fbuge_fcc2,
892 gen_op_eval_fble_fcc2,
893 gen_op_eval_fbule_fcc2,
894 gen_op_eval_fbo_fcc2,
898 gen_op_eval_fbne_fcc3,
899 gen_op_eval_fblg_fcc3,
900 gen_op_eval_fbul_fcc3,
901 gen_op_eval_fbl_fcc3,
902 gen_op_eval_fbug_fcc3,
903 gen_op_eval_fbg_fcc3,
904 gen_op_eval_fbu_fcc3,
906 gen_op_eval_fbe_fcc3,
907 gen_op_eval_fbue_fcc3,
908 gen_op_eval_fbge_fcc3,
909 gen_op_eval_fbuge_fcc3,
910 gen_op_eval_fble_fcc3,
911 gen_op_eval_fbule_fcc3,
912 gen_op_eval_fbo_fcc3,
919 #ifdef TARGET_SPARC64
920 static void gen_cond_reg(int cond)
946 /* XXX: potentially incorrect if dynamic npc */
947 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
949 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
950 target_ulong target = dc->pc + offset;
953 /* unconditional not taken */
955 dc->pc = dc->npc + 4;
956 dc->npc = dc->pc + 4;
959 dc->npc = dc->pc + 4;
961 } else if (cond == 0x8) {
962 /* unconditional taken */
965 dc->npc = dc->pc + 4;
972 gen_cond[cc][cond]();
974 gen_branch_a(dc, target, dc->npc);
978 dc->jump_pc[0] = target;
979 dc->jump_pc[1] = dc->npc + 4;
985 /* XXX: potentially incorrect if dynamic npc */
986 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
988 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
989 target_ulong target = dc->pc + offset;
992 /* unconditional not taken */
994 dc->pc = dc->npc + 4;
995 dc->npc = dc->pc + 4;
998 dc->npc = dc->pc + 4;
1000 } else if (cond == 0x8) {
1001 /* unconditional taken */
1004 dc->npc = dc->pc + 4;
1011 gen_fcond[cc][cond]();
1013 gen_branch_a(dc, target, dc->npc);
1017 dc->jump_pc[0] = target;
1018 dc->jump_pc[1] = dc->npc + 4;
1024 #ifdef TARGET_SPARC64
1025 /* XXX: potentially incorrect if dynamic npc */
1026 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1028 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1029 target_ulong target = dc->pc + offset;
1034 gen_branch_a(dc, target, dc->npc);
1038 dc->jump_pc[0] = target;
1039 dc->jump_pc[1] = dc->npc + 4;
1044 static GenOpFunc * const gen_fcmps[4] = {
1051 static GenOpFunc * const gen_fcmpd[4] = {
1058 static GenOpFunc * const gen_fcmpes[4] = {
1065 static GenOpFunc * const gen_fcmped[4] = {
1074 static int gen_trap_ifnofpu(DisasContext * dc)
1076 #if !defined(CONFIG_USER_ONLY)
1077 if (!dc->fpu_enabled) {
1079 gen_op_exception(TT_NFPU_INSN);
1087 /* before an instruction, dc->pc must be static */
1088 static void disas_sparc_insn(DisasContext * dc)
1090 unsigned int insn, opc, rs1, rs2, rd;
1092 insn = ldl_code(dc->pc);
1093 opc = GET_FIELD(insn, 0, 1);
1095 rd = GET_FIELD(insn, 2, 6);
1097 case 0: /* branches/sethi */
1099 unsigned int xop = GET_FIELD(insn, 7, 9);
1102 #ifdef TARGET_SPARC64
1103 case 0x1: /* V9 BPcc */
1107 target = GET_FIELD_SP(insn, 0, 18);
1108 target = sign_extend(target, 18);
1110 cc = GET_FIELD_SP(insn, 20, 21);
1112 do_branch(dc, target, insn, 0);
1114 do_branch(dc, target, insn, 1);
1119 case 0x3: /* V9 BPr */
1121 target = GET_FIELD_SP(insn, 0, 13) |
1122 (GET_FIELD_SP(insn, 20, 21) << 14);
1123 target = sign_extend(target, 16);
1125 rs1 = GET_FIELD(insn, 13, 17);
1126 gen_movl_reg_T0(rs1);
1127 do_branch_reg(dc, target, insn);
1130 case 0x5: /* V9 FBPcc */
1132 int cc = GET_FIELD_SP(insn, 20, 21);
1133 if (gen_trap_ifnofpu(dc))
1135 target = GET_FIELD_SP(insn, 0, 18);
1136 target = sign_extend(target, 19);
1138 do_fbranch(dc, target, insn, cc);
1142 case 0x7: /* CBN+x */
1147 case 0x2: /* BN+x */
1149 target = GET_FIELD(insn, 10, 31);
1150 target = sign_extend(target, 22);
1152 do_branch(dc, target, insn, 0);
1155 case 0x6: /* FBN+x */
1157 if (gen_trap_ifnofpu(dc))
1159 target = GET_FIELD(insn, 10, 31);
1160 target = sign_extend(target, 22);
1162 do_fbranch(dc, target, insn, 0);
1165 case 0x4: /* SETHI */
1170 uint32_t value = GET_FIELD(insn, 10, 31);
1171 gen_movl_imm_T0(value << 10);
1172 gen_movl_T0_reg(rd);
1177 case 0x0: /* UNIMPL */
1186 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1188 #ifdef TARGET_SPARC64
1189 if (dc->pc == (uint32_t)dc->pc) {
1190 gen_op_movl_T0_im(dc->pc);
1192 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1195 gen_op_movl_T0_im(dc->pc);
1197 gen_movl_T0_reg(15);
1203 case 2: /* FPU & Logical Operations */
1205 unsigned int xop = GET_FIELD(insn, 7, 12);
1206 if (xop == 0x3a) { /* generate trap */
1209 rs1 = GET_FIELD(insn, 13, 17);
1210 gen_movl_reg_T0(rs1);
1212 rs2 = GET_FIELD(insn, 25, 31);
1216 gen_movl_simm_T1(rs2);
1222 rs2 = GET_FIELD(insn, 27, 31);
1226 gen_movl_reg_T1(rs2);
1232 cond = GET_FIELD(insn, 3, 6);
1236 } else if (cond != 0) {
1237 #ifdef TARGET_SPARC64
1239 int cc = GET_FIELD_SP(insn, 11, 12);
1243 gen_cond[0][cond]();
1245 gen_cond[1][cond]();
1251 gen_cond[0][cond]();
1260 } else if (xop == 0x28) {
1261 rs1 = GET_FIELD(insn, 13, 17);
1264 #ifndef TARGET_SPARC64
1265 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1266 manual, rdy on the microSPARC
1268 case 0x0f: /* stbar in the SPARCv8 manual,
1269 rdy on the microSPARC II */
1270 case 0x10 ... 0x1f: /* implementation-dependent in the
1271 SPARCv8 manual, rdy on the
1274 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1275 gen_movl_T0_reg(rd);
1277 #ifdef TARGET_SPARC64
1278 case 0x2: /* V9 rdccr */
1280 gen_movl_T0_reg(rd);
1282 case 0x3: /* V9 rdasi */
1283 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1284 gen_movl_T0_reg(rd);
1286 case 0x4: /* V9 rdtick */
1288 gen_movl_T0_reg(rd);
1290 case 0x5: /* V9 rdpc */
1291 if (dc->pc == (uint32_t)dc->pc) {
1292 gen_op_movl_T0_im(dc->pc);
1294 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1296 gen_movl_T0_reg(rd);
1298 case 0x6: /* V9 rdfprs */
1299 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1300 gen_movl_T0_reg(rd);
1302 case 0xf: /* V9 membar */
1303 break; /* no effect */
1304 case 0x13: /* Graphics Status */
1305 if (gen_trap_ifnofpu(dc))
1307 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1308 gen_movl_T0_reg(rd);
1310 case 0x17: /* Tick compare */
1311 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1312 gen_movl_T0_reg(rd);
1314 case 0x18: /* System tick */
1316 gen_movl_T0_reg(rd);
1318 case 0x19: /* System tick compare */
1319 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1320 gen_movl_T0_reg(rd);
1322 case 0x10: /* Performance Control */
1323 case 0x11: /* Performance Instrumentation Counter */
1324 case 0x12: /* Dispatch Control */
1325 case 0x14: /* Softint set, WO */
1326 case 0x15: /* Softint clear, WO */
1327 case 0x16: /* Softint write */
1332 #if !defined(CONFIG_USER_ONLY)
1333 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1334 #ifndef TARGET_SPARC64
1335 if (!supervisor(dc))
1339 if (!hypervisor(dc))
1341 rs1 = GET_FIELD(insn, 13, 17);
1344 // gen_op_rdhpstate();
1347 // gen_op_rdhtstate();
1350 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1353 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1356 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1358 case 31: // hstick_cmpr
1359 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1365 gen_movl_T0_reg(rd);
1367 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1368 if (!supervisor(dc))
1370 #ifdef TARGET_SPARC64
1371 rs1 = GET_FIELD(insn, 13, 17);
1389 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1395 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1398 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1404 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1406 case 11: // canrestore
1407 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1409 case 12: // cleanwin
1410 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1412 case 13: // otherwin
1413 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1416 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1418 case 16: // UA2005 gl
1419 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1421 case 26: // UA2005 strand status
1422 if (!hypervisor(dc))
1424 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1427 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1434 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1436 gen_movl_T0_reg(rd);
1438 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1439 #ifdef TARGET_SPARC64
1442 if (!supervisor(dc))
1444 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1445 gen_movl_T0_reg(rd);
1449 } else if (xop == 0x34) { /* FPU Operations */
1450 if (gen_trap_ifnofpu(dc))
1452 gen_op_clear_ieee_excp_and_FTT();
1453 rs1 = GET_FIELD(insn, 13, 17);
1454 rs2 = GET_FIELD(insn, 27, 31);
1455 xop = GET_FIELD(insn, 18, 26);
1457 case 0x1: /* fmovs */
1458 gen_op_load_fpr_FT0(rs2);
1459 gen_op_store_FT0_fpr(rd);
1461 case 0x5: /* fnegs */
1462 gen_op_load_fpr_FT1(rs2);
1464 gen_op_store_FT0_fpr(rd);
1466 case 0x9: /* fabss */
1467 gen_op_load_fpr_FT1(rs2);
1469 gen_op_store_FT0_fpr(rd);
1471 case 0x29: /* fsqrts */
1472 gen_op_load_fpr_FT1(rs2);
1474 gen_op_store_FT0_fpr(rd);
1476 case 0x2a: /* fsqrtd */
1477 gen_op_load_fpr_DT1(DFPREG(rs2));
1479 gen_op_store_DT0_fpr(DFPREG(rd));
1481 case 0x2b: /* fsqrtq */
1484 gen_op_load_fpr_FT0(rs1);
1485 gen_op_load_fpr_FT1(rs2);
1487 gen_op_store_FT0_fpr(rd);
1490 gen_op_load_fpr_DT0(DFPREG(rs1));
1491 gen_op_load_fpr_DT1(DFPREG(rs2));
1493 gen_op_store_DT0_fpr(DFPREG(rd));
1495 case 0x43: /* faddq */
1498 gen_op_load_fpr_FT0(rs1);
1499 gen_op_load_fpr_FT1(rs2);
1501 gen_op_store_FT0_fpr(rd);
1504 gen_op_load_fpr_DT0(DFPREG(rs1));
1505 gen_op_load_fpr_DT1(DFPREG(rs2));
1507 gen_op_store_DT0_fpr(DFPREG(rd));
1509 case 0x47: /* fsubq */
1512 gen_op_load_fpr_FT0(rs1);
1513 gen_op_load_fpr_FT1(rs2);
1515 gen_op_store_FT0_fpr(rd);
1518 gen_op_load_fpr_DT0(DFPREG(rs1));
1519 gen_op_load_fpr_DT1(DFPREG(rs2));
1521 gen_op_store_DT0_fpr(rd);
1523 case 0x4b: /* fmulq */
1526 gen_op_load_fpr_FT0(rs1);
1527 gen_op_load_fpr_FT1(rs2);
1529 gen_op_store_FT0_fpr(rd);
1532 gen_op_load_fpr_DT0(DFPREG(rs1));
1533 gen_op_load_fpr_DT1(DFPREG(rs2));
1535 gen_op_store_DT0_fpr(DFPREG(rd));
1537 case 0x4f: /* fdivq */
1540 gen_op_load_fpr_FT0(rs1);
1541 gen_op_load_fpr_FT1(rs2);
1543 gen_op_store_DT0_fpr(DFPREG(rd));
1545 case 0x6e: /* fdmulq */
1548 gen_op_load_fpr_FT1(rs2);
1550 gen_op_store_FT0_fpr(rd);
1553 gen_op_load_fpr_DT1(DFPREG(rs2));
1555 gen_op_store_FT0_fpr(rd);
1557 case 0xc7: /* fqtos */
1560 gen_op_load_fpr_FT1(rs2);
1562 gen_op_store_DT0_fpr(DFPREG(rd));
1565 gen_op_load_fpr_FT1(rs2);
1567 gen_op_store_DT0_fpr(DFPREG(rd));
1569 case 0xcb: /* fqtod */
1571 case 0xcc: /* fitoq */
1573 case 0xcd: /* fstoq */
1575 case 0xce: /* fdtoq */
1578 gen_op_load_fpr_FT1(rs2);
1580 gen_op_store_FT0_fpr(rd);
1583 gen_op_load_fpr_DT1(rs2);
1585 gen_op_store_FT0_fpr(rd);
1587 case 0xd3: /* fqtoi */
1589 #ifdef TARGET_SPARC64
1590 case 0x2: /* V9 fmovd */
1591 gen_op_load_fpr_DT0(DFPREG(rs2));
1592 gen_op_store_DT0_fpr(DFPREG(rd));
1594 case 0x6: /* V9 fnegd */
1595 gen_op_load_fpr_DT1(DFPREG(rs2));
1597 gen_op_store_DT0_fpr(DFPREG(rd));
1599 case 0xa: /* V9 fabsd */
1600 gen_op_load_fpr_DT1(DFPREG(rs2));
1602 gen_op_store_DT0_fpr(DFPREG(rd));
1604 case 0x81: /* V9 fstox */
1605 gen_op_load_fpr_FT1(rs2);
1607 gen_op_store_DT0_fpr(DFPREG(rd));
1609 case 0x82: /* V9 fdtox */
1610 gen_op_load_fpr_DT1(DFPREG(rs2));
1612 gen_op_store_DT0_fpr(DFPREG(rd));
1614 case 0x84: /* V9 fxtos */
1615 gen_op_load_fpr_DT1(DFPREG(rs2));
1617 gen_op_store_FT0_fpr(rd);
1619 case 0x88: /* V9 fxtod */
1620 gen_op_load_fpr_DT1(DFPREG(rs2));
1622 gen_op_store_DT0_fpr(DFPREG(rd));
1624 case 0x3: /* V9 fmovq */
1625 case 0x7: /* V9 fnegq */
1626 case 0xb: /* V9 fabsq */
1627 case 0x83: /* V9 fqtox */
1628 case 0x8c: /* V9 fxtoq */
1634 } else if (xop == 0x35) { /* FPU Operations */
1635 #ifdef TARGET_SPARC64
1638 if (gen_trap_ifnofpu(dc))
1640 gen_op_clear_ieee_excp_and_FTT();
1641 rs1 = GET_FIELD(insn, 13, 17);
1642 rs2 = GET_FIELD(insn, 27, 31);
1643 xop = GET_FIELD(insn, 18, 26);
1644 #ifdef TARGET_SPARC64
1645 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1646 cond = GET_FIELD_SP(insn, 14, 17);
1647 gen_op_load_fpr_FT0(rd);
1648 gen_op_load_fpr_FT1(rs2);
1649 rs1 = GET_FIELD(insn, 13, 17);
1650 gen_movl_reg_T0(rs1);
1654 gen_op_store_FT0_fpr(rd);
1656 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1657 cond = GET_FIELD_SP(insn, 14, 17);
1658 gen_op_load_fpr_DT0(rd);
1659 gen_op_load_fpr_DT1(rs2);
1661 rs1 = GET_FIELD(insn, 13, 17);
1662 gen_movl_reg_T0(rs1);
1665 gen_op_store_DT0_fpr(rd);
1667 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1672 #ifdef TARGET_SPARC64
1673 case 0x001: /* V9 fmovscc %fcc0 */
1674 cond = GET_FIELD_SP(insn, 14, 17);
1675 gen_op_load_fpr_FT0(rd);
1676 gen_op_load_fpr_FT1(rs2);
1678 gen_fcond[0][cond]();
1680 gen_op_store_FT0_fpr(rd);
1682 case 0x002: /* V9 fmovdcc %fcc0 */
1683 cond = GET_FIELD_SP(insn, 14, 17);
1684 gen_op_load_fpr_DT0(rd);
1685 gen_op_load_fpr_DT1(rs2);
1687 gen_fcond[0][cond]();
1689 gen_op_store_DT0_fpr(rd);
1691 case 0x003: /* V9 fmovqcc %fcc0 */
1693 case 0x041: /* V9 fmovscc %fcc1 */
1694 cond = GET_FIELD_SP(insn, 14, 17);
1695 gen_op_load_fpr_FT0(rd);
1696 gen_op_load_fpr_FT1(rs2);
1698 gen_fcond[1][cond]();
1700 gen_op_store_FT0_fpr(rd);
1702 case 0x042: /* V9 fmovdcc %fcc1 */
1703 cond = GET_FIELD_SP(insn, 14, 17);
1704 gen_op_load_fpr_DT0(rd);
1705 gen_op_load_fpr_DT1(rs2);
1707 gen_fcond[1][cond]();
1709 gen_op_store_DT0_fpr(rd);
1711 case 0x043: /* V9 fmovqcc %fcc1 */
1713 case 0x081: /* V9 fmovscc %fcc2 */
1714 cond = GET_FIELD_SP(insn, 14, 17);
1715 gen_op_load_fpr_FT0(rd);
1716 gen_op_load_fpr_FT1(rs2);
1718 gen_fcond[2][cond]();
1720 gen_op_store_FT0_fpr(rd);
1722 case 0x082: /* V9 fmovdcc %fcc2 */
1723 cond = GET_FIELD_SP(insn, 14, 17);
1724 gen_op_load_fpr_DT0(rd);
1725 gen_op_load_fpr_DT1(rs2);
1727 gen_fcond[2][cond]();
1729 gen_op_store_DT0_fpr(rd);
1731 case 0x083: /* V9 fmovqcc %fcc2 */
1733 case 0x0c1: /* V9 fmovscc %fcc3 */
1734 cond = GET_FIELD_SP(insn, 14, 17);
1735 gen_op_load_fpr_FT0(rd);
1736 gen_op_load_fpr_FT1(rs2);
1738 gen_fcond[3][cond]();
1740 gen_op_store_FT0_fpr(rd);
1742 case 0x0c2: /* V9 fmovdcc %fcc3 */
1743 cond = GET_FIELD_SP(insn, 14, 17);
1744 gen_op_load_fpr_DT0(rd);
1745 gen_op_load_fpr_DT1(rs2);
1747 gen_fcond[3][cond]();
1749 gen_op_store_DT0_fpr(rd);
1751 case 0x0c3: /* V9 fmovqcc %fcc3 */
1753 case 0x101: /* V9 fmovscc %icc */
1754 cond = GET_FIELD_SP(insn, 14, 17);
1755 gen_op_load_fpr_FT0(rd);
1756 gen_op_load_fpr_FT1(rs2);
1758 gen_cond[0][cond]();
1760 gen_op_store_FT0_fpr(rd);
1762 case 0x102: /* V9 fmovdcc %icc */
1763 cond = GET_FIELD_SP(insn, 14, 17);
1764 gen_op_load_fpr_DT0(rd);
1765 gen_op_load_fpr_DT1(rs2);
1767 gen_cond[0][cond]();
1769 gen_op_store_DT0_fpr(rd);
1771 case 0x103: /* V9 fmovqcc %icc */
1773 case 0x181: /* V9 fmovscc %xcc */
1774 cond = GET_FIELD_SP(insn, 14, 17);
1775 gen_op_load_fpr_FT0(rd);
1776 gen_op_load_fpr_FT1(rs2);
1778 gen_cond[1][cond]();
1780 gen_op_store_FT0_fpr(rd);
1782 case 0x182: /* V9 fmovdcc %xcc */
1783 cond = GET_FIELD_SP(insn, 14, 17);
1784 gen_op_load_fpr_DT0(rd);
1785 gen_op_load_fpr_DT1(rs2);
1787 gen_cond[1][cond]();
1789 gen_op_store_DT0_fpr(rd);
1791 case 0x183: /* V9 fmovqcc %xcc */
1794 case 0x51: /* V9 %fcc */
1795 gen_op_load_fpr_FT0(rs1);
1796 gen_op_load_fpr_FT1(rs2);
1797 #ifdef TARGET_SPARC64
1798 gen_fcmps[rd & 3]();
1803 case 0x52: /* V9 %fcc */
1804 gen_op_load_fpr_DT0(DFPREG(rs1));
1805 gen_op_load_fpr_DT1(DFPREG(rs2));
1806 #ifdef TARGET_SPARC64
1807 gen_fcmpd[rd & 3]();
1812 case 0x53: /* fcmpq */
1814 case 0x55: /* fcmpes, V9 %fcc */
1815 gen_op_load_fpr_FT0(rs1);
1816 gen_op_load_fpr_FT1(rs2);
1817 #ifdef TARGET_SPARC64
1818 gen_fcmpes[rd & 3]();
1823 case 0x56: /* fcmped, V9 %fcc */
1824 gen_op_load_fpr_DT0(DFPREG(rs1));
1825 gen_op_load_fpr_DT1(DFPREG(rs2));
1826 #ifdef TARGET_SPARC64
1827 gen_fcmped[rd & 3]();
1832 case 0x57: /* fcmpeq */
1838 } else if (xop == 0x2) {
1841 rs1 = GET_FIELD(insn, 13, 17);
1843 // or %g0, x, y -> mov T1, x; mov y, T1
1844 if (IS_IMM) { /* immediate */
1845 rs2 = GET_FIELDs(insn, 19, 31);
1846 gen_movl_simm_T1(rs2);
1847 } else { /* register */
1848 rs2 = GET_FIELD(insn, 27, 31);
1849 gen_movl_reg_T1(rs2);
1851 gen_movl_T1_reg(rd);
1853 gen_movl_reg_T0(rs1);
1854 if (IS_IMM) { /* immediate */
1855 // or x, #0, y -> mov T1, x; mov y, T1
1856 rs2 = GET_FIELDs(insn, 19, 31);
1858 gen_movl_simm_T1(rs2);
1861 } else { /* register */
1862 // or x, %g0, y -> mov T1, x; mov y, T1
1863 rs2 = GET_FIELD(insn, 27, 31);
1865 gen_movl_reg_T1(rs2);
1869 gen_movl_T0_reg(rd);
1872 #ifdef TARGET_SPARC64
1873 } else if (xop == 0x25) { /* sll, V9 sllx */
1874 rs1 = GET_FIELD(insn, 13, 17);
1875 gen_movl_reg_T0(rs1);
1876 if (IS_IMM) { /* immediate */
1877 rs2 = GET_FIELDs(insn, 20, 31);
1878 gen_movl_simm_T1(rs2);
1879 } else { /* register */
1880 rs2 = GET_FIELD(insn, 27, 31);
1881 gen_movl_reg_T1(rs2);
1883 if (insn & (1 << 12))
1887 gen_movl_T0_reg(rd);
1888 } else if (xop == 0x26) { /* srl, V9 srlx */
1889 rs1 = GET_FIELD(insn, 13, 17);
1890 gen_movl_reg_T0(rs1);
1891 if (IS_IMM) { /* immediate */
1892 rs2 = GET_FIELDs(insn, 20, 31);
1893 gen_movl_simm_T1(rs2);
1894 } else { /* register */
1895 rs2 = GET_FIELD(insn, 27, 31);
1896 gen_movl_reg_T1(rs2);
1898 if (insn & (1 << 12))
1902 gen_movl_T0_reg(rd);
1903 } else if (xop == 0x27) { /* sra, V9 srax */
1904 rs1 = GET_FIELD(insn, 13, 17);
1905 gen_movl_reg_T0(rs1);
1906 if (IS_IMM) { /* immediate */
1907 rs2 = GET_FIELDs(insn, 20, 31);
1908 gen_movl_simm_T1(rs2);
1909 } else { /* register */
1910 rs2 = GET_FIELD(insn, 27, 31);
1911 gen_movl_reg_T1(rs2);
1913 if (insn & (1 << 12))
1917 gen_movl_T0_reg(rd);
1919 } else if (xop < 0x36) {
1920 rs1 = GET_FIELD(insn, 13, 17);
1921 gen_movl_reg_T0(rs1);
1922 if (IS_IMM) { /* immediate */
1923 rs2 = GET_FIELDs(insn, 19, 31);
1924 gen_movl_simm_T1(rs2);
1925 } else { /* register */
1926 rs2 = GET_FIELD(insn, 27, 31);
1927 gen_movl_reg_T1(rs2);
1930 switch (xop & ~0x10) {
1933 gen_op_add_T1_T0_cc();
1940 gen_op_logic_T0_cc();
1945 gen_op_logic_T0_cc();
1950 gen_op_logic_T0_cc();
1954 gen_op_sub_T1_T0_cc();
1959 gen_op_andn_T1_T0();
1961 gen_op_logic_T0_cc();
1966 gen_op_logic_T0_cc();
1969 gen_op_xnor_T1_T0();
1971 gen_op_logic_T0_cc();
1975 gen_op_addx_T1_T0_cc();
1977 gen_op_addx_T1_T0();
1979 #ifdef TARGET_SPARC64
1980 case 0x9: /* V9 mulx */
1981 gen_op_mulx_T1_T0();
1985 gen_op_umul_T1_T0();
1987 gen_op_logic_T0_cc();
1990 gen_op_smul_T1_T0();
1992 gen_op_logic_T0_cc();
1996 gen_op_subx_T1_T0_cc();
1998 gen_op_subx_T1_T0();
2000 #ifdef TARGET_SPARC64
2001 case 0xd: /* V9 udivx */
2002 gen_op_udivx_T1_T0();
2006 gen_op_udiv_T1_T0();
2011 gen_op_sdiv_T1_T0();
2018 gen_movl_T0_reg(rd);
2021 case 0x20: /* taddcc */
2022 gen_op_tadd_T1_T0_cc();
2023 gen_movl_T0_reg(rd);
2025 case 0x21: /* tsubcc */
2026 gen_op_tsub_T1_T0_cc();
2027 gen_movl_T0_reg(rd);
2029 case 0x22: /* taddcctv */
2031 gen_op_tadd_T1_T0_ccTV();
2032 gen_movl_T0_reg(rd);
2034 case 0x23: /* tsubcctv */
2036 gen_op_tsub_T1_T0_ccTV();
2037 gen_movl_T0_reg(rd);
2039 case 0x24: /* mulscc */
2040 gen_op_mulscc_T1_T0();
2041 gen_movl_T0_reg(rd);
2043 #ifndef TARGET_SPARC64
2044 case 0x25: /* sll */
2046 gen_movl_T0_reg(rd);
2048 case 0x26: /* srl */
2050 gen_movl_T0_reg(rd);
2052 case 0x27: /* sra */
2054 gen_movl_T0_reg(rd);
2062 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
2064 #ifndef TARGET_SPARC64
2065 case 0x01 ... 0x0f: /* undefined in the
2069 case 0x10 ... 0x1f: /* implementation-dependent
2075 case 0x2: /* V9 wrccr */
2079 case 0x3: /* V9 wrasi */
2081 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2083 case 0x6: /* V9 wrfprs */
2085 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
2092 case 0xf: /* V9 sir, nop if user */
2093 #if !defined(CONFIG_USER_ONLY)
2098 case 0x13: /* Graphics Status */
2099 if (gen_trap_ifnofpu(dc))
2102 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2104 case 0x17: /* Tick compare */
2105 #if !defined(CONFIG_USER_ONLY)
2106 if (!supervisor(dc))
2110 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2111 gen_op_wrtick_cmpr();
2113 case 0x18: /* System tick */
2114 #if !defined(CONFIG_USER_ONLY)
2115 if (!supervisor(dc))
2121 case 0x19: /* System tick compare */
2122 #if !defined(CONFIG_USER_ONLY)
2123 if (!supervisor(dc))
2127 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2128 gen_op_wrstick_cmpr();
2131 case 0x10: /* Performance Control */
2132 case 0x11: /* Performance Instrumentation Counter */
2133 case 0x12: /* Dispatch Control */
2134 case 0x14: /* Softint set */
2135 case 0x15: /* Softint clear */
2136 case 0x16: /* Softint write */
2143 #if !defined(CONFIG_USER_ONLY)
2144 case 0x31: /* wrpsr, V9 saved, restored */
2146 if (!supervisor(dc))
2148 #ifdef TARGET_SPARC64
2156 case 2: /* UA2005 allclean */
2157 case 3: /* UA2005 otherw */
2158 case 4: /* UA2005 normalw */
2159 case 5: /* UA2005 invalw */
2175 case 0x32: /* wrwim, V9 wrpr */
2177 if (!supervisor(dc))
2180 #ifdef TARGET_SPARC64
2198 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2209 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2212 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2218 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2220 case 11: // canrestore
2221 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2223 case 12: // cleanwin
2224 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2226 case 13: // otherwin
2227 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2230 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2232 case 16: // UA2005 gl
2233 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2235 case 26: // UA2005 strand status
2236 if (!hypervisor(dc))
2238 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2248 case 0x33: /* wrtbr, UA2005 wrhpr */
2250 #ifndef TARGET_SPARC64
2251 if (!supervisor(dc))
2254 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2256 if (!hypervisor(dc))
2261 // XXX gen_op_wrhpstate();
2269 // XXX gen_op_wrhtstate();
2272 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2275 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2277 case 31: // hstick_cmpr
2278 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2279 gen_op_wrhstick_cmpr();
2281 case 6: // hver readonly
2289 #ifdef TARGET_SPARC64
2290 case 0x2c: /* V9 movcc */
2292 int cc = GET_FIELD_SP(insn, 11, 12);
2293 int cond = GET_FIELD_SP(insn, 14, 17);
2294 if (IS_IMM) { /* immediate */
2295 rs2 = GET_FIELD_SPs(insn, 0, 10);
2296 gen_movl_simm_T1(rs2);
2299 rs2 = GET_FIELD_SP(insn, 0, 4);
2300 gen_movl_reg_T1(rs2);
2302 gen_movl_reg_T0(rd);
2304 if (insn & (1 << 18)) {
2306 gen_cond[0][cond]();
2308 gen_cond[1][cond]();
2312 gen_fcond[cc][cond]();
2315 gen_movl_T0_reg(rd);
2318 case 0x2d: /* V9 sdivx */
2319 gen_op_sdivx_T1_T0();
2320 gen_movl_T0_reg(rd);
2322 case 0x2e: /* V9 popc */
2324 if (IS_IMM) { /* immediate */
2325 rs2 = GET_FIELD_SPs(insn, 0, 12);
2326 gen_movl_simm_T1(rs2);
2327 // XXX optimize: popc(constant)
2330 rs2 = GET_FIELD_SP(insn, 0, 4);
2331 gen_movl_reg_T1(rs2);
2334 gen_movl_T0_reg(rd);
2336 case 0x2f: /* V9 movr */
2338 int cond = GET_FIELD_SP(insn, 10, 12);
2339 rs1 = GET_FIELD(insn, 13, 17);
2341 gen_movl_reg_T0(rs1);
2343 if (IS_IMM) { /* immediate */
2344 rs2 = GET_FIELD_SPs(insn, 0, 9);
2345 gen_movl_simm_T1(rs2);
2348 rs2 = GET_FIELD_SP(insn, 0, 4);
2349 gen_movl_reg_T1(rs2);
2351 gen_movl_reg_T0(rd);
2353 gen_movl_T0_reg(rd);
2361 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2362 #ifdef TARGET_SPARC64
2363 int opf = GET_FIELD_SP(insn, 5, 13);
2364 rs1 = GET_FIELD(insn, 13, 17);
2365 rs2 = GET_FIELD(insn, 27, 31);
2366 if (gen_trap_ifnofpu(dc))
2370 case 0x000: /* VIS I edge8cc */
2371 case 0x001: /* VIS II edge8n */
2372 case 0x002: /* VIS I edge8lcc */
2373 case 0x003: /* VIS II edge8ln */
2374 case 0x004: /* VIS I edge16cc */
2375 case 0x005: /* VIS II edge16n */
2376 case 0x006: /* VIS I edge16lcc */
2377 case 0x007: /* VIS II edge16ln */
2378 case 0x008: /* VIS I edge32cc */
2379 case 0x009: /* VIS II edge32n */
2380 case 0x00a: /* VIS I edge32lcc */
2381 case 0x00b: /* VIS II edge32ln */
2384 case 0x010: /* VIS I array8 */
2385 gen_movl_reg_T0(rs1);
2386 gen_movl_reg_T1(rs2);
2388 gen_movl_T0_reg(rd);
2390 case 0x012: /* VIS I array16 */
2391 gen_movl_reg_T0(rs1);
2392 gen_movl_reg_T1(rs2);
2394 gen_movl_T0_reg(rd);
2396 case 0x014: /* VIS I array32 */
2397 gen_movl_reg_T0(rs1);
2398 gen_movl_reg_T1(rs2);
2400 gen_movl_T0_reg(rd);
2402 case 0x018: /* VIS I alignaddr */
2403 gen_movl_reg_T0(rs1);
2404 gen_movl_reg_T1(rs2);
2406 gen_movl_T0_reg(rd);
2408 case 0x019: /* VIS II bmask */
2409 case 0x01a: /* VIS I alignaddrl */
2412 case 0x020: /* VIS I fcmple16 */
2413 gen_op_load_fpr_DT0(rs1);
2414 gen_op_load_fpr_DT1(rs2);
2416 gen_op_store_DT0_fpr(rd);
2418 case 0x022: /* VIS I fcmpne16 */
2419 gen_op_load_fpr_DT0(rs1);
2420 gen_op_load_fpr_DT1(rs2);
2422 gen_op_store_DT0_fpr(rd);
2424 case 0x024: /* VIS I fcmple32 */
2425 gen_op_load_fpr_DT0(rs1);
2426 gen_op_load_fpr_DT1(rs2);
2428 gen_op_store_DT0_fpr(rd);
2430 case 0x026: /* VIS I fcmpne32 */
2431 gen_op_load_fpr_DT0(rs1);
2432 gen_op_load_fpr_DT1(rs2);
2434 gen_op_store_DT0_fpr(rd);
2436 case 0x028: /* VIS I fcmpgt16 */
2437 gen_op_load_fpr_DT0(rs1);
2438 gen_op_load_fpr_DT1(rs2);
2440 gen_op_store_DT0_fpr(rd);
2442 case 0x02a: /* VIS I fcmpeq16 */
2443 gen_op_load_fpr_DT0(rs1);
2444 gen_op_load_fpr_DT1(rs2);
2446 gen_op_store_DT0_fpr(rd);
2448 case 0x02c: /* VIS I fcmpgt32 */
2449 gen_op_load_fpr_DT0(rs1);
2450 gen_op_load_fpr_DT1(rs2);
2452 gen_op_store_DT0_fpr(rd);
2454 case 0x02e: /* VIS I fcmpeq32 */
2455 gen_op_load_fpr_DT0(rs1);
2456 gen_op_load_fpr_DT1(rs2);
2458 gen_op_store_DT0_fpr(rd);
2460 case 0x031: /* VIS I fmul8x16 */
2461 gen_op_load_fpr_DT0(rs1);
2462 gen_op_load_fpr_DT1(rs2);
2464 gen_op_store_DT0_fpr(rd);
2466 case 0x033: /* VIS I fmul8x16au */
2467 gen_op_load_fpr_DT0(rs1);
2468 gen_op_load_fpr_DT1(rs2);
2469 gen_op_fmul8x16au();
2470 gen_op_store_DT0_fpr(rd);
2472 case 0x035: /* VIS I fmul8x16al */
2473 gen_op_load_fpr_DT0(rs1);
2474 gen_op_load_fpr_DT1(rs2);
2475 gen_op_fmul8x16al();
2476 gen_op_store_DT0_fpr(rd);
2478 case 0x036: /* VIS I fmul8sux16 */
2479 gen_op_load_fpr_DT0(rs1);
2480 gen_op_load_fpr_DT1(rs2);
2481 gen_op_fmul8sux16();
2482 gen_op_store_DT0_fpr(rd);
2484 case 0x037: /* VIS I fmul8ulx16 */
2485 gen_op_load_fpr_DT0(rs1);
2486 gen_op_load_fpr_DT1(rs2);
2487 gen_op_fmul8ulx16();
2488 gen_op_store_DT0_fpr(rd);
2490 case 0x038: /* VIS I fmuld8sux16 */
2491 gen_op_load_fpr_DT0(rs1);
2492 gen_op_load_fpr_DT1(rs2);
2493 gen_op_fmuld8sux16();
2494 gen_op_store_DT0_fpr(rd);
2496 case 0x039: /* VIS I fmuld8ulx16 */
2497 gen_op_load_fpr_DT0(rs1);
2498 gen_op_load_fpr_DT1(rs2);
2499 gen_op_fmuld8ulx16();
2500 gen_op_store_DT0_fpr(rd);
2502 case 0x03a: /* VIS I fpack32 */
2503 case 0x03b: /* VIS I fpack16 */
2504 case 0x03d: /* VIS I fpackfix */
2505 case 0x03e: /* VIS I pdist */
2508 case 0x048: /* VIS I faligndata */
2509 gen_op_load_fpr_DT0(rs1);
2510 gen_op_load_fpr_DT1(rs2);
2511 gen_op_faligndata();
2512 gen_op_store_DT0_fpr(rd);
2514 case 0x04b: /* VIS I fpmerge */
2515 gen_op_load_fpr_DT0(rs1);
2516 gen_op_load_fpr_DT1(rs2);
2518 gen_op_store_DT0_fpr(rd);
2520 case 0x04c: /* VIS II bshuffle */
2523 case 0x04d: /* VIS I fexpand */
2524 gen_op_load_fpr_DT0(rs1);
2525 gen_op_load_fpr_DT1(rs2);
2527 gen_op_store_DT0_fpr(rd);
2529 case 0x050: /* VIS I fpadd16 */
2530 gen_op_load_fpr_DT0(rs1);
2531 gen_op_load_fpr_DT1(rs2);
2533 gen_op_store_DT0_fpr(rd);
2535 case 0x051: /* VIS I fpadd16s */
2536 gen_op_load_fpr_FT0(rs1);
2537 gen_op_load_fpr_FT1(rs2);
2539 gen_op_store_FT0_fpr(rd);
2541 case 0x052: /* VIS I fpadd32 */
2542 gen_op_load_fpr_DT0(rs1);
2543 gen_op_load_fpr_DT1(rs2);
2545 gen_op_store_DT0_fpr(rd);
2547 case 0x053: /* VIS I fpadd32s */
2548 gen_op_load_fpr_FT0(rs1);
2549 gen_op_load_fpr_FT1(rs2);
2551 gen_op_store_FT0_fpr(rd);
2553 case 0x054: /* VIS I fpsub16 */
2554 gen_op_load_fpr_DT0(rs1);
2555 gen_op_load_fpr_DT1(rs2);
2557 gen_op_store_DT0_fpr(rd);
2559 case 0x055: /* VIS I fpsub16s */
2560 gen_op_load_fpr_FT0(rs1);
2561 gen_op_load_fpr_FT1(rs2);
2563 gen_op_store_FT0_fpr(rd);
2565 case 0x056: /* VIS I fpsub32 */
2566 gen_op_load_fpr_DT0(rs1);
2567 gen_op_load_fpr_DT1(rs2);
2569 gen_op_store_DT0_fpr(rd);
2571 case 0x057: /* VIS I fpsub32s */
2572 gen_op_load_fpr_FT0(rs1);
2573 gen_op_load_fpr_FT1(rs2);
2575 gen_op_store_FT0_fpr(rd);
2577 case 0x060: /* VIS I fzero */
2578 gen_op_movl_DT0_0();
2579 gen_op_store_DT0_fpr(rd);
2581 case 0x061: /* VIS I fzeros */
2582 gen_op_movl_FT0_0();
2583 gen_op_store_FT0_fpr(rd);
2585 case 0x062: /* VIS I fnor */
2586 gen_op_load_fpr_DT0(rs1);
2587 gen_op_load_fpr_DT1(rs2);
2589 gen_op_store_DT0_fpr(rd);
2591 case 0x063: /* VIS I fnors */
2592 gen_op_load_fpr_FT0(rs1);
2593 gen_op_load_fpr_FT1(rs2);
2595 gen_op_store_FT0_fpr(rd);
2597 case 0x064: /* VIS I fandnot2 */
2598 gen_op_load_fpr_DT1(rs1);
2599 gen_op_load_fpr_DT0(rs2);
2601 gen_op_store_DT0_fpr(rd);
2603 case 0x065: /* VIS I fandnot2s */
2604 gen_op_load_fpr_FT1(rs1);
2605 gen_op_load_fpr_FT0(rs2);
2607 gen_op_store_FT0_fpr(rd);
2609 case 0x066: /* VIS I fnot2 */
2610 gen_op_load_fpr_DT1(rs2);
2612 gen_op_store_DT0_fpr(rd);
2614 case 0x067: /* VIS I fnot2s */
2615 gen_op_load_fpr_FT1(rs2);
2617 gen_op_store_FT0_fpr(rd);
2619 case 0x068: /* VIS I fandnot1 */
2620 gen_op_load_fpr_DT0(rs1);
2621 gen_op_load_fpr_DT1(rs2);
2623 gen_op_store_DT0_fpr(rd);
2625 case 0x069: /* VIS I fandnot1s */
2626 gen_op_load_fpr_FT0(rs1);
2627 gen_op_load_fpr_FT1(rs2);
2629 gen_op_store_FT0_fpr(rd);
2631 case 0x06a: /* VIS I fnot1 */
2632 gen_op_load_fpr_DT1(rs1);
2634 gen_op_store_DT0_fpr(rd);
2636 case 0x06b: /* VIS I fnot1s */
2637 gen_op_load_fpr_FT1(rs1);
2639 gen_op_store_FT0_fpr(rd);
2641 case 0x06c: /* VIS I fxor */
2642 gen_op_load_fpr_DT0(rs1);
2643 gen_op_load_fpr_DT1(rs2);
2645 gen_op_store_DT0_fpr(rd);
2647 case 0x06d: /* VIS I fxors */
2648 gen_op_load_fpr_FT0(rs1);
2649 gen_op_load_fpr_FT1(rs2);
2651 gen_op_store_FT0_fpr(rd);
2653 case 0x06e: /* VIS I fnand */
2654 gen_op_load_fpr_DT0(rs1);
2655 gen_op_load_fpr_DT1(rs2);
2657 gen_op_store_DT0_fpr(rd);
2659 case 0x06f: /* VIS I fnands */
2660 gen_op_load_fpr_FT0(rs1);
2661 gen_op_load_fpr_FT1(rs2);
2663 gen_op_store_FT0_fpr(rd);
2665 case 0x070: /* VIS I fand */
2666 gen_op_load_fpr_DT0(rs1);
2667 gen_op_load_fpr_DT1(rs2);
2669 gen_op_store_DT0_fpr(rd);
2671 case 0x071: /* VIS I fands */
2672 gen_op_load_fpr_FT0(rs1);
2673 gen_op_load_fpr_FT1(rs2);
2675 gen_op_store_FT0_fpr(rd);
2677 case 0x072: /* VIS I fxnor */
2678 gen_op_load_fpr_DT0(rs1);
2679 gen_op_load_fpr_DT1(rs2);
2681 gen_op_store_DT0_fpr(rd);
2683 case 0x073: /* VIS I fxnors */
2684 gen_op_load_fpr_FT0(rs1);
2685 gen_op_load_fpr_FT1(rs2);
2687 gen_op_store_FT0_fpr(rd);
2689 case 0x074: /* VIS I fsrc1 */
2690 gen_op_load_fpr_DT0(rs1);
2691 gen_op_store_DT0_fpr(rd);
2693 case 0x075: /* VIS I fsrc1s */
2694 gen_op_load_fpr_FT0(rs1);
2695 gen_op_store_FT0_fpr(rd);
2697 case 0x076: /* VIS I fornot2 */
2698 gen_op_load_fpr_DT1(rs1);
2699 gen_op_load_fpr_DT0(rs2);
2701 gen_op_store_DT0_fpr(rd);
2703 case 0x077: /* VIS I fornot2s */
2704 gen_op_load_fpr_FT1(rs1);
2705 gen_op_load_fpr_FT0(rs2);
2707 gen_op_store_FT0_fpr(rd);
2709 case 0x078: /* VIS I fsrc2 */
2710 gen_op_load_fpr_DT0(rs2);
2711 gen_op_store_DT0_fpr(rd);
2713 case 0x079: /* VIS I fsrc2s */
2714 gen_op_load_fpr_FT0(rs2);
2715 gen_op_store_FT0_fpr(rd);
2717 case 0x07a: /* VIS I fornot1 */
2718 gen_op_load_fpr_DT0(rs1);
2719 gen_op_load_fpr_DT1(rs2);
2721 gen_op_store_DT0_fpr(rd);
2723 case 0x07b: /* VIS I fornot1s */
2724 gen_op_load_fpr_FT0(rs1);
2725 gen_op_load_fpr_FT1(rs2);
2727 gen_op_store_FT0_fpr(rd);
2729 case 0x07c: /* VIS I for */
2730 gen_op_load_fpr_DT0(rs1);
2731 gen_op_load_fpr_DT1(rs2);
2733 gen_op_store_DT0_fpr(rd);
2735 case 0x07d: /* VIS I fors */
2736 gen_op_load_fpr_FT0(rs1);
2737 gen_op_load_fpr_FT1(rs2);
2739 gen_op_store_FT0_fpr(rd);
2741 case 0x07e: /* VIS I fone */
2742 gen_op_movl_DT0_1();
2743 gen_op_store_DT0_fpr(rd);
2745 case 0x07f: /* VIS I fones */
2746 gen_op_movl_FT0_1();
2747 gen_op_store_FT0_fpr(rd);
2749 case 0x080: /* VIS I shutdown */
2750 case 0x081: /* VIS II siam */
2759 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2760 #ifdef TARGET_SPARC64
2765 #ifdef TARGET_SPARC64
2766 } else if (xop == 0x39) { /* V9 return */
2767 rs1 = GET_FIELD(insn, 13, 17);
2769 gen_movl_reg_T0(rs1);
2770 if (IS_IMM) { /* immediate */
2771 rs2 = GET_FIELDs(insn, 19, 31);
2775 gen_movl_simm_T1(rs2);
2780 } else { /* register */
2781 rs2 = GET_FIELD(insn, 27, 31);
2785 gen_movl_reg_T1(rs2);
2793 gen_op_check_align_T0_3();
2794 gen_op_movl_npc_T0();
2795 dc->npc = DYNAMIC_PC;
2799 rs1 = GET_FIELD(insn, 13, 17);
2800 gen_movl_reg_T0(rs1);
2801 if (IS_IMM) { /* immediate */
2802 rs2 = GET_FIELDs(insn, 19, 31);
2806 gen_movl_simm_T1(rs2);
2811 } else { /* register */
2812 rs2 = GET_FIELD(insn, 27, 31);
2816 gen_movl_reg_T1(rs2);
2823 case 0x38: /* jmpl */
2826 #ifdef TARGET_SPARC64
2827 if (dc->pc == (uint32_t)dc->pc) {
2828 gen_op_movl_T1_im(dc->pc);
2830 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2833 gen_op_movl_T1_im(dc->pc);
2835 gen_movl_T1_reg(rd);
2838 gen_op_check_align_T0_3();
2839 gen_op_movl_npc_T0();
2840 dc->npc = DYNAMIC_PC;
2843 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2844 case 0x39: /* rett, V9 return */
2846 if (!supervisor(dc))
2849 gen_op_check_align_T0_3();
2850 gen_op_movl_npc_T0();
2851 dc->npc = DYNAMIC_PC;
2856 case 0x3b: /* flush */
2859 case 0x3c: /* save */
2862 gen_movl_T0_reg(rd);
2864 case 0x3d: /* restore */
2867 gen_movl_T0_reg(rd);
2869 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2870 case 0x3e: /* V9 done/retry */
2874 if (!supervisor(dc))
2876 dc->npc = DYNAMIC_PC;
2877 dc->pc = DYNAMIC_PC;
2881 if (!supervisor(dc))
2883 dc->npc = DYNAMIC_PC;
2884 dc->pc = DYNAMIC_PC;
2900 case 3: /* load/store instructions */
2902 unsigned int xop = GET_FIELD(insn, 7, 12);
2903 rs1 = GET_FIELD(insn, 13, 17);
2905 gen_movl_reg_T0(rs1);
2906 if (xop == 0x3c || xop == 0x3e)
2908 rs2 = GET_FIELD(insn, 27, 31);
2909 gen_movl_reg_T1(rs2);
2911 else if (IS_IMM) { /* immediate */
2912 rs2 = GET_FIELDs(insn, 19, 31);
2916 gen_movl_simm_T1(rs2);
2921 } else { /* register */
2922 rs2 = GET_FIELD(insn, 27, 31);
2926 gen_movl_reg_T1(rs2);
2932 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2933 (xop > 0x17 && xop <= 0x1d ) ||
2934 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
2936 case 0x0: /* load word */
2937 #ifdef CONFIG_USER_ONLY
2938 gen_op_check_align_T0_3();
2940 #ifndef TARGET_SPARC64
2946 case 0x1: /* load unsigned byte */
2949 case 0x2: /* load unsigned halfword */
2950 #ifdef CONFIG_USER_ONLY
2951 gen_op_check_align_T0_1();
2955 case 0x3: /* load double word */
2956 gen_op_check_align_T0_7();
2960 gen_movl_T0_reg(rd + 1);
2962 case 0x9: /* load signed byte */
2965 case 0xa: /* load signed halfword */
2966 #ifdef CONFIG_USER_ONLY
2967 gen_op_check_align_T0_1();
2971 case 0xd: /* ldstub -- XXX: should be atomically */
2972 gen_op_ldst(ldstub);
2974 case 0x0f: /* swap register with memory. Also atomically */
2975 #ifdef CONFIG_USER_ONLY
2976 gen_op_check_align_T0_3();
2978 gen_movl_reg_T1(rd);
2981 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2982 case 0x10: /* load word alternate */
2983 #ifndef TARGET_SPARC64
2986 if (!supervisor(dc))
2988 #elif CONFIG_USER_ONLY
2989 gen_op_check_align_T0_3();
2991 gen_ld_asi(insn, 4, 0);
2993 case 0x11: /* load unsigned byte alternate */
2994 #ifndef TARGET_SPARC64
2997 if (!supervisor(dc))
3000 gen_ld_asi(insn, 1, 0);
3002 case 0x12: /* load unsigned halfword alternate */
3003 #ifndef TARGET_SPARC64
3006 if (!supervisor(dc))
3008 #elif CONFIG_USER_ONLY
3009 gen_op_check_align_T0_1();
3011 gen_ld_asi(insn, 2, 0);
3013 case 0x13: /* load double word alternate */
3014 #ifndef TARGET_SPARC64
3017 if (!supervisor(dc))
3022 gen_op_check_align_T0_7();
3024 gen_movl_T0_reg(rd + 1);
3026 case 0x19: /* load signed byte alternate */
3027 #ifndef TARGET_SPARC64
3030 if (!supervisor(dc))
3033 gen_ld_asi(insn, 1, 1);
3035 case 0x1a: /* load signed halfword alternate */
3036 #ifndef TARGET_SPARC64
3039 if (!supervisor(dc))
3041 #elif CONFIG_USER_ONLY
3042 gen_op_check_align_T0_1();
3044 gen_ld_asi(insn, 2, 1);
3046 case 0x1d: /* ldstuba -- XXX: should be atomically */
3047 #ifndef TARGET_SPARC64
3050 if (!supervisor(dc))
3053 gen_ldstub_asi(insn);
3055 case 0x1f: /* swap reg with alt. memory. Also atomically */
3056 #ifndef TARGET_SPARC64
3059 if (!supervisor(dc))
3061 #elif CONFIG_USER_ONLY
3062 gen_op_check_align_T0_3();
3064 gen_movl_reg_T1(rd);
3068 #ifndef TARGET_SPARC64
3069 case 0x30: /* ldc */
3070 case 0x31: /* ldcsr */
3071 case 0x33: /* lddc */
3075 #ifdef TARGET_SPARC64
3076 case 0x08: /* V9 ldsw */
3077 #ifdef CONFIG_USER_ONLY
3078 gen_op_check_align_T0_3();
3082 case 0x0b: /* V9 ldx */
3083 gen_op_check_align_T0_7();
3086 case 0x18: /* V9 ldswa */
3087 #ifdef CONFIG_USER_ONLY
3088 gen_op_check_align_T0_3();
3090 gen_ld_asi(insn, 4, 1);
3092 case 0x1b: /* V9 ldxa */
3093 gen_op_check_align_T0_7();
3094 gen_ld_asi(insn, 8, 0);
3096 case 0x2d: /* V9 prefetch, no effect */
3098 case 0x30: /* V9 ldfa */
3099 #ifdef CONFIG_USER_ONLY
3100 gen_op_check_align_T0_3();
3102 gen_ldf_asi(insn, 4);
3104 case 0x33: /* V9 lddfa */
3105 gen_op_check_align_T0_3();
3106 gen_ldf_asi(insn, 8);
3108 case 0x3d: /* V9 prefetcha, no effect */
3110 case 0x32: /* V9 ldqfa */
3116 gen_movl_T1_reg(rd);
3117 #ifdef TARGET_SPARC64
3120 } else if (xop >= 0x20 && xop < 0x24) {
3121 if (gen_trap_ifnofpu(dc))
3124 case 0x20: /* load fpreg */
3125 #ifdef CONFIG_USER_ONLY
3126 gen_op_check_align_T0_3();
3129 gen_op_store_FT0_fpr(rd);
3131 case 0x21: /* load fsr */
3132 #ifdef CONFIG_USER_ONLY
3133 gen_op_check_align_T0_3();
3138 case 0x22: /* load quad fpreg */
3140 case 0x23: /* load double fpreg */
3141 gen_op_check_align_T0_7();
3143 gen_op_store_DT0_fpr(DFPREG(rd));
3148 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3149 xop == 0xe || xop == 0x1e) {
3150 gen_movl_reg_T1(rd);
3153 #ifdef CONFIG_USER_ONLY
3154 gen_op_check_align_T0_3();
3162 #ifdef CONFIG_USER_ONLY
3163 gen_op_check_align_T0_1();
3170 gen_op_check_align_T0_7();
3172 gen_movl_reg_T2(rd + 1);
3175 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3177 #ifndef TARGET_SPARC64
3180 if (!supervisor(dc))
3183 #ifdef CONFIG_USER_ONLY
3184 gen_op_check_align_T0_3();
3186 gen_st_asi(insn, 4);
3189 #ifndef TARGET_SPARC64
3192 if (!supervisor(dc))
3195 gen_st_asi(insn, 1);
3198 #ifndef TARGET_SPARC64
3201 if (!supervisor(dc))
3204 #ifdef CONFIG_USER_ONLY
3205 gen_op_check_align_T0_1();
3207 gen_st_asi(insn, 2);
3210 #ifndef TARGET_SPARC64
3213 if (!supervisor(dc))
3218 gen_op_check_align_T0_7();
3220 gen_movl_reg_T2(rd + 1);
3224 #ifdef TARGET_SPARC64
3225 case 0x0e: /* V9 stx */
3226 gen_op_check_align_T0_7();
3229 case 0x1e: /* V9 stxa */
3230 gen_op_check_align_T0_7();
3231 gen_st_asi(insn, 8);
3237 } else if (xop > 0x23 && xop < 0x28) {
3238 if (gen_trap_ifnofpu(dc))
3242 #ifdef CONFIG_USER_ONLY
3243 gen_op_check_align_T0_3();
3245 gen_op_load_fpr_FT0(rd);
3248 case 0x25: /* stfsr, V9 stxfsr */
3249 #ifdef CONFIG_USER_ONLY
3250 gen_op_check_align_T0_3();
3255 #if !defined(CONFIG_USER_ONLY)
3256 case 0x26: /* stdfq */
3257 if (!supervisor(dc))
3259 if (gen_trap_ifnofpu(dc))
3264 gen_op_check_align_T0_7();
3265 gen_op_load_fpr_DT0(DFPREG(rd));
3271 } else if (xop > 0x33 && xop < 0x3f) {
3273 #ifdef TARGET_SPARC64
3274 case 0x34: /* V9 stfa */
3275 #ifdef CONFIG_USER_ONLY
3276 gen_op_check_align_T0_3();
3278 gen_op_load_fpr_FT0(rd);
3279 gen_stf_asi(insn, 4);
3281 case 0x37: /* V9 stdfa */
3282 gen_op_check_align_T0_3();
3283 gen_op_load_fpr_DT0(DFPREG(rd));
3284 gen_stf_asi(insn, 8);
3286 case 0x3c: /* V9 casa */
3287 #ifdef CONFIG_USER_ONLY
3288 gen_op_check_align_T0_3();
3291 gen_movl_reg_T2(rd);
3293 gen_movl_T1_reg(rd);
3295 case 0x3e: /* V9 casxa */
3296 gen_op_check_align_T0_7();
3298 gen_movl_reg_T2(rd);
3300 gen_movl_T1_reg(rd);
3302 case 0x36: /* V9 stqfa */
3305 case 0x34: /* stc */
3306 case 0x35: /* stcsr */
3307 case 0x36: /* stdcq */
3308 case 0x37: /* stdc */
3320 /* default case for non jump instructions */
3321 if (dc->npc == DYNAMIC_PC) {
3322 dc->pc = DYNAMIC_PC;
3324 } else if (dc->npc == JUMP_PC) {
3325 /* we can do a static jump */
3326 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
3330 dc->npc = dc->npc + 4;
3336 gen_op_exception(TT_ILL_INSN);
3339 #if !defined(CONFIG_USER_ONLY)
3342 gen_op_exception(TT_PRIV_INSN);
3348 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3351 #if !defined(CONFIG_USER_ONLY)
3354 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3358 #ifndef TARGET_SPARC64
3361 gen_op_exception(TT_NCP_INSN);
3367 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3368 int spc, CPUSPARCState *env)
3370 target_ulong pc_start, last_pc;
3371 uint16_t *gen_opc_end;
3372 DisasContext dc1, *dc = &dc1;
3375 memset(dc, 0, sizeof(DisasContext));
3380 dc->npc = (target_ulong) tb->cs_base;
3381 #if defined(CONFIG_USER_ONLY)
3383 dc->fpu_enabled = 1;
3385 dc->mem_idx = ((env->psrs) != 0);
3386 #ifdef TARGET_SPARC64
3387 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3389 dc->fpu_enabled = ((env->psref) != 0);
3392 gen_opc_ptr = gen_opc_buf;
3393 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3394 gen_opparam_ptr = gen_opparam_buf;
3398 if (env->nb_breakpoints > 0) {
3399 for(j = 0; j < env->nb_breakpoints; j++) {
3400 if (env->breakpoints[j] == dc->pc) {
3401 if (dc->pc != pc_start)
3413 fprintf(logfile, "Search PC...\n");
3414 j = gen_opc_ptr - gen_opc_buf;
3418 gen_opc_instr_start[lj++] = 0;
3419 gen_opc_pc[lj] = dc->pc;
3420 gen_opc_npc[lj] = dc->npc;
3421 gen_opc_instr_start[lj] = 1;
3425 disas_sparc_insn(dc);
3429 /* if the next PC is different, we abort now */
3430 if (dc->pc != (last_pc + 4))
3432 /* if we reach a page boundary, we stop generation so that the
3433 PC of a TT_TFAULT exception is always in the right page */
3434 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3436 /* if single step mode, we generate only one instruction and
3437 generate an exception */
3438 if (env->singlestep_enabled) {
3444 } while ((gen_opc_ptr < gen_opc_end) &&
3445 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3449 if (dc->pc != DYNAMIC_PC &&
3450 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3451 /* static PC and NPC: we can use direct chaining */
3452 gen_branch(dc, dc->pc, dc->npc);
3454 if (dc->pc != DYNAMIC_PC)
3461 *gen_opc_ptr = INDEX_op_end;
3463 j = gen_opc_ptr - gen_opc_buf;
3466 gen_opc_instr_start[lj++] = 0;
3472 gen_opc_jump_pc[0] = dc->jump_pc[0];
3473 gen_opc_jump_pc[1] = dc->jump_pc[1];
3475 tb->size = last_pc + 4 - pc_start;
3478 if (loglevel & CPU_LOG_TB_IN_ASM) {
3479 fprintf(logfile, "--------------\n");
3480 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3481 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3482 fprintf(logfile, "\n");
3483 if (loglevel & CPU_LOG_TB_OP) {
3484 fprintf(logfile, "OP:\n");
3485 dump_ops(gen_opc_buf, gen_opparam_buf);
3486 fprintf(logfile, "\n");
3493 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3495 return gen_intermediate_code_internal(tb, 0, env);
3498 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3500 return gen_intermediate_code_internal(tb, 1, env);
3503 extern int ram_size;
3505 void cpu_reset(CPUSPARCState *env)
3510 env->regwptr = env->regbase + (env->cwp * 16);
3511 #if defined(CONFIG_USER_ONLY)
3512 env->user_mode_only = 1;
3513 #ifdef TARGET_SPARC64
3514 env->cleanwin = NWINDOWS - 2;
3515 env->cansave = NWINDOWS - 2;
3516 env->pstate = PS_RMO | PS_PEF | PS_IE;
3517 env->asi = 0x82; // Primary no-fault
3523 #ifdef TARGET_SPARC64
3524 env->pstate = PS_PRIV;
3525 env->pc = 0x1fff0000000ULL;
3528 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3529 env->mmuregs[0] |= MMU_BM;
3531 env->npc = env->pc + 4;
3535 CPUSPARCState *cpu_sparc_init(void)
3539 env = qemu_mallocz(sizeof(CPUSPARCState));
3547 static const sparc_def_t sparc_defs[] = {
3548 #ifdef TARGET_SPARC64
3550 .name = "TI UltraSparc II",
3551 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3552 | (MAXTL << 8) | (NWINDOWS - 1)),
3553 .fpu_version = 0x00000000,
3558 .name = "Fujitsu MB86904",
3559 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3560 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3561 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3564 .name = "Fujitsu MB86907",
3565 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3566 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3567 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3570 .name = "TI MicroSparc I",
3571 .iu_version = 0x41000000,
3572 .fpu_version = 4 << 17,
3573 .mmu_version = 0x41000000,
3576 .name = "TI SuperSparc II",
3577 .iu_version = 0x40000000,
3578 .fpu_version = 0 << 17,
3579 .mmu_version = 0x04000000,
3582 .name = "Ross RT620",
3583 .iu_version = 0x1e000000,
3584 .fpu_version = 1 << 17,
3585 .mmu_version = 0x17000000,
3590 int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3597 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3598 if (strcasecmp(name, sparc_defs[i].name) == 0) {
3599 *def = &sparc_defs[i];
3608 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3612 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3613 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3615 sparc_defs[i].iu_version,
3616 sparc_defs[i].fpu_version,
3617 sparc_defs[i].mmu_version);
3621 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3623 env->version = def->iu_version;
3624 env->fsr = def->fpu_version;
3625 #if !defined(TARGET_SPARC64)
3626 env->mmuregs[0] |= def->mmu_version;
3631 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3633 void cpu_dump_state(CPUState *env, FILE *f,
3634 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3639 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3640 cpu_fprintf(f, "General Registers:\n");
3641 for (i = 0; i < 4; i++)
3642 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3643 cpu_fprintf(f, "\n");
3645 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3646 cpu_fprintf(f, "\nCurrent Register Window:\n");
3647 for (x = 0; x < 3; x++) {
3648 for (i = 0; i < 4; i++)
3649 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3650 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3651 env->regwptr[i + x * 8]);
3652 cpu_fprintf(f, "\n");
3654 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3655 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3656 env->regwptr[i + x * 8]);
3657 cpu_fprintf(f, "\n");
3659 cpu_fprintf(f, "\nFloating Point Registers:\n");
3660 for (i = 0; i < 32; i++) {
3662 cpu_fprintf(f, "%%f%02d:", i);
3663 cpu_fprintf(f, " %016lf", env->fpr[i]);
3665 cpu_fprintf(f, "\n");
3667 #ifdef TARGET_SPARC64
3668 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3669 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3670 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3671 env->cansave, env->canrestore, env->otherwin, env->wstate,
3672 env->cleanwin, NWINDOWS - 1 - env->cwp);
3674 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3675 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3676 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3677 env->psrs?'S':'-', env->psrps?'P':'-',
3678 env->psret?'E':'-', env->wim);
3680 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3683 #if defined(CONFIG_USER_ONLY)
3684 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3690 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3691 int *access_index, target_ulong address, int rw,
3694 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3696 target_phys_addr_t phys_addr;
3697 int prot, access_index;
3699 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
3700 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3702 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3708 void helper_flush(target_ulong addr)
3711 tb_invalidate_page_range(addr, addr + 8);