vcs.maemo.org Git - qemu/blob - target-sparc/translate.c

   1 /*
   2    SPARC translation
   3
   4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
   5    Copyright (C) 2003-2005 Fabrice Bellard
   6
   7    This library is free software; you can redistribute it and/or
   8    modify it under the terms of the GNU Lesser General Public
   9    License as published by the Free Software Foundation; either
  10    version 2 of the License, or (at your option) any later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    Lesser General Public License for more details.
  16
  17    You should have received a copy of the GNU Lesser General Public
  18    License along with this library; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23    TODO-list:
  24
  25    Rest of V9 instructions, VIS instructions
  26    NPC/PC static optimisations (use JUMP_TB when possible)
  27    Optimize synthetic instructions
  28    128-bit float
  29 */
  30
  31 #include <stdarg.h>
  32 #include <stdlib.h>
  33 #include <stdio.h>
  34 #include <string.h>
  35 #include <inttypes.h>
  36
  37 #include "cpu.h"
  38 #include "exec-all.h"
  39 #include "disas.h"
  40
  41 #define DEBUG_DISAS
  42
  43 #define DYNAMIC_PC  1 /* dynamic pc value */
  44 #define JUMP_PC     2 /* dynamic pc value which takes only two values
  45                          according to jump_pc[T2] */
  46
  47 typedef struct DisasContext {
  48     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
  49     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
  50     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
  51     int is_br;
  52     int mem_idx;
  53     int fpu_enabled;
  54     struct TranslationBlock *tb;
  55 } DisasContext;
  56
  57 struct sparc_def_t {
  58     const unsigned char *name;
  59     target_ulong iu_version;
  60     uint32_t fpu_version;
  61     uint32_t mmu_version;
  62 };
  63
  64 static uint16_t *gen_opc_ptr;
  65 static uint32_t *gen_opparam_ptr;
  66 extern FILE *logfile;
  67 extern int loglevel;
  68
  69 enum {
  70 #define DEF(s,n,copy_size) INDEX_op_ ## s,
  71 #include "opc.h"
  72 #undef DEF
  73     NB_OPS
  74 };
  75
  76 #include "gen-op.h"
  77
  78 // This function uses non-native bit order
  79 #define GET_FIELD(X, FROM, TO) \
  80   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
  81
  82 // This function uses the order in the manuals, i.e. bit 0 is 2^0
  83 #define GET_FIELD_SP(X, FROM, TO) \
  84     GET_FIELD(X, 31 - (TO), 31 - (FROM))
  85
  86 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
  87 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
  88
  89 #ifdef TARGET_SPARC64
  90 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
  91 #else
  92 #define DFPREG(r) (r & 0x1e)
  93 #endif
  94
  95 #ifdef USE_DIRECT_JUMP
  96 #define TBPARAM(x)
  97 #else
  98 #define TBPARAM(x) (long)(x)
  99 #endif
 100
 101 static int sign_extend(int x, int len)
 102 {
 103     len = 32 - len;
 104     return (x << len) >> len;
 105 }
 106
 107 #define IS_IMM (insn & (1<<13))
 108
 109 static void disas_sparc_insn(DisasContext * dc);
 110
 111 static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
 112     {
 113      gen_op_movl_g0_T0,
 114      gen_op_movl_g1_T0,
 115      gen_op_movl_g2_T0,
 116      gen_op_movl_g3_T0,
 117      gen_op_movl_g4_T0,
 118      gen_op_movl_g5_T0,
 119      gen_op_movl_g6_T0,
 120      gen_op_movl_g7_T0,
 121      gen_op_movl_o0_T0,
 122      gen_op_movl_o1_T0,
 123      gen_op_movl_o2_T0,
 124      gen_op_movl_o3_T0,
 125      gen_op_movl_o4_T0,
 126      gen_op_movl_o5_T0,
 127      gen_op_movl_o6_T0,
 128      gen_op_movl_o7_T0,
 129      gen_op_movl_l0_T0,
 130      gen_op_movl_l1_T0,
 131      gen_op_movl_l2_T0,
 132      gen_op_movl_l3_T0,
 133      gen_op_movl_l4_T0,
 134      gen_op_movl_l5_T0,
 135      gen_op_movl_l6_T0,
 136      gen_op_movl_l7_T0,
 137      gen_op_movl_i0_T0,
 138      gen_op_movl_i1_T0,
 139      gen_op_movl_i2_T0,
 140      gen_op_movl_i3_T0,
 141      gen_op_movl_i4_T0,
 142      gen_op_movl_i5_T0,
 143      gen_op_movl_i6_T0,
 144      gen_op_movl_i7_T0,
 145      },
 146     {
 147      gen_op_movl_g0_T1,
 148      gen_op_movl_g1_T1,
 149      gen_op_movl_g2_T1,
 150      gen_op_movl_g3_T1,
 151      gen_op_movl_g4_T1,
 152      gen_op_movl_g5_T1,
 153      gen_op_movl_g6_T1,
 154      gen_op_movl_g7_T1,
 155      gen_op_movl_o0_T1,
 156      gen_op_movl_o1_T1,
 157      gen_op_movl_o2_T1,
 158      gen_op_movl_o3_T1,
 159      gen_op_movl_o4_T1,
 160      gen_op_movl_o5_T1,
 161      gen_op_movl_o6_T1,
 162      gen_op_movl_o7_T1,
 163      gen_op_movl_l0_T1,
 164      gen_op_movl_l1_T1,
 165      gen_op_movl_l2_T1,
 166      gen_op_movl_l3_T1,
 167      gen_op_movl_l4_T1,
 168      gen_op_movl_l5_T1,
 169      gen_op_movl_l6_T1,
 170      gen_op_movl_l7_T1,
 171      gen_op_movl_i0_T1,
 172      gen_op_movl_i1_T1,
 173      gen_op_movl_i2_T1,
 174      gen_op_movl_i3_T1,
 175      gen_op_movl_i4_T1,
 176      gen_op_movl_i5_T1,
 177      gen_op_movl_i6_T1,
 178      gen_op_movl_i7_T1,
 179      }
 180 };
 181
 182 static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
 183     {
 184      gen_op_movl_T0_g0,
 185      gen_op_movl_T0_g1,
 186      gen_op_movl_T0_g2,
 187      gen_op_movl_T0_g3,
 188      gen_op_movl_T0_g4,
 189      gen_op_movl_T0_g5,
 190      gen_op_movl_T0_g6,
 191      gen_op_movl_T0_g7,
 192      gen_op_movl_T0_o0,
 193      gen_op_movl_T0_o1,
 194      gen_op_movl_T0_o2,
 195      gen_op_movl_T0_o3,
 196      gen_op_movl_T0_o4,
 197      gen_op_movl_T0_o5,
 198      gen_op_movl_T0_o6,
 199      gen_op_movl_T0_o7,
 200      gen_op_movl_T0_l0,
 201      gen_op_movl_T0_l1,
 202      gen_op_movl_T0_l2,
 203      gen_op_movl_T0_l3,
 204      gen_op_movl_T0_l4,
 205      gen_op_movl_T0_l5,
 206      gen_op_movl_T0_l6,
 207      gen_op_movl_T0_l7,
 208      gen_op_movl_T0_i0,
 209      gen_op_movl_T0_i1,
 210      gen_op_movl_T0_i2,
 211      gen_op_movl_T0_i3,
 212      gen_op_movl_T0_i4,
 213      gen_op_movl_T0_i5,
 214      gen_op_movl_T0_i6,
 215      gen_op_movl_T0_i7,
 216      },
 217     {
 218      gen_op_movl_T1_g0,
 219      gen_op_movl_T1_g1,
 220      gen_op_movl_T1_g2,
 221      gen_op_movl_T1_g3,
 222      gen_op_movl_T1_g4,
 223      gen_op_movl_T1_g5,
 224      gen_op_movl_T1_g6,
 225      gen_op_movl_T1_g7,
 226      gen_op_movl_T1_o0,
 227      gen_op_movl_T1_o1,
 228      gen_op_movl_T1_o2,
 229      gen_op_movl_T1_o3,
 230      gen_op_movl_T1_o4,
 231      gen_op_movl_T1_o5,
 232      gen_op_movl_T1_o6,
 233      gen_op_movl_T1_o7,
 234      gen_op_movl_T1_l0,
 235      gen_op_movl_T1_l1,
 236      gen_op_movl_T1_l2,
 237      gen_op_movl_T1_l3,
 238      gen_op_movl_T1_l4,
 239      gen_op_movl_T1_l5,
 240      gen_op_movl_T1_l6,
 241      gen_op_movl_T1_l7,
 242      gen_op_movl_T1_i0,
 243      gen_op_movl_T1_i1,
 244      gen_op_movl_T1_i2,
 245      gen_op_movl_T1_i3,
 246      gen_op_movl_T1_i4,
 247      gen_op_movl_T1_i5,
 248      gen_op_movl_T1_i6,
 249      gen_op_movl_T1_i7,
 250      },
 251     {
 252      gen_op_movl_T2_g0,
 253      gen_op_movl_T2_g1,
 254      gen_op_movl_T2_g2,
 255      gen_op_movl_T2_g3,
 256      gen_op_movl_T2_g4,
 257      gen_op_movl_T2_g5,
 258      gen_op_movl_T2_g6,
 259      gen_op_movl_T2_g7,
 260      gen_op_movl_T2_o0,
 261      gen_op_movl_T2_o1,
 262      gen_op_movl_T2_o2,
 263      gen_op_movl_T2_o3,
 264      gen_op_movl_T2_o4,
 265      gen_op_movl_T2_o5,
 266      gen_op_movl_T2_o6,
 267      gen_op_movl_T2_o7,
 268      gen_op_movl_T2_l0,
 269      gen_op_movl_T2_l1,
 270      gen_op_movl_T2_l2,
 271      gen_op_movl_T2_l3,
 272      gen_op_movl_T2_l4,
 273      gen_op_movl_T2_l5,
 274      gen_op_movl_T2_l6,
 275      gen_op_movl_T2_l7,
 276      gen_op_movl_T2_i0,
 277      gen_op_movl_T2_i1,
 278      gen_op_movl_T2_i2,
 279      gen_op_movl_T2_i3,
 280      gen_op_movl_T2_i4,
 281      gen_op_movl_T2_i5,
 282      gen_op_movl_T2_i6,
 283      gen_op_movl_T2_i7,
 284      }
 285 };
 286
 287 static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
 288     gen_op_movl_T0_im,
 289     gen_op_movl_T1_im,
 290     gen_op_movl_T2_im
 291 };
 292
 293 // Sign extending version
 294 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
 295     gen_op_movl_T0_sim,
 296     gen_op_movl_T1_sim,
 297     gen_op_movl_T2_sim
 298 };
 299
 300 #ifdef TARGET_SPARC64
 301 #define GEN32(func, NAME) \
 302 static GenOpFunc * const NAME ## _table [64] = {                              \
 303 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 304 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 305 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 306 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 307 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 308 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 309 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 310 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 311 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
 312 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
 313 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
 314 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
 315 };                                                                            \
 316 static inline void func(int n)                                                \
 317 {                                                                             \
 318     NAME ## _table[n]();                                                      \
 319 }
 320 #else
 321 #define GEN32(func, NAME) \
 322 static GenOpFunc *const NAME ## _table [32] = {                               \
 323 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
 324 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
 325 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
 326 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
 327 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
 328 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 329 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 330 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 331 };                                                                            \
 332 static inline void func(int n)                                                \
 333 {                                                                             \
 334     NAME ## _table[n]();                                                      \
 335 }
 336 #endif
 337
 338 /* floating point registers moves */
 339 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
 340 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
 341 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
 342 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
 343
 344 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
 345 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
 346 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
 347 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
 348
 349 #ifdef ALIGN_7_BUGS_FIXED
 350 #else
 351 #ifndef CONFIG_USER_ONLY
 352 #define gen_op_check_align_T0_7()
 353 #endif
 354 #endif
 355
 356 /* moves */
 357 #ifdef CONFIG_USER_ONLY
 358 #define supervisor(dc) 0
 359 #ifdef TARGET_SPARC64
 360 #define hypervisor(dc) 0
 361 #endif
 362 #define gen_op_ldst(name)        gen_op_##name##_raw()
 363 #else
 364 #define supervisor(dc) (dc->mem_idx == 1)
 365 #ifdef TARGET_SPARC64
 366 #define hypervisor(dc) (dc->mem_idx == 2)
 367 #endif
 368 #define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
 369 #define OP_LD_TABLE(width)                                              \
 370     static GenOpFunc * const gen_op_##width[] = {                       \
 371         &gen_op_##width##_user,                                         \
 372         &gen_op_##width##_kernel,                                       \
 373     };
 374 #endif
 375
 376 #ifndef CONFIG_USER_ONLY
 377 OP_LD_TABLE(ld);
 378 OP_LD_TABLE(st);
 379 OP_LD_TABLE(ldub);
 380 OP_LD_TABLE(lduh);
 381 OP_LD_TABLE(ldsb);
 382 OP_LD_TABLE(ldsh);
 383 OP_LD_TABLE(stb);
 384 OP_LD_TABLE(sth);
 385 OP_LD_TABLE(std);
 386 OP_LD_TABLE(ldstub);
 387 OP_LD_TABLE(swap);
 388 OP_LD_TABLE(ldd);
 389 OP_LD_TABLE(stf);
 390 OP_LD_TABLE(stdf);
 391 OP_LD_TABLE(ldf);
 392 OP_LD_TABLE(lddf);
 393
 394 #ifdef TARGET_SPARC64
 395 OP_LD_TABLE(lduw);
 396 OP_LD_TABLE(ldsw);
 397 OP_LD_TABLE(ldx);
 398 OP_LD_TABLE(stx);
 399 #endif
 400 #endif
 401
 402 /* asi moves */
 403 #ifdef TARGET_SPARC64
 404 static inline void gen_ld_asi(int insn, int size, int sign)
 405 {
 406     int asi, offset;
 407
 408     if (IS_IMM) {
 409         offset = GET_FIELD(insn, 25, 31);
 410         gen_op_ld_asi_reg(offset, size, sign);
 411     } else {
 412         asi = GET_FIELD(insn, 19, 26);
 413         gen_op_ld_asi(asi, size, sign);
 414     }
 415 }
 416
 417 static inline void gen_st_asi(int insn, int size)
 418 {
 419     int asi, offset;
 420
 421     if (IS_IMM) {
 422         offset = GET_FIELD(insn, 25, 31);
 423         gen_op_st_asi_reg(offset, size);
 424     } else {
 425         asi = GET_FIELD(insn, 19, 26);
 426         gen_op_st_asi(asi, size);
 427     }
 428 }
 429
 430 static inline void gen_ldf_asi(int insn, int size)
 431 {
 432     int asi, offset, rd;
 433
 434     rd = DFPREG(GET_FIELD(insn, 2, 6));
 435     if (IS_IMM) {
 436         offset = GET_FIELD(insn, 25, 31);
 437         gen_op_ldf_asi_reg(offset, size, rd);
 438     } else {
 439         asi = GET_FIELD(insn, 19, 26);
 440         gen_op_ldf_asi(asi, size, rd);
 441     }
 442 }
 443
 444 static inline void gen_stf_asi(int insn, int size)
 445 {
 446     int asi, offset, rd;
 447
 448     rd = DFPREG(GET_FIELD(insn, 2, 6));
 449     if (IS_IMM) {
 450         offset = GET_FIELD(insn, 25, 31);
 451         gen_op_stf_asi_reg(offset, size, rd);
 452     } else {
 453         asi = GET_FIELD(insn, 19, 26);
 454         gen_op_stf_asi(asi, size, rd);
 455     }
 456 }
 457
 458 static inline void gen_swap_asi(int insn)
 459 {
 460     int asi, offset;
 461
 462     if (IS_IMM) {
 463         offset = GET_FIELD(insn, 25, 31);
 464         gen_op_swap_asi_reg(offset);
 465     } else {
 466         asi = GET_FIELD(insn, 19, 26);
 467         gen_op_swap_asi(asi);
 468     }
 469 }
 470
 471 static inline void gen_ldstub_asi(int insn)
 472 {
 473     int asi, offset;
 474
 475     if (IS_IMM) {
 476         offset = GET_FIELD(insn, 25, 31);
 477         gen_op_ldstub_asi_reg(offset);
 478     } else {
 479         asi = GET_FIELD(insn, 19, 26);
 480         gen_op_ldstub_asi(asi);
 481     }
 482 }
 483
 484 static inline void gen_ldda_asi(int insn)
 485 {
 486     int asi, offset;
 487
 488     if (IS_IMM) {
 489         offset = GET_FIELD(insn, 25, 31);
 490         gen_op_ldda_asi_reg(offset);
 491     } else {
 492         asi = GET_FIELD(insn, 19, 26);
 493         gen_op_ldda_asi(asi);
 494     }
 495 }
 496
 497 static inline void gen_stda_asi(int insn)
 498 {
 499     int asi, offset;
 500
 501     if (IS_IMM) {
 502         offset = GET_FIELD(insn, 25, 31);
 503         gen_op_stda_asi_reg(offset);
 504     } else {
 505         asi = GET_FIELD(insn, 19, 26);
 506         gen_op_stda_asi(asi);
 507     }
 508 }
 509
 510 static inline void gen_cas_asi(int insn)
 511 {
 512     int asi, offset;
 513
 514     if (IS_IMM) {
 515         offset = GET_FIELD(insn, 25, 31);
 516         gen_op_cas_asi_reg(offset);
 517     } else {
 518         asi = GET_FIELD(insn, 19, 26);
 519         gen_op_cas_asi(asi);
 520     }
 521 }
 522
 523 static inline void gen_casx_asi(int insn)
 524 {
 525     int asi, offset;
 526
 527     if (IS_IMM) {
 528         offset = GET_FIELD(insn, 25, 31);
 529         gen_op_casx_asi_reg(offset);
 530     } else {
 531         asi = GET_FIELD(insn, 19, 26);
 532         gen_op_casx_asi(asi);
 533     }
 534 }
 535
 536 #elif !defined(CONFIG_USER_ONLY)
 537
 538 static inline void gen_ld_asi(int insn, int size, int sign)
 539 {
 540     int asi;
 541
 542     asi = GET_FIELD(insn, 19, 26);
 543     gen_op_ld_asi(asi, size, sign);
 544 }
 545
 546 static inline void gen_st_asi(int insn, int size)
 547 {
 548     int asi;
 549
 550     asi = GET_FIELD(insn, 19, 26);
 551     gen_op_st_asi(asi, size);
 552 }
 553
 554 static inline void gen_ldstub_asi(int insn)
 555 {
 556     int asi;
 557
 558     asi = GET_FIELD(insn, 19, 26);
 559     gen_op_ldstub_asi(asi);
 560 }
 561
 562 static inline void gen_swap_asi(int insn)
 563 {
 564     int asi;
 565
 566     asi = GET_FIELD(insn, 19, 26);
 567     gen_op_swap_asi(asi);
 568 }
 569
 570 static inline void gen_ldda_asi(int insn)
 571 {
 572     int asi;
 573
 574     asi = GET_FIELD(insn, 19, 26);
 575     gen_op_ld_asi(asi, 8, 0);
 576 }
 577
 578 static inline void gen_stda_asi(int insn)
 579 {
 580     int asi;
 581
 582     asi = GET_FIELD(insn, 19, 26);
 583     gen_op_st_asi(asi, 8);
 584 }
 585 #endif
 586
 587 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
 588 {
 589     gen_op_movl_TN_im[reg](imm);
 590 }
 591
 592 static inline void gen_movl_imm_T1(uint32_t val)
 593 {
 594     gen_movl_imm_TN(1, val);
 595 }
 596
 597 static inline void gen_movl_imm_T0(uint32_t val)
 598 {
 599     gen_movl_imm_TN(0, val);
 600 }
 601
 602 static inline void gen_movl_simm_TN(int reg, int32_t imm)
 603 {
 604     gen_op_movl_TN_sim[reg](imm);
 605 }
 606
 607 static inline void gen_movl_simm_T1(int32_t val)
 608 {
 609     gen_movl_simm_TN(1, val);
 610 }
 611
 612 static inline void gen_movl_simm_T0(int32_t val)
 613 {
 614     gen_movl_simm_TN(0, val);
 615 }
 616
 617 static inline void gen_movl_reg_TN(int reg, int t)
 618 {
 619     if (reg)
 620         gen_op_movl_reg_TN[t][reg] ();
 621     else
 622         gen_movl_imm_TN(t, 0);
 623 }
 624
 625 static inline void gen_movl_reg_T0(int reg)
 626 {
 627     gen_movl_reg_TN(reg, 0);
 628 }
 629
 630 static inline void gen_movl_reg_T1(int reg)
 631 {
 632     gen_movl_reg_TN(reg, 1);
 633 }
 634
 635 static inline void gen_movl_reg_T2(int reg)
 636 {
 637     gen_movl_reg_TN(reg, 2);
 638 }
 639
 640 static inline void gen_movl_TN_reg(int reg, int t)
 641 {
 642     if (reg)
 643         gen_op_movl_TN_reg[t][reg] ();
 644 }
 645
 646 static inline void gen_movl_T0_reg(int reg)
 647 {
 648     gen_movl_TN_reg(reg, 0);
 649 }
 650
 651 static inline void gen_movl_T1_reg(int reg)
 652 {
 653     gen_movl_TN_reg(reg, 1);
 654 }
 655
 656 static inline void gen_jmp_im(target_ulong pc)
 657 {
 658 #ifdef TARGET_SPARC64
 659     if (pc == (uint32_t)pc) {
 660         gen_op_jmp_im(pc);
 661     } else {
 662         gen_op_jmp_im64(pc >> 32, pc);
 663     }
 664 #else
 665     gen_op_jmp_im(pc);
 666 #endif
 667 }
 668
 669 static inline void gen_movl_npc_im(target_ulong npc)
 670 {
 671 #ifdef TARGET_SPARC64
 672     if (npc == (uint32_t)npc) {
 673         gen_op_movl_npc_im(npc);
 674     } else {
 675         gen_op_movq_npc_im64(npc >> 32, npc);
 676     }
 677 #else
 678     gen_op_movl_npc_im(npc);
 679 #endif
 680 }
 681
 682 static inline void gen_goto_tb(DisasContext *s, int tb_num,
 683                                target_ulong pc, target_ulong npc)
 684 {
 685     TranslationBlock *tb;
 686
 687     tb = s->tb;
 688     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
 689         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
 690         /* jump to same page: we can use a direct jump */
 691         if (tb_num == 0)
 692             gen_op_goto_tb0(TBPARAM(tb));
 693         else
 694             gen_op_goto_tb1(TBPARAM(tb));
 695         gen_jmp_im(pc);
 696         gen_movl_npc_im(npc);
 697         gen_op_movl_T0_im((long)tb + tb_num);
 698         gen_op_exit_tb();
 699     } else {
 700         /* jump to another page: currently not optimized */
 701         gen_jmp_im(pc);
 702         gen_movl_npc_im(npc);
 703         gen_op_movl_T0_0();
 704         gen_op_exit_tb();
 705     }
 706 }
 707
 708 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
 709                                target_ulong pc2)
 710 {
 711     int l1;
 712
 713     l1 = gen_new_label();
 714
 715     gen_op_jz_T2_label(l1);
 716
 717     gen_goto_tb(dc, 0, pc1, pc1 + 4);
 718
 719     gen_set_label(l1);
 720     gen_goto_tb(dc, 1, pc2, pc2 + 4);
 721 }
 722
 723 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
 724                                 target_ulong pc2)
 725 {
 726     int l1;
 727
 728     l1 = gen_new_label();
 729
 730     gen_op_jz_T2_label(l1);
 731
 732     gen_goto_tb(dc, 0, pc2, pc1);
 733
 734     gen_set_label(l1);
 735     gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
 736 }
 737
 738 static inline void gen_branch(DisasContext *dc, target_ulong pc,
 739                               target_ulong npc)
 740 {
 741     gen_goto_tb(dc, 0, pc, npc);
 742 }
 743
 744 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
 745 {
 746     int l1, l2;
 747
 748     l1 = gen_new_label();
 749     l2 = gen_new_label();
 750     gen_op_jz_T2_label(l1);
 751
 752     gen_movl_npc_im(npc1);
 753     gen_op_jmp_label(l2);
 754
 755     gen_set_label(l1);
 756     gen_movl_npc_im(npc2);
 757     gen_set_label(l2);
 758 }
 759
 760 /* call this function before using T2 as it may have been set for a jump */
 761 static inline void flush_T2(DisasContext * dc)
 762 {
 763     if (dc->npc == JUMP_PC) {
 764         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 765         dc->npc = DYNAMIC_PC;
 766     }
 767 }
 768
 769 static inline void save_npc(DisasContext * dc)
 770 {
 771     if (dc->npc == JUMP_PC) {
 772         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 773         dc->npc = DYNAMIC_PC;
 774     } else if (dc->npc != DYNAMIC_PC) {
 775         gen_movl_npc_im(dc->npc);
 776     }
 777 }
 778
 779 static inline void save_state(DisasContext * dc)
 780 {
 781     gen_jmp_im(dc->pc);
 782     save_npc(dc);
 783 }
 784
 785 static inline void gen_mov_pc_npc(DisasContext * dc)
 786 {
 787     if (dc->npc == JUMP_PC) {
 788         gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
 789         gen_op_mov_pc_npc();
 790         dc->pc = DYNAMIC_PC;
 791     } else if (dc->npc == DYNAMIC_PC) {
 792         gen_op_mov_pc_npc();
 793         dc->pc = DYNAMIC_PC;
 794     } else {
 795         dc->pc = dc->npc;
 796     }
 797 }
 798
 799 static GenOpFunc * const gen_cond[2][16] = {
 800     {
 801         gen_op_eval_bn,
 802         gen_op_eval_be,
 803         gen_op_eval_ble,
 804         gen_op_eval_bl,
 805         gen_op_eval_bleu,
 806         gen_op_eval_bcs,
 807         gen_op_eval_bneg,
 808         gen_op_eval_bvs,
 809         gen_op_eval_ba,
 810         gen_op_eval_bne,
 811         gen_op_eval_bg,
 812         gen_op_eval_bge,
 813         gen_op_eval_bgu,
 814         gen_op_eval_bcc,
 815         gen_op_eval_bpos,
 816         gen_op_eval_bvc,
 817     },
 818     {
 819 #ifdef TARGET_SPARC64
 820         gen_op_eval_bn,
 821         gen_op_eval_xbe,
 822         gen_op_eval_xble,
 823         gen_op_eval_xbl,
 824         gen_op_eval_xbleu,
 825         gen_op_eval_xbcs,
 826         gen_op_eval_xbneg,
 827         gen_op_eval_xbvs,
 828         gen_op_eval_ba,
 829         gen_op_eval_xbne,
 830         gen_op_eval_xbg,
 831         gen_op_eval_xbge,
 832         gen_op_eval_xbgu,
 833         gen_op_eval_xbcc,
 834         gen_op_eval_xbpos,
 835         gen_op_eval_xbvc,
 836 #endif
 837     },
 838 };
 839
 840 static GenOpFunc * const gen_fcond[4][16] = {
 841     {
 842         gen_op_eval_bn,
 843         gen_op_eval_fbne,
 844         gen_op_eval_fblg,
 845         gen_op_eval_fbul,
 846         gen_op_eval_fbl,
 847         gen_op_eval_fbug,
 848         gen_op_eval_fbg,
 849         gen_op_eval_fbu,
 850         gen_op_eval_ba,
 851         gen_op_eval_fbe,
 852         gen_op_eval_fbue,
 853         gen_op_eval_fbge,
 854         gen_op_eval_fbuge,
 855         gen_op_eval_fble,
 856         gen_op_eval_fbule,
 857         gen_op_eval_fbo,
 858     },
 859 #ifdef TARGET_SPARC64
 860     {
 861         gen_op_eval_bn,
 862         gen_op_eval_fbne_fcc1,
 863         gen_op_eval_fblg_fcc1,
 864         gen_op_eval_fbul_fcc1,
 865         gen_op_eval_fbl_fcc1,
 866         gen_op_eval_fbug_fcc1,
 867         gen_op_eval_fbg_fcc1,
 868         gen_op_eval_fbu_fcc1,
 869         gen_op_eval_ba,
 870         gen_op_eval_fbe_fcc1,
 871         gen_op_eval_fbue_fcc1,
 872         gen_op_eval_fbge_fcc1,
 873         gen_op_eval_fbuge_fcc1,
 874         gen_op_eval_fble_fcc1,
 875         gen_op_eval_fbule_fcc1,
 876         gen_op_eval_fbo_fcc1,
 877     },
 878     {
 879         gen_op_eval_bn,
 880         gen_op_eval_fbne_fcc2,
 881         gen_op_eval_fblg_fcc2,
 882         gen_op_eval_fbul_fcc2,
 883         gen_op_eval_fbl_fcc2,
 884         gen_op_eval_fbug_fcc2,
 885         gen_op_eval_fbg_fcc2,
 886         gen_op_eval_fbu_fcc2,
 887         gen_op_eval_ba,
 888         gen_op_eval_fbe_fcc2,
 889         gen_op_eval_fbue_fcc2,
 890         gen_op_eval_fbge_fcc2,
 891         gen_op_eval_fbuge_fcc2,
 892         gen_op_eval_fble_fcc2,
 893         gen_op_eval_fbule_fcc2,
 894         gen_op_eval_fbo_fcc2,
 895     },
 896     {
 897         gen_op_eval_bn,
 898         gen_op_eval_fbne_fcc3,
 899         gen_op_eval_fblg_fcc3,
 900         gen_op_eval_fbul_fcc3,
 901         gen_op_eval_fbl_fcc3,
 902         gen_op_eval_fbug_fcc3,
 903         gen_op_eval_fbg_fcc3,
 904         gen_op_eval_fbu_fcc3,
 905         gen_op_eval_ba,
 906         gen_op_eval_fbe_fcc3,
 907         gen_op_eval_fbue_fcc3,
 908         gen_op_eval_fbge_fcc3,
 909         gen_op_eval_fbuge_fcc3,
 910         gen_op_eval_fble_fcc3,
 911         gen_op_eval_fbule_fcc3,
 912         gen_op_eval_fbo_fcc3,
 913     },
 914 #else
 915     {}, {}, {},
 916 #endif
 917 };
 918
 919 #ifdef TARGET_SPARC64
 920 static void gen_cond_reg(int cond)
 921 {
 922         switch (cond) {
 923         case 0x1:
 924             gen_op_eval_brz();
 925             break;
 926         case 0x2:
 927             gen_op_eval_brlez();
 928             break;
 929         case 0x3:
 930             gen_op_eval_brlz();
 931             break;
 932         case 0x5:
 933             gen_op_eval_brnz();
 934             break;
 935         case 0x6:
 936             gen_op_eval_brgz();
 937             break;
 938         default:
 939         case 0x7:
 940             gen_op_eval_brgez();
 941             break;
 942         }
 943 }
 944 #endif
 945
 946 /* XXX: potentially incorrect if dynamic npc */
 947 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
 948 {
 949     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 950     target_ulong target = dc->pc + offset;
 951
 952     if (cond == 0x0) {
 953         /* unconditional not taken */
 954         if (a) {
 955             dc->pc = dc->npc + 4;
 956             dc->npc = dc->pc + 4;
 957         } else {
 958             dc->pc = dc->npc;
 959             dc->npc = dc->pc + 4;
 960         }
 961     } else if (cond == 0x8) {
 962         /* unconditional taken */
 963         if (a) {
 964             dc->pc = target;
 965             dc->npc = dc->pc + 4;
 966         } else {
 967             dc->pc = dc->npc;
 968             dc->npc = target;
 969         }
 970     } else {
 971         flush_T2(dc);
 972         gen_cond[cc][cond]();
 973         if (a) {
 974             gen_branch_a(dc, target, dc->npc);
 975             dc->is_br = 1;
 976         } else {
 977             dc->pc = dc->npc;
 978             dc->jump_pc[0] = target;
 979             dc->jump_pc[1] = dc->npc + 4;
 980             dc->npc = JUMP_PC;
 981         }
 982     }
 983 }
 984
 985 /* XXX: potentially incorrect if dynamic npc */
 986 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
 987 {
 988     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
 989     target_ulong target = dc->pc + offset;
 990
 991     if (cond == 0x0) {
 992         /* unconditional not taken */
 993         if (a) {
 994             dc->pc = dc->npc + 4;
 995             dc->npc = dc->pc + 4;
 996         } else {
 997             dc->pc = dc->npc;
 998             dc->npc = dc->pc + 4;
 999         }
1000     } else if (cond == 0x8) {
1001         /* unconditional taken */
1002         if (a) {
1003             dc->pc = target;
1004             dc->npc = dc->pc + 4;
1005         } else {
1006             dc->pc = dc->npc;
1007             dc->npc = target;
1008         }
1009     } else {
1010         flush_T2(dc);
1011         gen_fcond[cc][cond]();
1012         if (a) {
1013             gen_branch_a(dc, target, dc->npc);
1014             dc->is_br = 1;
1015         } else {
1016             dc->pc = dc->npc;
1017             dc->jump_pc[0] = target;
1018             dc->jump_pc[1] = dc->npc + 4;
1019             dc->npc = JUMP_PC;
1020         }
1021     }
1022 }
1023
1024 #ifdef TARGET_SPARC64
1025 /* XXX: potentially incorrect if dynamic npc */
1026 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1027 {
1028     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1029     target_ulong target = dc->pc + offset;
1030
1031     flush_T2(dc);
1032     gen_cond_reg(cond);
1033     if (a) {
1034         gen_branch_a(dc, target, dc->npc);
1035         dc->is_br = 1;
1036     } else {
1037         dc->pc = dc->npc;
1038         dc->jump_pc[0] = target;
1039         dc->jump_pc[1] = dc->npc + 4;
1040         dc->npc = JUMP_PC;
1041     }
1042 }
1043
1044 static GenOpFunc * const gen_fcmps[4] = {
1045     gen_op_fcmps,
1046     gen_op_fcmps_fcc1,
1047     gen_op_fcmps_fcc2,
1048     gen_op_fcmps_fcc3,
1049 };
1050
1051 static GenOpFunc * const gen_fcmpd[4] = {
1052     gen_op_fcmpd,
1053     gen_op_fcmpd_fcc1,
1054     gen_op_fcmpd_fcc2,
1055     gen_op_fcmpd_fcc3,
1056 };
1057
1058 static GenOpFunc * const gen_fcmpes[4] = {
1059     gen_op_fcmpes,
1060     gen_op_fcmpes_fcc1,
1061     gen_op_fcmpes_fcc2,
1062     gen_op_fcmpes_fcc3,
1063 };
1064
1065 static GenOpFunc * const gen_fcmped[4] = {
1066     gen_op_fcmped,
1067     gen_op_fcmped_fcc1,
1068     gen_op_fcmped_fcc2,
1069     gen_op_fcmped_fcc3,
1070 };
1071
1072 #endif
1073
1074 static int gen_trap_ifnofpu(DisasContext * dc)
1075 {
1076 #if !defined(CONFIG_USER_ONLY)
1077     if (!dc->fpu_enabled) {
1078         save_state(dc);
1079         gen_op_exception(TT_NFPU_INSN);
1080         dc->is_br = 1;
1081         return 1;
1082     }
1083 #endif
1084     return 0;
1085 }
1086
1087 /* before an instruction, dc->pc must be static */
1088 static void disas_sparc_insn(DisasContext * dc)
1089 {
1090     unsigned int insn, opc, rs1, rs2, rd;
1091
1092     insn = ldl_code(dc->pc);
1093     opc = GET_FIELD(insn, 0, 1);
1094
1095     rd = GET_FIELD(insn, 2, 6);
1096     switch (opc) {
1097     case 0:                     /* branches/sethi */
1098         {
1099             unsigned int xop = GET_FIELD(insn, 7, 9);
1100             int32_t target;
1101             switch (xop) {
1102 #ifdef TARGET_SPARC64
1103             case 0x1:           /* V9 BPcc */
1104                 {
1105                     int cc;
1106
1107                     target = GET_FIELD_SP(insn, 0, 18);
1108                     target = sign_extend(target, 18);
1109                     target <<= 2;
1110                     cc = GET_FIELD_SP(insn, 20, 21);
1111                     if (cc == 0)
1112                         do_branch(dc, target, insn, 0);
1113                     else if (cc == 2)
1114                         do_branch(dc, target, insn, 1);
1115                     else
1116                         goto illegal_insn;
1117                     goto jmp_insn;
1118                 }
1119             case 0x3:           /* V9 BPr */
1120                 {
1121                     target = GET_FIELD_SP(insn, 0, 13) |
1122                         (GET_FIELD_SP(insn, 20, 21) << 14);
1123                     target = sign_extend(target, 16);
1124                     target <<= 2;
1125                     rs1 = GET_FIELD(insn, 13, 17);
1126                     gen_movl_reg_T0(rs1);
1127                     do_branch_reg(dc, target, insn);
1128                     goto jmp_insn;
1129                 }
1130             case 0x5:           /* V9 FBPcc */
1131                 {
1132                     int cc = GET_FIELD_SP(insn, 20, 21);
1133                     if (gen_trap_ifnofpu(dc))
1134                         goto jmp_insn;
1135                     target = GET_FIELD_SP(insn, 0, 18);
1136                     target = sign_extend(target, 19);
1137                     target <<= 2;
1138                     do_fbranch(dc, target, insn, cc);
1139                     goto jmp_insn;
1140                 }
1141 #else
1142             case 0x7:           /* CBN+x */
1143                 {
1144                     goto ncp_insn;
1145                 }
1146 #endif
1147             case 0x2:           /* BN+x */
1148                 {
1149                     target = GET_FIELD(insn, 10, 31);
1150                     target = sign_extend(target, 22);
1151                     target <<= 2;
1152                     do_branch(dc, target, insn, 0);
1153                     goto jmp_insn;
1154                 }
1155             case 0x6:           /* FBN+x */
1156                 {
1157                     if (gen_trap_ifnofpu(dc))
1158                         goto jmp_insn;
1159                     target = GET_FIELD(insn, 10, 31);
1160                     target = sign_extend(target, 22);
1161                     target <<= 2;
1162                     do_fbranch(dc, target, insn, 0);
1163                     goto jmp_insn;
1164                 }
1165             case 0x4:           /* SETHI */
1166 #define OPTIM
1167 #if defined(OPTIM)
1168                 if (rd) { // nop
1169 #endif
1170                     uint32_t value = GET_FIELD(insn, 10, 31);
1171                     gen_movl_imm_T0(value << 10);
1172                     gen_movl_T0_reg(rd);
1173 #if defined(OPTIM)
1174                 }
1175 #endif
1176                 break;
1177             case 0x0:           /* UNIMPL */
1178             default:
1179                 goto illegal_insn;
1180             }
1181             break;
1182         }
1183         break;
1184     case 1:
1185         /*CALL*/ {
1186             target_long target = GET_FIELDs(insn, 2, 31) << 2;
1187
1188 #ifdef TARGET_SPARC64
1189             if (dc->pc == (uint32_t)dc->pc) {
1190                 gen_op_movl_T0_im(dc->pc);
1191             } else {
1192                 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1193             }
1194 #else
1195             gen_op_movl_T0_im(dc->pc);
1196 #endif
1197             gen_movl_T0_reg(15);
1198             target += dc->pc;
1199             gen_mov_pc_npc(dc);
1200             dc->npc = target;
1201         }
1202         goto jmp_insn;
1203     case 2:                     /* FPU & Logical Operations */
1204         {
1205             unsigned int xop = GET_FIELD(insn, 7, 12);
1206             if (xop == 0x3a) {  /* generate trap */
1207                 int cond;
1208
1209                 rs1 = GET_FIELD(insn, 13, 17);
1210                 gen_movl_reg_T0(rs1);
1211                 if (IS_IMM) {
1212                     rs2 = GET_FIELD(insn, 25, 31);
1213 #if defined(OPTIM)
1214                     if (rs2 != 0) {
1215 #endif
1216                         gen_movl_simm_T1(rs2);
1217                         gen_op_add_T1_T0();
1218 #if defined(OPTIM)
1219                     }
1220 #endif
1221                 } else {
1222                     rs2 = GET_FIELD(insn, 27, 31);
1223 #if defined(OPTIM)
1224                     if (rs2 != 0) {
1225 #endif
1226                         gen_movl_reg_T1(rs2);
1227                         gen_op_add_T1_T0();
1228 #if defined(OPTIM)
1229                     }
1230 #endif
1231                 }
1232                 cond = GET_FIELD(insn, 3, 6);
1233                 if (cond == 0x8) {
1234                     save_state(dc);
1235                     gen_op_trap_T0();
1236                 } else if (cond != 0) {
1237 #ifdef TARGET_SPARC64
1238                     /* V9 icc/xcc */
1239                     int cc = GET_FIELD_SP(insn, 11, 12);
1240                     flush_T2(dc);
1241                     save_state(dc);
1242                     if (cc == 0)
1243                         gen_cond[0][cond]();
1244                     else if (cc == 2)
1245                         gen_cond[1][cond]();
1246                     else
1247                         goto illegal_insn;
1248 #else
1249                     flush_T2(dc);
1250                     save_state(dc);
1251                     gen_cond[0][cond]();
1252 #endif
1253                     gen_op_trapcc_T0();
1254                 }
1255                 gen_op_next_insn();
1256                 gen_op_movl_T0_0();
1257                 gen_op_exit_tb();
1258                 dc->is_br = 1;
1259                 goto jmp_insn;
1260             } else if (xop == 0x28) {
1261                 rs1 = GET_FIELD(insn, 13, 17);
1262                 switch(rs1) {
1263                 case 0: /* rdy */
1264 #ifndef TARGET_SPARC64
1265                 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1266                                        manual, rdy on the microSPARC
1267                                        II */
1268                 case 0x0f:          /* stbar in the SPARCv8 manual,
1269                                        rdy on the microSPARC II */
1270                 case 0x10 ... 0x1f: /* implementation-dependent in the
1271                                        SPARCv8 manual, rdy on the
1272                                        microSPARC II */
1273 #endif
1274                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1275                     gen_movl_T0_reg(rd);
1276                     break;
1277 #ifdef TARGET_SPARC64
1278                 case 0x2: /* V9 rdccr */
1279                     gen_op_rdccr();
1280                     gen_movl_T0_reg(rd);
1281                     break;
1282                 case 0x3: /* V9 rdasi */
1283                     gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1284                     gen_movl_T0_reg(rd);
1285                     break;
1286                 case 0x4: /* V9 rdtick */
1287                     gen_op_rdtick();
1288                     gen_movl_T0_reg(rd);
1289                     break;
1290                 case 0x5: /* V9 rdpc */
1291                     if (dc->pc == (uint32_t)dc->pc) {
1292                         gen_op_movl_T0_im(dc->pc);
1293                     } else {
1294                         gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1295                     }
1296                     gen_movl_T0_reg(rd);
1297                     break;
1298                 case 0x6: /* V9 rdfprs */
1299                     gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1300                     gen_movl_T0_reg(rd);
1301                     break;
1302                 case 0xf: /* V9 membar */
1303                     break; /* no effect */
1304                 case 0x13: /* Graphics Status */
1305                     if (gen_trap_ifnofpu(dc))
1306                         goto jmp_insn;
1307                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1308                     gen_movl_T0_reg(rd);
1309                     break;
1310                 case 0x17: /* Tick compare */
1311                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1312                     gen_movl_T0_reg(rd);
1313                     break;
1314                 case 0x18: /* System tick */
1315                     gen_op_rdstick();
1316                     gen_movl_T0_reg(rd);
1317                     break;
1318                 case 0x19: /* System tick compare */
1319                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1320                     gen_movl_T0_reg(rd);
1321                     break;
1322                 case 0x10: /* Performance Control */
1323                 case 0x11: /* Performance Instrumentation Counter */
1324                 case 0x12: /* Dispatch Control */
1325                 case 0x14: /* Softint set, WO */
1326                 case 0x15: /* Softint clear, WO */
1327                 case 0x16: /* Softint write */
1328 #endif
1329                 default:
1330                     goto illegal_insn;
1331                 }
1332 #if !defined(CONFIG_USER_ONLY)
1333             } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1334 #ifndef TARGET_SPARC64
1335                 if (!supervisor(dc))
1336                     goto priv_insn;
1337                 gen_op_rdpsr();
1338 #else
1339                 if (!hypervisor(dc))
1340                     goto priv_insn;
1341                 rs1 = GET_FIELD(insn, 13, 17);
1342                 switch (rs1) {
1343                 case 0: // hpstate
1344                     // gen_op_rdhpstate();
1345                     break;
1346                 case 1: // htstate
1347                     // gen_op_rdhtstate();
1348                     break;
1349                 case 3: // hintp
1350                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1351                     break;
1352                 case 5: // htba
1353                     gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1354                     break;
1355                 case 6: // hver
1356                     gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1357                     break;
1358                 case 31: // hstick_cmpr
1359                     gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1360                     break;
1361                 default:
1362                     goto illegal_insn;
1363                 }
1364 #endif
1365                 gen_movl_T0_reg(rd);
1366                 break;
1367             } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1368                 if (!supervisor(dc))
1369                     goto priv_insn;
1370 #ifdef TARGET_SPARC64
1371                 rs1 = GET_FIELD(insn, 13, 17);
1372                 switch (rs1) {
1373                 case 0: // tpc
1374                     gen_op_rdtpc();
1375                     break;
1376                 case 1: // tnpc
1377                     gen_op_rdtnpc();
1378                     break;
1379                 case 2: // tstate
1380                     gen_op_rdtstate();
1381                     break;
1382                 case 3: // tt
1383                     gen_op_rdtt();
1384                     break;
1385                 case 4: // tick
1386                     gen_op_rdtick();
1387                     break;
1388                 case 5: // tba
1389                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1390                     break;
1391                 case 6: // pstate
1392                     gen_op_rdpstate();
1393                     break;
1394                 case 7: // tl
1395                     gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1396                     break;
1397                 case 8: // pil
1398                     gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1399                     break;
1400                 case 9: // cwp
1401                     gen_op_rdcwp();
1402                     break;
1403                 case 10: // cansave
1404                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1405                     break;
1406                 case 11: // canrestore
1407                     gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1408                     break;
1409                 case 12: // cleanwin
1410                     gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1411                     break;
1412                 case 13: // otherwin
1413                     gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1414                     break;
1415                 case 14: // wstate
1416                     gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1417                     break;
1418                 case 16: // UA2005 gl
1419                     gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1420                     break;
1421                 case 26: // UA2005 strand status
1422                     if (!hypervisor(dc))
1423                         goto priv_insn;
1424                     gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1425                     break;
1426                 case 31: // ver
1427                     gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1428                     break;
1429                 case 15: // fq
1430                 default:
1431                     goto illegal_insn;
1432                 }
1433 #else
1434                 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1435 #endif
1436                 gen_movl_T0_reg(rd);
1437                 break;
1438             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1439 #ifdef TARGET_SPARC64
1440                 gen_op_flushw();
1441 #else
1442                 if (!supervisor(dc))
1443                     goto priv_insn;
1444                 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1445                 gen_movl_T0_reg(rd);
1446 #endif
1447                 break;
1448 #endif
1449             } else if (xop == 0x34) {   /* FPU Operations */
1450                 if (gen_trap_ifnofpu(dc))
1451                     goto jmp_insn;
1452                 gen_op_clear_ieee_excp_and_FTT();
1453                 rs1 = GET_FIELD(insn, 13, 17);
1454                 rs2 = GET_FIELD(insn, 27, 31);
1455                 xop = GET_FIELD(insn, 18, 26);
1456                 switch (xop) {
1457                     case 0x1: /* fmovs */
1458                         gen_op_load_fpr_FT0(rs2);
1459                         gen_op_store_FT0_fpr(rd);
1460                         break;
1461                     case 0x5: /* fnegs */
1462                         gen_op_load_fpr_FT1(rs2);
1463                         gen_op_fnegs();
1464                         gen_op_store_FT0_fpr(rd);
1465                         break;
1466                     case 0x9: /* fabss */
1467                         gen_op_load_fpr_FT1(rs2);
1468                         gen_op_fabss();
1469                         gen_op_store_FT0_fpr(rd);
1470                         break;
1471                     case 0x29: /* fsqrts */
1472                         gen_op_load_fpr_FT1(rs2);
1473                         gen_op_fsqrts();
1474                         gen_op_store_FT0_fpr(rd);
1475                         break;
1476                     case 0x2a: /* fsqrtd */
1477                         gen_op_load_fpr_DT1(DFPREG(rs2));
1478                         gen_op_fsqrtd();
1479                         gen_op_store_DT0_fpr(DFPREG(rd));
1480                         break;
1481                     case 0x2b: /* fsqrtq */
1482                         goto nfpu_insn;
1483                     case 0x41:
1484                         gen_op_load_fpr_FT0(rs1);
1485                         gen_op_load_fpr_FT1(rs2);
1486                         gen_op_fadds();
1487                         gen_op_store_FT0_fpr(rd);
1488                         break;
1489                     case 0x42:
1490                         gen_op_load_fpr_DT0(DFPREG(rs1));
1491                         gen_op_load_fpr_DT1(DFPREG(rs2));
1492                         gen_op_faddd();
1493                         gen_op_store_DT0_fpr(DFPREG(rd));
1494                         break;
1495                     case 0x43: /* faddq */
1496                         goto nfpu_insn;
1497                     case 0x45:
1498                         gen_op_load_fpr_FT0(rs1);
1499                         gen_op_load_fpr_FT1(rs2);
1500                         gen_op_fsubs();
1501                         gen_op_store_FT0_fpr(rd);
1502                         break;
1503                     case 0x46:
1504                         gen_op_load_fpr_DT0(DFPREG(rs1));
1505                         gen_op_load_fpr_DT1(DFPREG(rs2));
1506                         gen_op_fsubd();
1507                         gen_op_store_DT0_fpr(DFPREG(rd));
1508                         break;
1509                     case 0x47: /* fsubq */
1510                         goto nfpu_insn;
1511                     case 0x49:
1512                         gen_op_load_fpr_FT0(rs1);
1513                         gen_op_load_fpr_FT1(rs2);
1514                         gen_op_fmuls();
1515                         gen_op_store_FT0_fpr(rd);
1516                         break;
1517                     case 0x4a:
1518                         gen_op_load_fpr_DT0(DFPREG(rs1));
1519                         gen_op_load_fpr_DT1(DFPREG(rs2));
1520                         gen_op_fmuld();
1521                         gen_op_store_DT0_fpr(rd);
1522                         break;
1523                     case 0x4b: /* fmulq */
1524                         goto nfpu_insn;
1525                     case 0x4d:
1526                         gen_op_load_fpr_FT0(rs1);
1527                         gen_op_load_fpr_FT1(rs2);
1528                         gen_op_fdivs();
1529                         gen_op_store_FT0_fpr(rd);
1530                         break;
1531                     case 0x4e:
1532                         gen_op_load_fpr_DT0(DFPREG(rs1));
1533                         gen_op_load_fpr_DT1(DFPREG(rs2));
1534                         gen_op_fdivd();
1535                         gen_op_store_DT0_fpr(DFPREG(rd));
1536                         break;
1537                     case 0x4f: /* fdivq */
1538                         goto nfpu_insn;
1539                     case 0x69:
1540                         gen_op_load_fpr_FT0(rs1);
1541                         gen_op_load_fpr_FT1(rs2);
1542                         gen_op_fsmuld();
1543                         gen_op_store_DT0_fpr(DFPREG(rd));
1544                         break;
1545                     case 0x6e: /* fdmulq */
1546                         goto nfpu_insn;
1547                     case 0xc4:
1548                         gen_op_load_fpr_FT1(rs2);
1549                         gen_op_fitos();
1550                         gen_op_store_FT0_fpr(rd);
1551                         break;
1552                     case 0xc6:
1553                         gen_op_load_fpr_DT1(DFPREG(rs2));
1554                         gen_op_fdtos();
1555                         gen_op_store_FT0_fpr(rd);
1556                         break;
1557                     case 0xc7: /* fqtos */
1558                         goto nfpu_insn;
1559                     case 0xc8:
1560                         gen_op_load_fpr_FT1(rs2);
1561                         gen_op_fitod();
1562                         gen_op_store_DT0_fpr(DFPREG(rd));
1563                         break;
1564                     case 0xc9:
1565                         gen_op_load_fpr_FT1(rs2);
1566                         gen_op_fstod();
1567                         gen_op_store_DT0_fpr(DFPREG(rd));
1568                         break;
1569                     case 0xcb: /* fqtod */
1570                         goto nfpu_insn;
1571                     case 0xcc: /* fitoq */
1572                         goto nfpu_insn;
1573                     case 0xcd: /* fstoq */
1574                         goto nfpu_insn;
1575                     case 0xce: /* fdtoq */
1576                         goto nfpu_insn;
1577                     case 0xd1:
1578                         gen_op_load_fpr_FT1(rs2);
1579                         gen_op_fstoi();
1580                         gen_op_store_FT0_fpr(rd);
1581                         break;
1582                     case 0xd2:
1583                         gen_op_load_fpr_DT1(rs2);
1584                         gen_op_fdtoi();
1585                         gen_op_store_FT0_fpr(rd);
1586                         break;
1587                     case 0xd3: /* fqtoi */
1588                         goto nfpu_insn;
1589 #ifdef TARGET_SPARC64
1590                     case 0x2: /* V9 fmovd */
1591                         gen_op_load_fpr_DT0(DFPREG(rs2));
1592                         gen_op_store_DT0_fpr(DFPREG(rd));
1593                         break;
1594                     case 0x6: /* V9 fnegd */
1595                         gen_op_load_fpr_DT1(DFPREG(rs2));
1596                         gen_op_fnegd();
1597                         gen_op_store_DT0_fpr(DFPREG(rd));
1598                         break;
1599                     case 0xa: /* V9 fabsd */
1600                         gen_op_load_fpr_DT1(DFPREG(rs2));
1601                         gen_op_fabsd();
1602                         gen_op_store_DT0_fpr(DFPREG(rd));
1603                         break;
1604                     case 0x81: /* V9 fstox */
1605                         gen_op_load_fpr_FT1(rs2);
1606                         gen_op_fstox();
1607                         gen_op_store_DT0_fpr(DFPREG(rd));
1608                         break;
1609                     case 0x82: /* V9 fdtox */
1610                         gen_op_load_fpr_DT1(DFPREG(rs2));
1611                         gen_op_fdtox();
1612                         gen_op_store_DT0_fpr(DFPREG(rd));
1613                         break;
1614                     case 0x84: /* V9 fxtos */
1615                         gen_op_load_fpr_DT1(DFPREG(rs2));
1616                         gen_op_fxtos();
1617                         gen_op_store_FT0_fpr(rd);
1618                         break;
1619                     case 0x88: /* V9 fxtod */
1620                         gen_op_load_fpr_DT1(DFPREG(rs2));
1621                         gen_op_fxtod();
1622                         gen_op_store_DT0_fpr(DFPREG(rd));
1623                         break;
1624                     case 0x3: /* V9 fmovq */
1625                     case 0x7: /* V9 fnegq */
1626                     case 0xb: /* V9 fabsq */
1627                     case 0x83: /* V9 fqtox */
1628                     case 0x8c: /* V9 fxtoq */
1629                         goto nfpu_insn;
1630 #endif
1631                     default:
1632                         goto illegal_insn;
1633                 }
1634             } else if (xop == 0x35) {   /* FPU Operations */
1635 #ifdef TARGET_SPARC64
1636                 int cond;
1637 #endif
1638                 if (gen_trap_ifnofpu(dc))
1639                     goto jmp_insn;
1640                 gen_op_clear_ieee_excp_and_FTT();
1641                 rs1 = GET_FIELD(insn, 13, 17);
1642                 rs2 = GET_FIELD(insn, 27, 31);
1643                 xop = GET_FIELD(insn, 18, 26);
1644 #ifdef TARGET_SPARC64
1645                 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1646                     cond = GET_FIELD_SP(insn, 14, 17);
1647                     gen_op_load_fpr_FT0(rd);
1648                     gen_op_load_fpr_FT1(rs2);
1649                     rs1 = GET_FIELD(insn, 13, 17);
1650                     gen_movl_reg_T0(rs1);
1651                     flush_T2(dc);
1652                     gen_cond_reg(cond);
1653                     gen_op_fmovs_cc();
1654                     gen_op_store_FT0_fpr(rd);
1655                     break;
1656                 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1657                     cond = GET_FIELD_SP(insn, 14, 17);
1658                     gen_op_load_fpr_DT0(rd);
1659                     gen_op_load_fpr_DT1(rs2);
1660                     flush_T2(dc);
1661                     rs1 = GET_FIELD(insn, 13, 17);
1662                     gen_movl_reg_T0(rs1);
1663                     gen_cond_reg(cond);
1664                     gen_op_fmovs_cc();
1665                     gen_op_store_DT0_fpr(rd);
1666                     break;
1667                 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1668                     goto nfpu_insn;
1669                 }
1670 #endif
1671                 switch (xop) {
1672 #ifdef TARGET_SPARC64
1673                     case 0x001: /* V9 fmovscc %fcc0 */
1674                         cond = GET_FIELD_SP(insn, 14, 17);
1675                         gen_op_load_fpr_FT0(rd);
1676                         gen_op_load_fpr_FT1(rs2);
1677                         flush_T2(dc);
1678                         gen_fcond[0][cond]();
1679                         gen_op_fmovs_cc();
1680                         gen_op_store_FT0_fpr(rd);
1681                         break;
1682                     case 0x002: /* V9 fmovdcc %fcc0 */
1683                         cond = GET_FIELD_SP(insn, 14, 17);
1684                         gen_op_load_fpr_DT0(rd);
1685                         gen_op_load_fpr_DT1(rs2);
1686                         flush_T2(dc);
1687                         gen_fcond[0][cond]();
1688                         gen_op_fmovd_cc();
1689                         gen_op_store_DT0_fpr(rd);
1690                         break;
1691                     case 0x003: /* V9 fmovqcc %fcc0 */
1692                         goto nfpu_insn;
1693                     case 0x041: /* V9 fmovscc %fcc1 */
1694                         cond = GET_FIELD_SP(insn, 14, 17);
1695                         gen_op_load_fpr_FT0(rd);
1696                         gen_op_load_fpr_FT1(rs2);
1697                         flush_T2(dc);
1698                         gen_fcond[1][cond]();
1699                         gen_op_fmovs_cc();
1700                         gen_op_store_FT0_fpr(rd);
1701                         break;
1702                     case 0x042: /* V9 fmovdcc %fcc1 */
1703                         cond = GET_FIELD_SP(insn, 14, 17);
1704                         gen_op_load_fpr_DT0(rd);
1705                         gen_op_load_fpr_DT1(rs2);
1706                         flush_T2(dc);
1707                         gen_fcond[1][cond]();
1708                         gen_op_fmovd_cc();
1709                         gen_op_store_DT0_fpr(rd);
1710                         break;
1711                     case 0x043: /* V9 fmovqcc %fcc1 */
1712                         goto nfpu_insn;
1713                     case 0x081: /* V9 fmovscc %fcc2 */
1714                         cond = GET_FIELD_SP(insn, 14, 17);
1715                         gen_op_load_fpr_FT0(rd);
1716                         gen_op_load_fpr_FT1(rs2);
1717                         flush_T2(dc);
1718                         gen_fcond[2][cond]();
1719                         gen_op_fmovs_cc();
1720                         gen_op_store_FT0_fpr(rd);
1721                         break;
1722                     case 0x082: /* V9 fmovdcc %fcc2 */
1723                         cond = GET_FIELD_SP(insn, 14, 17);
1724                         gen_op_load_fpr_DT0(rd);
1725                         gen_op_load_fpr_DT1(rs2);
1726                         flush_T2(dc);
1727                         gen_fcond[2][cond]();
1728                         gen_op_fmovd_cc();
1729                         gen_op_store_DT0_fpr(rd);
1730                         break;
1731                     case 0x083: /* V9 fmovqcc %fcc2 */
1732                         goto nfpu_insn;
1733                     case 0x0c1: /* V9 fmovscc %fcc3 */
1734                         cond = GET_FIELD_SP(insn, 14, 17);
1735                         gen_op_load_fpr_FT0(rd);
1736                         gen_op_load_fpr_FT1(rs2);
1737                         flush_T2(dc);
1738                         gen_fcond[3][cond]();
1739                         gen_op_fmovs_cc();
1740                         gen_op_store_FT0_fpr(rd);
1741                         break;
1742                     case 0x0c2: /* V9 fmovdcc %fcc3 */
1743                         cond = GET_FIELD_SP(insn, 14, 17);
1744                         gen_op_load_fpr_DT0(rd);
1745                         gen_op_load_fpr_DT1(rs2);
1746                         flush_T2(dc);
1747                         gen_fcond[3][cond]();
1748                         gen_op_fmovd_cc();
1749                         gen_op_store_DT0_fpr(rd);
1750                         break;
1751                     case 0x0c3: /* V9 fmovqcc %fcc3 */
1752                         goto nfpu_insn;
1753                     case 0x101: /* V9 fmovscc %icc */
1754                         cond = GET_FIELD_SP(insn, 14, 17);
1755                         gen_op_load_fpr_FT0(rd);
1756                         gen_op_load_fpr_FT1(rs2);
1757                         flush_T2(dc);
1758                         gen_cond[0][cond]();
1759                         gen_op_fmovs_cc();
1760                         gen_op_store_FT0_fpr(rd);
1761                         break;
1762                     case 0x102: /* V9 fmovdcc %icc */
1763                         cond = GET_FIELD_SP(insn, 14, 17);
1764                         gen_op_load_fpr_DT0(rd);
1765                         gen_op_load_fpr_DT1(rs2);
1766                         flush_T2(dc);
1767                         gen_cond[0][cond]();
1768                         gen_op_fmovd_cc();
1769                         gen_op_store_DT0_fpr(rd);
1770                         break;
1771                     case 0x103: /* V9 fmovqcc %icc */
1772                         goto nfpu_insn;
1773                     case 0x181: /* V9 fmovscc %xcc */
1774                         cond = GET_FIELD_SP(insn, 14, 17);
1775                         gen_op_load_fpr_FT0(rd);
1776                         gen_op_load_fpr_FT1(rs2);
1777                         flush_T2(dc);
1778                         gen_cond[1][cond]();
1779                         gen_op_fmovs_cc();
1780                         gen_op_store_FT0_fpr(rd);
1781                         break;
1782                     case 0x182: /* V9 fmovdcc %xcc */
1783                         cond = GET_FIELD_SP(insn, 14, 17);
1784                         gen_op_load_fpr_DT0(rd);
1785                         gen_op_load_fpr_DT1(rs2);
1786                         flush_T2(dc);
1787                         gen_cond[1][cond]();
1788                         gen_op_fmovd_cc();
1789                         gen_op_store_DT0_fpr(rd);
1790                         break;
1791                     case 0x183: /* V9 fmovqcc %xcc */
1792                         goto nfpu_insn;
1793 #endif
1794                     case 0x51: /* V9 %fcc */
1795                         gen_op_load_fpr_FT0(rs1);
1796                         gen_op_load_fpr_FT1(rs2);
1797 #ifdef TARGET_SPARC64
1798                         gen_fcmps[rd & 3]();
1799 #else
1800                         gen_op_fcmps();
1801 #endif
1802                         break;
1803                     case 0x52: /* V9 %fcc */
1804                         gen_op_load_fpr_DT0(DFPREG(rs1));
1805                         gen_op_load_fpr_DT1(DFPREG(rs2));
1806 #ifdef TARGET_SPARC64
1807                         gen_fcmpd[rd & 3]();
1808 #else
1809                         gen_op_fcmpd();
1810 #endif
1811                         break;
1812                     case 0x53: /* fcmpq */
1813                         goto nfpu_insn;
1814                     case 0x55: /* fcmpes, V9 %fcc */
1815                         gen_op_load_fpr_FT0(rs1);
1816                         gen_op_load_fpr_FT1(rs2);
1817 #ifdef TARGET_SPARC64
1818                         gen_fcmpes[rd & 3]();
1819 #else
1820                         gen_op_fcmpes();
1821 #endif
1822                         break;
1823                     case 0x56: /* fcmped, V9 %fcc */
1824                         gen_op_load_fpr_DT0(DFPREG(rs1));
1825                         gen_op_load_fpr_DT1(DFPREG(rs2));
1826 #ifdef TARGET_SPARC64
1827                         gen_fcmped[rd & 3]();
1828 #else
1829                         gen_op_fcmped();
1830 #endif
1831                         break;
1832                     case 0x57: /* fcmpeq */
1833                         goto nfpu_insn;
1834                     default:
1835                         goto illegal_insn;
1836                 }
1837 #if defined(OPTIM)
1838             } else if (xop == 0x2) {
1839                 // clr/mov shortcut
1840
1841                 rs1 = GET_FIELD(insn, 13, 17);
1842                 if (rs1 == 0) {
1843                     // or %g0, x, y -> mov T1, x; mov y, T1
1844                     if (IS_IMM) {       /* immediate */
1845                         rs2 = GET_FIELDs(insn, 19, 31);
1846                         gen_movl_simm_T1(rs2);
1847                     } else {            /* register */
1848                         rs2 = GET_FIELD(insn, 27, 31);
1849                         gen_movl_reg_T1(rs2);
1850                     }
1851                     gen_movl_T1_reg(rd);
1852                 } else {
1853                     gen_movl_reg_T0(rs1);
1854                     if (IS_IMM) {       /* immediate */
1855                         // or x, #0, y -> mov T1, x; mov y, T1
1856                         rs2 = GET_FIELDs(insn, 19, 31);
1857                         if (rs2 != 0) {
1858                             gen_movl_simm_T1(rs2);
1859                             gen_op_or_T1_T0();
1860                         }
1861                     } else {            /* register */
1862                         // or x, %g0, y -> mov T1, x; mov y, T1
1863                         rs2 = GET_FIELD(insn, 27, 31);
1864                         if (rs2 != 0) {
1865                             gen_movl_reg_T1(rs2);
1866                             gen_op_or_T1_T0();
1867                         }
1868                     }
1869                     gen_movl_T0_reg(rd);
1870                 }
1871 #endif
1872 #ifdef TARGET_SPARC64
1873             } else if (xop == 0x25) { /* sll, V9 sllx */
1874                 rs1 = GET_FIELD(insn, 13, 17);
1875                 gen_movl_reg_T0(rs1);
1876                 if (IS_IMM) {   /* immediate */
1877                     rs2 = GET_FIELDs(insn, 20, 31);
1878                     gen_movl_simm_T1(rs2);
1879                 } else {                /* register */
1880                     rs2 = GET_FIELD(insn, 27, 31);
1881                     gen_movl_reg_T1(rs2);
1882                 }
1883                 if (insn & (1 << 12))
1884                     gen_op_sllx();
1885                 else
1886                     gen_op_sll();
1887                 gen_movl_T0_reg(rd);
1888             } else if (xop == 0x26) { /* srl, V9 srlx */
1889                 rs1 = GET_FIELD(insn, 13, 17);
1890                 gen_movl_reg_T0(rs1);
1891                 if (IS_IMM) {   /* immediate */
1892                     rs2 = GET_FIELDs(insn, 20, 31);
1893                     gen_movl_simm_T1(rs2);
1894                 } else {                /* register */
1895                     rs2 = GET_FIELD(insn, 27, 31);
1896                     gen_movl_reg_T1(rs2);
1897                 }
1898                 if (insn & (1 << 12))
1899                     gen_op_srlx();
1900                 else
1901                     gen_op_srl();
1902                 gen_movl_T0_reg(rd);
1903             } else if (xop == 0x27) { /* sra, V9 srax */
1904                 rs1 = GET_FIELD(insn, 13, 17);
1905                 gen_movl_reg_T0(rs1);
1906                 if (IS_IMM) {   /* immediate */
1907                     rs2 = GET_FIELDs(insn, 20, 31);
1908                     gen_movl_simm_T1(rs2);
1909                 } else {                /* register */
1910                     rs2 = GET_FIELD(insn, 27, 31);
1911                     gen_movl_reg_T1(rs2);
1912                 }
1913                 if (insn & (1 << 12))
1914                     gen_op_srax();
1915                 else
1916                     gen_op_sra();
1917                 gen_movl_T0_reg(rd);
1918 #endif
1919             } else if (xop < 0x36) {
1920                 rs1 = GET_FIELD(insn, 13, 17);
1921                 gen_movl_reg_T0(rs1);
1922                 if (IS_IMM) {   /* immediate */
1923                     rs2 = GET_FIELDs(insn, 19, 31);
1924                     gen_movl_simm_T1(rs2);
1925                 } else {                /* register */
1926                     rs2 = GET_FIELD(insn, 27, 31);
1927                     gen_movl_reg_T1(rs2);
1928                 }
1929                 if (xop < 0x20) {
1930                     switch (xop & ~0x10) {
1931                     case 0x0:
1932                         if (xop & 0x10)
1933                             gen_op_add_T1_T0_cc();
1934                         else
1935                             gen_op_add_T1_T0();
1936                         break;
1937                     case 0x1:
1938                         gen_op_and_T1_T0();
1939                         if (xop & 0x10)
1940                             gen_op_logic_T0_cc();
1941                         break;
1942                     case 0x2:
1943                         gen_op_or_T1_T0();
1944                         if (xop & 0x10)
1945                             gen_op_logic_T0_cc();
1946                         break;
1947                     case 0x3:
1948                         gen_op_xor_T1_T0();
1949                         if (xop & 0x10)
1950                             gen_op_logic_T0_cc();
1951                         break;
1952                     case 0x4:
1953                         if (xop & 0x10)
1954                             gen_op_sub_T1_T0_cc();
1955                         else
1956                             gen_op_sub_T1_T0();
1957                         break;
1958                     case 0x5:
1959                         gen_op_andn_T1_T0();
1960                         if (xop & 0x10)
1961                             gen_op_logic_T0_cc();
1962                         break;
1963                     case 0x6:
1964                         gen_op_orn_T1_T0();
1965                         if (xop & 0x10)
1966                             gen_op_logic_T0_cc();
1967                         break;
1968                     case 0x7:
1969                         gen_op_xnor_T1_T0();
1970                         if (xop & 0x10)
1971                             gen_op_logic_T0_cc();
1972                         break;
1973                     case 0x8:
1974                         if (xop & 0x10)
1975                             gen_op_addx_T1_T0_cc();
1976                         else
1977                             gen_op_addx_T1_T0();
1978                         break;
1979 #ifdef TARGET_SPARC64
1980                     case 0x9: /* V9 mulx */
1981                         gen_op_mulx_T1_T0();
1982                         break;
1983 #endif
1984                     case 0xa:
1985                         gen_op_umul_T1_T0();
1986                         if (xop & 0x10)
1987                             gen_op_logic_T0_cc();
1988                         break;
1989                     case 0xb:
1990                         gen_op_smul_T1_T0();
1991                         if (xop & 0x10)
1992                             gen_op_logic_T0_cc();
1993                         break;
1994                     case 0xc:
1995                         if (xop & 0x10)
1996                             gen_op_subx_T1_T0_cc();
1997                         else
1998                             gen_op_subx_T1_T0();
1999                         break;
2000 #ifdef TARGET_SPARC64
2001                     case 0xd: /* V9 udivx */
2002                         gen_op_udivx_T1_T0();
2003                         break;
2004 #endif
2005                     case 0xe:
2006                         gen_op_udiv_T1_T0();
2007                         if (xop & 0x10)
2008                             gen_op_div_cc();
2009                         break;
2010                     case 0xf:
2011                         gen_op_sdiv_T1_T0();
2012                         if (xop & 0x10)
2013                             gen_op_div_cc();
2014                         break;
2015                     default:
2016                         goto illegal_insn;
2017                     }
2018                     gen_movl_T0_reg(rd);
2019                 } else {
2020                     switch (xop) {
2021                     case 0x20: /* taddcc */
2022                         gen_op_tadd_T1_T0_cc();
2023                         gen_movl_T0_reg(rd);
2024                         break;
2025                     case 0x21: /* tsubcc */
2026                         gen_op_tsub_T1_T0_cc();
2027                         gen_movl_T0_reg(rd);
2028                         break;
2029                     case 0x22: /* taddcctv */
2030                         gen_op_tadd_T1_T0_ccTV();
2031                         gen_movl_T0_reg(rd);
2032                         break;
2033                     case 0x23: /* tsubcctv */
2034                         gen_op_tsub_T1_T0_ccTV();
2035                         gen_movl_T0_reg(rd);
2036                         break;
2037                     case 0x24: /* mulscc */
2038                         gen_op_mulscc_T1_T0();
2039                         gen_movl_T0_reg(rd);
2040                         break;
2041 #ifndef TARGET_SPARC64
2042                     case 0x25:  /* sll */
2043                         gen_op_sll();
2044                         gen_movl_T0_reg(rd);
2045                         break;
2046                     case 0x26:  /* srl */
2047                         gen_op_srl();
2048                         gen_movl_T0_reg(rd);
2049                         break;
2050                     case 0x27:  /* sra */
2051                         gen_op_sra();
2052                         gen_movl_T0_reg(rd);
2053                         break;
2054 #endif
2055                     case 0x30:
2056                         {
2057                             switch(rd) {
2058                             case 0: /* wry */
2059                                 gen_op_xor_T1_T0();
2060                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
2061                                 break;
2062 #ifndef TARGET_SPARC64
2063                             case 0x01 ... 0x0f: /* undefined in the
2064                                                    SPARCv8 manual, nop
2065                                                    on the microSPARC
2066                                                    II */
2067                             case 0x10 ... 0x1f: /* implementation-dependent
2068                                                    in the SPARCv8
2069                                                    manual, nop on the
2070                                                    microSPARC II */
2071                                 break;
2072 #else
2073                             case 0x2: /* V9 wrccr */
2074                                 gen_op_xor_T1_T0();
2075                                 gen_op_wrccr();
2076                                 break;
2077                             case 0x3: /* V9 wrasi */
2078                                 gen_op_xor_T1_T0();
2079                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2080                                 break;
2081                             case 0x6: /* V9 wrfprs */
2082                                 gen_op_xor_T1_T0();
2083                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
2084                                 save_state(dc);
2085                                 gen_op_next_insn();
2086                                 gen_op_movl_T0_0();
2087                                 gen_op_exit_tb();
2088                                 dc->is_br = 1;
2089                                 break;
2090                             case 0xf: /* V9 sir, nop if user */
2091 #if !defined(CONFIG_USER_ONLY)
2092                                 if (supervisor(dc))
2093                                     gen_op_sir();
2094 #endif
2095                                 break;
2096                             case 0x13: /* Graphics Status */
2097                                 if (gen_trap_ifnofpu(dc))
2098                                     goto jmp_insn;
2099                                 gen_op_xor_T1_T0();
2100                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2101                                 break;
2102                             case 0x17: /* Tick compare */
2103 #if !defined(CONFIG_USER_ONLY)
2104                                 if (!supervisor(dc))
2105                                     goto illegal_insn;
2106 #endif
2107                                 gen_op_xor_T1_T0();
2108                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2109                                 gen_op_wrtick_cmpr();
2110                                 break;
2111                             case 0x18: /* System tick */
2112 #if !defined(CONFIG_USER_ONLY)
2113                                 if (!supervisor(dc))
2114                                     goto illegal_insn;
2115 #endif
2116                                 gen_op_xor_T1_T0();
2117                                 gen_op_wrstick();
2118                                 break;
2119                             case 0x19: /* System tick compare */
2120 #if !defined(CONFIG_USER_ONLY)
2121                                 if (!supervisor(dc))
2122                                     goto illegal_insn;
2123 #endif
2124                                 gen_op_xor_T1_T0();
2125                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2126                                 gen_op_wrstick_cmpr();
2127                                 break;
2128
2129                             case 0x10: /* Performance Control */
2130                             case 0x11: /* Performance Instrumentation Counter */
2131                             case 0x12: /* Dispatch Control */
2132                             case 0x14: /* Softint set */
2133                             case 0x15: /* Softint clear */
2134                             case 0x16: /* Softint write */
2135 #endif
2136                             default:
2137                                 goto illegal_insn;
2138                             }
2139                         }
2140                         break;
2141 #if !defined(CONFIG_USER_ONLY)
2142                     case 0x31: /* wrpsr, V9 saved, restored */
2143                         {
2144                             if (!supervisor(dc))
2145                                 goto priv_insn;
2146 #ifdef TARGET_SPARC64
2147                             switch (rd) {
2148                             case 0:
2149                                 gen_op_saved();
2150                                 break;
2151                             case 1:
2152                                 gen_op_restored();
2153                                 break;
2154                             case 2: /* UA2005 allclean */
2155                             case 3: /* UA2005 otherw */
2156                             case 4: /* UA2005 normalw */
2157                             case 5: /* UA2005 invalw */
2158                                 // XXX
2159                             default:
2160                                 goto illegal_insn;
2161                             }
2162 #else
2163                             gen_op_xor_T1_T0();
2164                             gen_op_wrpsr();
2165                             save_state(dc);
2166                             gen_op_next_insn();
2167                             gen_op_movl_T0_0();
2168                             gen_op_exit_tb();
2169                             dc->is_br = 1;
2170 #endif
2171                         }
2172                         break;
2173                     case 0x32: /* wrwim, V9 wrpr */
2174                         {
2175                             if (!supervisor(dc))
2176                                 goto priv_insn;
2177                             gen_op_xor_T1_T0();
2178 #ifdef TARGET_SPARC64
2179                             switch (rd) {
2180                             case 0: // tpc
2181                                 gen_op_wrtpc();
2182                                 break;
2183                             case 1: // tnpc
2184                                 gen_op_wrtnpc();
2185                                 break;
2186                             case 2: // tstate
2187                                 gen_op_wrtstate();
2188                                 break;
2189                             case 3: // tt
2190                                 gen_op_wrtt();
2191                                 break;
2192                             case 4: // tick
2193                                 gen_op_wrtick();
2194                                 break;
2195                             case 5: // tba
2196                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2197                                 break;
2198                             case 6: // pstate
2199                                 gen_op_wrpstate();
2200                                 save_state(dc);
2201                                 gen_op_next_insn();
2202                                 gen_op_movl_T0_0();
2203                                 gen_op_exit_tb();
2204                                 dc->is_br = 1;
2205                                 break;
2206                             case 7: // tl
2207                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2208                                 break;
2209                             case 8: // pil
2210                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2211                                 break;
2212                             case 9: // cwp
2213                                 gen_op_wrcwp();
2214                                 break;
2215                             case 10: // cansave
2216                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2217                                 break;
2218                             case 11: // canrestore
2219                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2220                                 break;
2221                             case 12: // cleanwin
2222                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2223                                 break;
2224                             case 13: // otherwin
2225                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2226                                 break;
2227                             case 14: // wstate
2228                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2229                                 break;
2230                             case 16: // UA2005 gl
2231                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2232                                 break;
2233                             case 26: // UA2005 strand status
2234                                 if (!hypervisor(dc))
2235                                     goto priv_insn;
2236                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2237                                 break;
2238                             default:
2239                                 goto illegal_insn;
2240                             }
2241 #else
2242                             gen_op_wrwim();
2243 #endif
2244                         }
2245                         break;
2246                     case 0x33: /* wrtbr, UA2005 wrhpr */
2247                         {
2248 #ifndef TARGET_SPARC64
2249                             if (!supervisor(dc))
2250                                 goto priv_insn;
2251                             gen_op_xor_T1_T0();
2252                             gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2253 #else
2254                             if (!hypervisor(dc))
2255                                 goto priv_insn;
2256                             gen_op_xor_T1_T0();
2257                             switch (rd) {
2258                             case 0: // hpstate
2259                                 // XXX gen_op_wrhpstate();
2260                                 save_state(dc);
2261                                 gen_op_next_insn();
2262                                 gen_op_movl_T0_0();
2263                                 gen_op_exit_tb();
2264                                 dc->is_br = 1;
2265                                 break;
2266                             case 1: // htstate
2267                                 // XXX gen_op_wrhtstate();
2268                                 break;
2269                             case 3: // hintp
2270                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2271                                 break;
2272                             case 5: // htba
2273                                 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2274                                 break;
2275                             case 31: // hstick_cmpr
2276                                 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2277                                 gen_op_wrhstick_cmpr();
2278                                 break;
2279                             case 6: // hver readonly
2280                             default:
2281                                 goto illegal_insn;
2282                             }
2283 #endif
2284                         }
2285                         break;
2286 #endif
2287 #ifdef TARGET_SPARC64
2288                     case 0x2c: /* V9 movcc */
2289                         {
2290                             int cc = GET_FIELD_SP(insn, 11, 12);
2291                             int cond = GET_FIELD_SP(insn, 14, 17);
2292                             if (IS_IMM) {       /* immediate */
2293                                 rs2 = GET_FIELD_SPs(insn, 0, 10);
2294                                 gen_movl_simm_T1(rs2);
2295                             }
2296                             else {
2297                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2298                                 gen_movl_reg_T1(rs2);
2299                             }
2300                             gen_movl_reg_T0(rd);
2301                             flush_T2(dc);
2302                             if (insn & (1 << 18)) {
2303                                 if (cc == 0)
2304                                     gen_cond[0][cond]();
2305                                 else if (cc == 2)
2306                                     gen_cond[1][cond]();
2307                                 else
2308                                     goto illegal_insn;
2309                             } else {
2310                                 gen_fcond[cc][cond]();
2311                             }
2312                             gen_op_mov_cc();
2313                             gen_movl_T0_reg(rd);
2314                             break;
2315                         }
2316                     case 0x2d: /* V9 sdivx */
2317                         gen_op_sdivx_T1_T0();
2318                         gen_movl_T0_reg(rd);
2319                         break;
2320                     case 0x2e: /* V9 popc */
2321                         {
2322                             if (IS_IMM) {       /* immediate */
2323                                 rs2 = GET_FIELD_SPs(insn, 0, 12);
2324                                 gen_movl_simm_T1(rs2);
2325                                 // XXX optimize: popc(constant)
2326                             }
2327                             else {
2328                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2329                                 gen_movl_reg_T1(rs2);
2330                             }
2331                             gen_op_popc();
2332                             gen_movl_T0_reg(rd);
2333                         }
2334                     case 0x2f: /* V9 movr */
2335                         {
2336                             int cond = GET_FIELD_SP(insn, 10, 12);
2337                             rs1 = GET_FIELD(insn, 13, 17);
2338                             flush_T2(dc);
2339                             gen_movl_reg_T0(rs1);
2340                             gen_cond_reg(cond);
2341                             if (IS_IMM) {       /* immediate */
2342                                 rs2 = GET_FIELD_SPs(insn, 0, 9);
2343                                 gen_movl_simm_T1(rs2);
2344                             }
2345                             else {
2346                                 rs2 = GET_FIELD_SP(insn, 0, 4);
2347                                 gen_movl_reg_T1(rs2);
2348                             }
2349                             gen_movl_reg_T0(rd);
2350                             gen_op_mov_cc();
2351                             gen_movl_T0_reg(rd);
2352                             break;
2353                         }
2354 #endif
2355                     default:
2356                         goto illegal_insn;
2357                     }
2358                 }
2359             } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2360 #ifdef TARGET_SPARC64
2361                 int opf = GET_FIELD_SP(insn, 5, 13);
2362                 rs1 = GET_FIELD(insn, 13, 17);
2363                 rs2 = GET_FIELD(insn, 27, 31);
2364                 if (gen_trap_ifnofpu(dc))
2365                     goto jmp_insn;
2366
2367                 switch (opf) {
2368                 case 0x000: /* VIS I edge8cc */
2369                 case 0x001: /* VIS II edge8n */
2370                 case 0x002: /* VIS I edge8lcc */
2371                 case 0x003: /* VIS II edge8ln */
2372                 case 0x004: /* VIS I edge16cc */
2373                 case 0x005: /* VIS II edge16n */
2374                 case 0x006: /* VIS I edge16lcc */
2375                 case 0x007: /* VIS II edge16ln */
2376                 case 0x008: /* VIS I edge32cc */
2377                 case 0x009: /* VIS II edge32n */
2378                 case 0x00a: /* VIS I edge32lcc */
2379                 case 0x00b: /* VIS II edge32ln */
2380                     // XXX
2381                     goto illegal_insn;
2382                 case 0x010: /* VIS I array8 */
2383                     gen_movl_reg_T0(rs1);
2384                     gen_movl_reg_T1(rs2);
2385                     gen_op_array8();
2386                     gen_movl_T0_reg(rd);
2387                     break;
2388                 case 0x012: /* VIS I array16 */
2389                     gen_movl_reg_T0(rs1);
2390                     gen_movl_reg_T1(rs2);
2391                     gen_op_array16();
2392                     gen_movl_T0_reg(rd);
2393                     break;
2394                 case 0x014: /* VIS I array32 */
2395                     gen_movl_reg_T0(rs1);
2396                     gen_movl_reg_T1(rs2);
2397                     gen_op_array32();
2398                     gen_movl_T0_reg(rd);
2399                     break;
2400                 case 0x018: /* VIS I alignaddr */
2401                     gen_movl_reg_T0(rs1);
2402                     gen_movl_reg_T1(rs2);
2403                     gen_op_alignaddr();
2404                     gen_movl_T0_reg(rd);
2405                     break;
2406                 case 0x019: /* VIS II bmask */
2407                 case 0x01a: /* VIS I alignaddrl */
2408                     // XXX
2409                     goto illegal_insn;
2410                 case 0x020: /* VIS I fcmple16 */
2411                     gen_op_load_fpr_DT0(rs1);
2412                     gen_op_load_fpr_DT1(rs2);
2413                     gen_op_fcmple16();
2414                     gen_op_store_DT0_fpr(rd);
2415                     break;
2416                 case 0x022: /* VIS I fcmpne16 */
2417                     gen_op_load_fpr_DT0(rs1);
2418                     gen_op_load_fpr_DT1(rs2);
2419                     gen_op_fcmpne16();
2420                     gen_op_store_DT0_fpr(rd);
2421                     break;
2422                 case 0x024: /* VIS I fcmple32 */
2423                     gen_op_load_fpr_DT0(rs1);
2424                     gen_op_load_fpr_DT1(rs2);
2425                     gen_op_fcmple32();
2426                     gen_op_store_DT0_fpr(rd);
2427                     break;
2428                 case 0x026: /* VIS I fcmpne32 */
2429                     gen_op_load_fpr_DT0(rs1);
2430                     gen_op_load_fpr_DT1(rs2);
2431                     gen_op_fcmpne32();
2432                     gen_op_store_DT0_fpr(rd);
2433                     break;
2434                 case 0x028: /* VIS I fcmpgt16 */
2435                     gen_op_load_fpr_DT0(rs1);
2436                     gen_op_load_fpr_DT1(rs2);
2437                     gen_op_fcmpgt16();
2438                     gen_op_store_DT0_fpr(rd);
2439                     break;
2440                 case 0x02a: /* VIS I fcmpeq16 */
2441                     gen_op_load_fpr_DT0(rs1);
2442                     gen_op_load_fpr_DT1(rs2);
2443                     gen_op_fcmpeq16();
2444                     gen_op_store_DT0_fpr(rd);
2445                     break;
2446                 case 0x02c: /* VIS I fcmpgt32 */
2447                     gen_op_load_fpr_DT0(rs1);
2448                     gen_op_load_fpr_DT1(rs2);
2449                     gen_op_fcmpgt32();
2450                     gen_op_store_DT0_fpr(rd);
2451                     break;
2452                 case 0x02e: /* VIS I fcmpeq32 */
2453                     gen_op_load_fpr_DT0(rs1);
2454                     gen_op_load_fpr_DT1(rs2);
2455                     gen_op_fcmpeq32();
2456                     gen_op_store_DT0_fpr(rd);
2457                     break;
2458                 case 0x031: /* VIS I fmul8x16 */
2459                     gen_op_load_fpr_DT0(rs1);
2460                     gen_op_load_fpr_DT1(rs2);
2461                     gen_op_fmul8x16();
2462                     gen_op_store_DT0_fpr(rd);
2463                     break;
2464                 case 0x033: /* VIS I fmul8x16au */
2465                     gen_op_load_fpr_DT0(rs1);
2466                     gen_op_load_fpr_DT1(rs2);
2467                     gen_op_fmul8x16au();
2468                     gen_op_store_DT0_fpr(rd);
2469                     break;
2470                 case 0x035: /* VIS I fmul8x16al */
2471                     gen_op_load_fpr_DT0(rs1);
2472                     gen_op_load_fpr_DT1(rs2);
2473                     gen_op_fmul8x16al();
2474                     gen_op_store_DT0_fpr(rd);
2475                     break;
2476                 case 0x036: /* VIS I fmul8sux16 */
2477                     gen_op_load_fpr_DT0(rs1);
2478                     gen_op_load_fpr_DT1(rs2);
2479                     gen_op_fmul8sux16();
2480                     gen_op_store_DT0_fpr(rd);
2481                     break;
2482                 case 0x037: /* VIS I fmul8ulx16 */
2483                     gen_op_load_fpr_DT0(rs1);
2484                     gen_op_load_fpr_DT1(rs2);
2485                     gen_op_fmul8ulx16();
2486                     gen_op_store_DT0_fpr(rd);
2487                     break;
2488                 case 0x038: /* VIS I fmuld8sux16 */
2489                     gen_op_load_fpr_DT0(rs1);
2490                     gen_op_load_fpr_DT1(rs2);
2491                     gen_op_fmuld8sux16();
2492                     gen_op_store_DT0_fpr(rd);
2493                     break;
2494                 case 0x039: /* VIS I fmuld8ulx16 */
2495                     gen_op_load_fpr_DT0(rs1);
2496                     gen_op_load_fpr_DT1(rs2);
2497                     gen_op_fmuld8ulx16();
2498                     gen_op_store_DT0_fpr(rd);
2499                     break;
2500                 case 0x03a: /* VIS I fpack32 */
2501                 case 0x03b: /* VIS I fpack16 */
2502                 case 0x03d: /* VIS I fpackfix */
2503                 case 0x03e: /* VIS I pdist */
2504                     // XXX
2505                     goto illegal_insn;
2506                 case 0x048: /* VIS I faligndata */
2507                     gen_op_load_fpr_DT0(rs1);
2508                     gen_op_load_fpr_DT1(rs2);
2509                     gen_op_faligndata();
2510                     gen_op_store_DT0_fpr(rd);
2511                     break;
2512                 case 0x04b: /* VIS I fpmerge */
2513                     gen_op_load_fpr_DT0(rs1);
2514                     gen_op_load_fpr_DT1(rs2);
2515                     gen_op_fpmerge();
2516                     gen_op_store_DT0_fpr(rd);
2517                     break;
2518                 case 0x04c: /* VIS II bshuffle */
2519                     // XXX
2520                     goto illegal_insn;
2521                 case 0x04d: /* VIS I fexpand */
2522                     gen_op_load_fpr_DT0(rs1);
2523                     gen_op_load_fpr_DT1(rs2);
2524                     gen_op_fexpand();
2525                     gen_op_store_DT0_fpr(rd);
2526                     break;
2527                 case 0x050: /* VIS I fpadd16 */
2528                     gen_op_load_fpr_DT0(rs1);
2529                     gen_op_load_fpr_DT1(rs2);
2530                     gen_op_fpadd16();
2531                     gen_op_store_DT0_fpr(rd);
2532                     break;
2533                 case 0x051: /* VIS I fpadd16s */
2534                     gen_op_load_fpr_FT0(rs1);
2535                     gen_op_load_fpr_FT1(rs2);
2536                     gen_op_fpadd16s();
2537                     gen_op_store_FT0_fpr(rd);
2538                     break;
2539                 case 0x052: /* VIS I fpadd32 */
2540                     gen_op_load_fpr_DT0(rs1);
2541                     gen_op_load_fpr_DT1(rs2);
2542                     gen_op_fpadd32();
2543                     gen_op_store_DT0_fpr(rd);
2544                     break;
2545                 case 0x053: /* VIS I fpadd32s */
2546                     gen_op_load_fpr_FT0(rs1);
2547                     gen_op_load_fpr_FT1(rs2);
2548                     gen_op_fpadd32s();
2549                     gen_op_store_FT0_fpr(rd);
2550                     break;
2551                 case 0x054: /* VIS I fpsub16 */
2552                     gen_op_load_fpr_DT0(rs1);
2553                     gen_op_load_fpr_DT1(rs2);
2554                     gen_op_fpsub16();
2555                     gen_op_store_DT0_fpr(rd);
2556                     break;
2557                 case 0x055: /* VIS I fpsub16s */
2558                     gen_op_load_fpr_FT0(rs1);
2559                     gen_op_load_fpr_FT1(rs2);
2560                     gen_op_fpsub16s();
2561                     gen_op_store_FT0_fpr(rd);
2562                     break;
2563                 case 0x056: /* VIS I fpsub32 */
2564                     gen_op_load_fpr_DT0(rs1);
2565                     gen_op_load_fpr_DT1(rs2);
2566                     gen_op_fpadd32();
2567                     gen_op_store_DT0_fpr(rd);
2568                     break;
2569                 case 0x057: /* VIS I fpsub32s */
2570                     gen_op_load_fpr_FT0(rs1);
2571                     gen_op_load_fpr_FT1(rs2);
2572                     gen_op_fpsub32s();
2573                     gen_op_store_FT0_fpr(rd);
2574                     break;
2575                 case 0x060: /* VIS I fzero */
2576                     gen_op_movl_DT0_0();
2577                     gen_op_store_DT0_fpr(rd);
2578                     break;
2579                 case 0x061: /* VIS I fzeros */
2580                     gen_op_movl_FT0_0();
2581                     gen_op_store_FT0_fpr(rd);
2582                     break;
2583                 case 0x062: /* VIS I fnor */
2584                     gen_op_load_fpr_DT0(rs1);
2585                     gen_op_load_fpr_DT1(rs2);
2586                     gen_op_fnor();
2587                     gen_op_store_DT0_fpr(rd);
2588                     break;
2589                 case 0x063: /* VIS I fnors */
2590                     gen_op_load_fpr_FT0(rs1);
2591                     gen_op_load_fpr_FT1(rs2);
2592                     gen_op_fnors();
2593                     gen_op_store_FT0_fpr(rd);
2594                     break;
2595                 case 0x064: /* VIS I fandnot2 */
2596                     gen_op_load_fpr_DT1(rs1);
2597                     gen_op_load_fpr_DT0(rs2);
2598                     gen_op_fandnot();
2599                     gen_op_store_DT0_fpr(rd);
2600                     break;
2601                 case 0x065: /* VIS I fandnot2s */
2602                     gen_op_load_fpr_FT1(rs1);
2603                     gen_op_load_fpr_FT0(rs2);
2604                     gen_op_fandnots();
2605                     gen_op_store_FT0_fpr(rd);
2606                     break;
2607                 case 0x066: /* VIS I fnot2 */
2608                     gen_op_load_fpr_DT1(rs2);
2609                     gen_op_fnot();
2610                     gen_op_store_DT0_fpr(rd);
2611                     break;
2612                 case 0x067: /* VIS I fnot2s */
2613                     gen_op_load_fpr_FT1(rs2);
2614                     gen_op_fnot();
2615                     gen_op_store_FT0_fpr(rd);
2616                     break;
2617                 case 0x068: /* VIS I fandnot1 */
2618                     gen_op_load_fpr_DT0(rs1);
2619                     gen_op_load_fpr_DT1(rs2);
2620                     gen_op_fandnot();
2621                     gen_op_store_DT0_fpr(rd);
2622                     break;
2623                 case 0x069: /* VIS I fandnot1s */
2624                     gen_op_load_fpr_FT0(rs1);
2625                     gen_op_load_fpr_FT1(rs2);
2626                     gen_op_fandnots();
2627                     gen_op_store_FT0_fpr(rd);
2628                     break;
2629                 case 0x06a: /* VIS I fnot1 */
2630                     gen_op_load_fpr_DT1(rs1);
2631                     gen_op_fnot();
2632                     gen_op_store_DT0_fpr(rd);
2633                     break;
2634                 case 0x06b: /* VIS I fnot1s */
2635                     gen_op_load_fpr_FT1(rs1);
2636                     gen_op_fnot();
2637                     gen_op_store_FT0_fpr(rd);
2638                     break;
2639                 case 0x06c: /* VIS I fxor */
2640                     gen_op_load_fpr_DT0(rs1);
2641                     gen_op_load_fpr_DT1(rs2);
2642                     gen_op_fxor();
2643                     gen_op_store_DT0_fpr(rd);
2644                     break;
2645                 case 0x06d: /* VIS I fxors */
2646                     gen_op_load_fpr_FT0(rs1);
2647                     gen_op_load_fpr_FT1(rs2);
2648                     gen_op_fxors();
2649                     gen_op_store_FT0_fpr(rd);
2650                     break;
2651                 case 0x06e: /* VIS I fnand */
2652                     gen_op_load_fpr_DT0(rs1);
2653                     gen_op_load_fpr_DT1(rs2);
2654                     gen_op_fnand();
2655                     gen_op_store_DT0_fpr(rd);
2656                     break;
2657                 case 0x06f: /* VIS I fnands */
2658                     gen_op_load_fpr_FT0(rs1);
2659                     gen_op_load_fpr_FT1(rs2);
2660                     gen_op_fnands();
2661                     gen_op_store_FT0_fpr(rd);
2662                     break;
2663                 case 0x070: /* VIS I fand */
2664                     gen_op_load_fpr_DT0(rs1);
2665                     gen_op_load_fpr_DT1(rs2);
2666                     gen_op_fand();
2667                     gen_op_store_DT0_fpr(rd);
2668                     break;
2669                 case 0x071: /* VIS I fands */
2670                     gen_op_load_fpr_FT0(rs1);
2671                     gen_op_load_fpr_FT1(rs2);
2672                     gen_op_fands();
2673                     gen_op_store_FT0_fpr(rd);
2674                     break;
2675                 case 0x072: /* VIS I fxnor */
2676                     gen_op_load_fpr_DT0(rs1);
2677                     gen_op_load_fpr_DT1(rs2);
2678                     gen_op_fxnor();
2679                     gen_op_store_DT0_fpr(rd);
2680                     break;
2681                 case 0x073: /* VIS I fxnors */
2682                     gen_op_load_fpr_FT0(rs1);
2683                     gen_op_load_fpr_FT1(rs2);
2684                     gen_op_fxnors();
2685                     gen_op_store_FT0_fpr(rd);
2686                     break;
2687                 case 0x074: /* VIS I fsrc1 */
2688                     gen_op_load_fpr_DT0(rs1);
2689                     gen_op_store_DT0_fpr(rd);
2690                     break;
2691                 case 0x075: /* VIS I fsrc1s */
2692                     gen_op_load_fpr_FT0(rs1);
2693                     gen_op_store_FT0_fpr(rd);
2694                     break;
2695                 case 0x076: /* VIS I fornot2 */
2696                     gen_op_load_fpr_DT1(rs1);
2697                     gen_op_load_fpr_DT0(rs2);
2698                     gen_op_fornot();
2699                     gen_op_store_DT0_fpr(rd);
2700                     break;
2701                 case 0x077: /* VIS I fornot2s */
2702                     gen_op_load_fpr_FT1(rs1);
2703                     gen_op_load_fpr_FT0(rs2);
2704                     gen_op_fornots();
2705                     gen_op_store_FT0_fpr(rd);
2706                     break;
2707                 case 0x078: /* VIS I fsrc2 */
2708                     gen_op_load_fpr_DT0(rs2);
2709                     gen_op_store_DT0_fpr(rd);
2710                     break;
2711                 case 0x079: /* VIS I fsrc2s */
2712                     gen_op_load_fpr_FT0(rs2);
2713                     gen_op_store_FT0_fpr(rd);
2714                     break;
2715                 case 0x07a: /* VIS I fornot1 */
2716                     gen_op_load_fpr_DT0(rs1);
2717                     gen_op_load_fpr_DT1(rs2);
2718                     gen_op_fornot();
2719                     gen_op_store_DT0_fpr(rd);
2720                     break;
2721                 case 0x07b: /* VIS I fornot1s */
2722                     gen_op_load_fpr_FT0(rs1);
2723                     gen_op_load_fpr_FT1(rs2);
2724                     gen_op_fornots();
2725                     gen_op_store_FT0_fpr(rd);
2726                     break;
2727                 case 0x07c: /* VIS I for */
2728                     gen_op_load_fpr_DT0(rs1);
2729                     gen_op_load_fpr_DT1(rs2);
2730                     gen_op_for();
2731                     gen_op_store_DT0_fpr(rd);
2732                     break;
2733                 case 0x07d: /* VIS I fors */
2734                     gen_op_load_fpr_FT0(rs1);
2735                     gen_op_load_fpr_FT1(rs2);
2736                     gen_op_fors();
2737                     gen_op_store_FT0_fpr(rd);
2738                     break;
2739                 case 0x07e: /* VIS I fone */
2740                     gen_op_movl_DT0_1();
2741                     gen_op_store_DT0_fpr(rd);
2742                     break;
2743                 case 0x07f: /* VIS I fones */
2744                     gen_op_movl_FT0_1();
2745                     gen_op_store_FT0_fpr(rd);
2746                     break;
2747                 case 0x080: /* VIS I shutdown */
2748                 case 0x081: /* VIS II siam */
2749                     // XXX
2750                     goto illegal_insn;
2751                 default:
2752                     goto illegal_insn;
2753                 }
2754 #else
2755                 goto ncp_insn;
2756 #endif
2757             } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2758 #ifdef TARGET_SPARC64
2759                 goto illegal_insn;
2760 #else
2761                 goto ncp_insn;
2762 #endif
2763 #ifdef TARGET_SPARC64
2764             } else if (xop == 0x39) { /* V9 return */
2765                 rs1 = GET_FIELD(insn, 13, 17);
2766                 save_state(dc);
2767                 gen_movl_reg_T0(rs1);
2768                 if (IS_IMM) {   /* immediate */
2769                     rs2 = GET_FIELDs(insn, 19, 31);
2770 #if defined(OPTIM)
2771                     if (rs2) {
2772 #endif
2773                         gen_movl_simm_T1(rs2);
2774                         gen_op_add_T1_T0();
2775 #if defined(OPTIM)
2776                     }
2777 #endif
2778                 } else {                /* register */
2779                     rs2 = GET_FIELD(insn, 27, 31);
2780 #if defined(OPTIM)
2781                     if (rs2) {
2782 #endif
2783                         gen_movl_reg_T1(rs2);
2784                         gen_op_add_T1_T0();
2785 #if defined(OPTIM)
2786                     }
2787 #endif
2788                 }
2789                 gen_op_restore();
2790                 gen_mov_pc_npc(dc);
2791                 gen_op_check_align_T0_3();
2792                 gen_op_movl_npc_T0();
2793                 dc->npc = DYNAMIC_PC;
2794                 goto jmp_insn;
2795 #endif
2796             } else {
2797                 rs1 = GET_FIELD(insn, 13, 17);
2798                 gen_movl_reg_T0(rs1);
2799                 if (IS_IMM) {   /* immediate */
2800                     rs2 = GET_FIELDs(insn, 19, 31);
2801 #if defined(OPTIM)
2802                     if (rs2) {
2803 #endif
2804                         gen_movl_simm_T1(rs2);
2805                         gen_op_add_T1_T0();
2806 #if defined(OPTIM)
2807                     }
2808 #endif
2809                 } else {                /* register */
2810                     rs2 = GET_FIELD(insn, 27, 31);
2811 #if defined(OPTIM)
2812                     if (rs2) {
2813 #endif
2814                         gen_movl_reg_T1(rs2);
2815                         gen_op_add_T1_T0();
2816 #if defined(OPTIM)
2817                     }
2818 #endif
2819                 }
2820                 switch (xop) {
2821                 case 0x38:      /* jmpl */
2822                     {
2823                         if (rd != 0) {
2824 #ifdef TARGET_SPARC64
2825                             if (dc->pc == (uint32_t)dc->pc) {
2826                                 gen_op_movl_T1_im(dc->pc);
2827                             } else {
2828                                 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2829                             }
2830 #else
2831                             gen_op_movl_T1_im(dc->pc);
2832 #endif
2833                             gen_movl_T1_reg(rd);
2834                         }
2835                         gen_mov_pc_npc(dc);
2836                         gen_op_check_align_T0_3();
2837                         gen_op_movl_npc_T0();
2838                         dc->npc = DYNAMIC_PC;
2839                     }
2840                     goto jmp_insn;
2841 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2842                 case 0x39:      /* rett, V9 return */
2843                     {
2844                         if (!supervisor(dc))
2845                             goto priv_insn;
2846                         gen_mov_pc_npc(dc);
2847                         gen_op_check_align_T0_3();
2848                         gen_op_movl_npc_T0();
2849                         dc->npc = DYNAMIC_PC;
2850                         gen_op_rett();
2851                     }
2852                     goto jmp_insn;
2853 #endif
2854                 case 0x3b: /* flush */
2855                     gen_op_flush_T0();
2856                     break;
2857                 case 0x3c:      /* save */
2858                     save_state(dc);
2859                     gen_op_save();
2860                     gen_movl_T0_reg(rd);
2861                     break;
2862                 case 0x3d:      /* restore */
2863                     save_state(dc);
2864                     gen_op_restore();
2865                     gen_movl_T0_reg(rd);
2866                     break;
2867 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2868                 case 0x3e:      /* V9 done/retry */
2869                     {
2870                         switch (rd) {
2871                         case 0:
2872                             if (!supervisor(dc))
2873                                 goto priv_insn;
2874                             dc->npc = DYNAMIC_PC;
2875                             dc->pc = DYNAMIC_PC;
2876                             gen_op_done();
2877                             goto jmp_insn;
2878                         case 1:
2879                             if (!supervisor(dc))
2880                                 goto priv_insn;
2881                             dc->npc = DYNAMIC_PC;
2882                             dc->pc = DYNAMIC_PC;
2883                             gen_op_retry();
2884                             goto jmp_insn;
2885                         default:
2886                             goto illegal_insn;
2887                         }
2888                     }
2889                     break;
2890 #endif
2891                 default:
2892                     goto illegal_insn;
2893                 }
2894             }
2895             break;
2896         }
2897         break;
2898     case 3:                     /* load/store instructions */
2899         {
2900             unsigned int xop = GET_FIELD(insn, 7, 12);
2901             rs1 = GET_FIELD(insn, 13, 17);
2902             save_state(dc);
2903             gen_movl_reg_T0(rs1);
2904             if (xop == 0x3c || xop == 0x3e)
2905             {
2906                 rs2 = GET_FIELD(insn, 27, 31);
2907                 gen_movl_reg_T1(rs2);
2908             }
2909             else if (IS_IMM) {       /* immediate */
2910                 rs2 = GET_FIELDs(insn, 19, 31);
2911 #if defined(OPTIM)
2912                 if (rs2 != 0) {
2913 #endif
2914                     gen_movl_simm_T1(rs2);
2915                     gen_op_add_T1_T0();
2916 #if defined(OPTIM)
2917                 }
2918 #endif
2919             } else {            /* register */
2920                 rs2 = GET_FIELD(insn, 27, 31);
2921 #if defined(OPTIM)
2922                 if (rs2 != 0) {
2923 #endif
2924                     gen_movl_reg_T1(rs2);
2925                     gen_op_add_T1_T0();
2926 #if defined(OPTIM)
2927                 }
2928 #endif
2929             }
2930             if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2931                 (xop > 0x17 && xop <= 0x1d ) ||
2932                 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
2933                 switch (xop) {
2934                 case 0x0:       /* load word */
2935 #ifdef CONFIG_USER_ONLY
2936                     gen_op_check_align_T0_3();
2937 #endif
2938 #ifndef TARGET_SPARC64
2939                     gen_op_ldst(ld);
2940 #else
2941                     gen_op_ldst(lduw);
2942 #endif
2943                     break;
2944                 case 0x1:       /* load unsigned byte */
2945                     gen_op_ldst(ldub);
2946                     break;
2947                 case 0x2:       /* load unsigned halfword */
2948 #ifdef CONFIG_USER_ONLY
2949                     gen_op_check_align_T0_1();
2950 #endif
2951                     gen_op_ldst(lduh);
2952                     break;
2953                 case 0x3:       /* load double word */
2954                     gen_op_check_align_T0_7();
2955                     if (rd & 1)
2956                         goto illegal_insn;
2957                     gen_op_ldst(ldd);
2958                     gen_movl_T0_reg(rd + 1);
2959                     break;
2960                 case 0x9:       /* load signed byte */
2961                     gen_op_ldst(ldsb);
2962                     break;
2963                 case 0xa:       /* load signed halfword */
2964 #ifdef CONFIG_USER_ONLY
2965                     gen_op_check_align_T0_1();
2966 #endif
2967                     gen_op_ldst(ldsh);
2968                     break;
2969                 case 0xd:       /* ldstub -- XXX: should be atomically */
2970                     gen_op_ldst(ldstub);
2971                     break;
2972                 case 0x0f:      /* swap register with memory. Also atomically */
2973 #ifdef CONFIG_USER_ONLY
2974                     gen_op_check_align_T0_3();
2975 #endif
2976                     gen_movl_reg_T1(rd);
2977                     gen_op_ldst(swap);
2978                     break;
2979 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2980                 case 0x10:      /* load word alternate */
2981 #ifndef TARGET_SPARC64
2982                     if (IS_IMM)
2983                         goto illegal_insn;
2984                     if (!supervisor(dc))
2985                         goto priv_insn;
2986 #elif CONFIG_USER_ONLY
2987                     gen_op_check_align_T0_3();
2988 #endif
2989                     gen_ld_asi(insn, 4, 0);
2990                     break;
2991                 case 0x11:      /* load unsigned byte alternate */
2992 #ifndef TARGET_SPARC64
2993                     if (IS_IMM)
2994                         goto illegal_insn;
2995                     if (!supervisor(dc))
2996                         goto priv_insn;
2997 #endif
2998                     gen_ld_asi(insn, 1, 0);
2999                     break;
3000                 case 0x12:      /* load unsigned halfword alternate */
3001 #ifndef TARGET_SPARC64
3002                     if (IS_IMM)
3003                         goto illegal_insn;
3004                     if (!supervisor(dc))
3005                         goto priv_insn;
3006 #elif CONFIG_USER_ONLY
3007                     gen_op_check_align_T0_1();
3008 #endif
3009                     gen_ld_asi(insn, 2, 0);
3010                     break;
3011                 case 0x13:      /* load double word alternate */
3012 #ifndef TARGET_SPARC64
3013                     if (IS_IMM)
3014                         goto illegal_insn;
3015                     if (!supervisor(dc))
3016                         goto priv_insn;
3017 #endif
3018                     if (rd & 1)
3019                         goto illegal_insn;
3020                     gen_op_check_align_T0_7();
3021                     gen_ldda_asi(insn);
3022                     gen_movl_T0_reg(rd + 1);
3023                     break;
3024                 case 0x19:      /* load signed byte alternate */
3025 #ifndef TARGET_SPARC64
3026                     if (IS_IMM)
3027                         goto illegal_insn;
3028                     if (!supervisor(dc))
3029                         goto priv_insn;
3030 #endif
3031                     gen_ld_asi(insn, 1, 1);
3032                     break;
3033                 case 0x1a:      /* load signed halfword alternate */
3034 #ifndef TARGET_SPARC64
3035                     if (IS_IMM)
3036                         goto illegal_insn;
3037                     if (!supervisor(dc))
3038                         goto priv_insn;
3039 #elif CONFIG_USER_ONLY
3040                     gen_op_check_align_T0_1();
3041 #endif
3042                     gen_ld_asi(insn, 2, 1);
3043                     break;
3044                 case 0x1d:      /* ldstuba -- XXX: should be atomically */
3045 #ifndef TARGET_SPARC64
3046                     if (IS_IMM)
3047                         goto illegal_insn;
3048                     if (!supervisor(dc))
3049                         goto priv_insn;
3050 #endif
3051                     gen_ldstub_asi(insn);
3052                     break;
3053                 case 0x1f:      /* swap reg with alt. memory. Also atomically */
3054 #ifndef TARGET_SPARC64
3055                     if (IS_IMM)
3056                         goto illegal_insn;
3057                     if (!supervisor(dc))
3058                         goto priv_insn;
3059 #elif CONFIG_USER_ONLY
3060                     gen_op_check_align_T0_3();
3061 #endif
3062                     gen_movl_reg_T1(rd);
3063                     gen_swap_asi(insn);
3064                     break;
3065
3066 #ifndef TARGET_SPARC64
3067                 case 0x30: /* ldc */
3068                 case 0x31: /* ldcsr */
3069                 case 0x33: /* lddc */
3070                     goto ncp_insn;
3071 #endif
3072 #endif
3073 #ifdef TARGET_SPARC64
3074                 case 0x08: /* V9 ldsw */
3075 #ifdef CONFIG_USER_ONLY
3076                     gen_op_check_align_T0_3();
3077 #endif
3078                     gen_op_ldst(ldsw);
3079                     break;
3080                 case 0x0b: /* V9 ldx */
3081                     gen_op_check_align_T0_7();
3082                     gen_op_ldst(ldx);
3083                     break;
3084                 case 0x18: /* V9 ldswa */
3085 #ifdef CONFIG_USER_ONLY
3086                     gen_op_check_align_T0_3();
3087 #endif
3088                     gen_ld_asi(insn, 4, 1);
3089                     break;
3090                 case 0x1b: /* V9 ldxa */
3091                     gen_op_check_align_T0_7();
3092                     gen_ld_asi(insn, 8, 0);
3093                     break;
3094                 case 0x2d: /* V9 prefetch, no effect */
3095                     goto skip_move;
3096                 case 0x30: /* V9 ldfa */
3097 #ifdef CONFIG_USER_ONLY
3098                     gen_op_check_align_T0_3();
3099 #endif
3100                     gen_ldf_asi(insn, 4);
3101                     goto skip_move;
3102                 case 0x33: /* V9 lddfa */
3103                     gen_op_check_align_T0_3();
3104                     gen_ldf_asi(insn, 8);
3105                     goto skip_move;
3106                 case 0x3d: /* V9 prefetcha, no effect */
3107                     goto skip_move;
3108                 case 0x32: /* V9 ldqfa */
3109                     goto nfpu_insn;
3110 #endif
3111                 default:
3112                     goto illegal_insn;
3113                 }
3114                 gen_movl_T1_reg(rd);
3115 #ifdef TARGET_SPARC64
3116             skip_move: ;
3117 #endif
3118             } else if (xop >= 0x20 && xop < 0x24) {
3119                 if (gen_trap_ifnofpu(dc))
3120                     goto jmp_insn;
3121                 switch (xop) {
3122                 case 0x20:      /* load fpreg */
3123 #ifdef CONFIG_USER_ONLY
3124                     gen_op_check_align_T0_3();
3125 #endif
3126                     gen_op_ldst(ldf);
3127                     gen_op_store_FT0_fpr(rd);
3128                     break;
3129                 case 0x21:      /* load fsr */
3130 #ifdef CONFIG_USER_ONLY
3131                     gen_op_check_align_T0_3();
3132 #endif
3133                     gen_op_ldst(ldf);
3134                     gen_op_ldfsr();
3135                     break;
3136                 case 0x22:      /* load quad fpreg */
3137                     goto nfpu_insn;
3138                 case 0x23:      /* load double fpreg */
3139                     gen_op_check_align_T0_7();
3140                     gen_op_ldst(lddf);
3141                     gen_op_store_DT0_fpr(DFPREG(rd));
3142                     break;
3143                 default:
3144                     goto illegal_insn;
3145                 }
3146             } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3147                        xop == 0xe || xop == 0x1e) {
3148                 gen_movl_reg_T1(rd);
3149                 switch (xop) {
3150                 case 0x4:
3151 #ifdef CONFIG_USER_ONLY
3152                     gen_op_check_align_T0_3();
3153 #endif
3154                     gen_op_ldst(st);
3155                     break;
3156                 case 0x5:
3157                     gen_op_ldst(stb);
3158                     break;
3159                 case 0x6:
3160 #ifdef CONFIG_USER_ONLY
3161                     gen_op_check_align_T0_1();
3162 #endif
3163                     gen_op_ldst(sth);
3164                     break;
3165                 case 0x7:
3166                     if (rd & 1)
3167                         goto illegal_insn;
3168                     gen_op_check_align_T0_7();
3169                     flush_T2(dc);
3170                     gen_movl_reg_T2(rd + 1);
3171                     gen_op_ldst(std);
3172                     break;
3173 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3174                 case 0x14:
3175 #ifndef TARGET_SPARC64
3176                     if (IS_IMM)
3177                         goto illegal_insn;
3178                     if (!supervisor(dc))
3179                         goto priv_insn;
3180 #endif
3181 #ifdef CONFIG_USER_ONLY
3182                     gen_op_check_align_T0_3();
3183 #endif
3184                     gen_st_asi(insn, 4);
3185                     break;
3186                 case 0x15:
3187 #ifndef TARGET_SPARC64
3188                     if (IS_IMM)
3189                         goto illegal_insn;
3190                     if (!supervisor(dc))
3191                         goto priv_insn;
3192 #endif
3193                     gen_st_asi(insn, 1);
3194                     break;
3195                 case 0x16:
3196 #ifndef TARGET_SPARC64
3197                     if (IS_IMM)
3198                         goto illegal_insn;
3199                     if (!supervisor(dc))
3200                         goto priv_insn;
3201 #endif
3202 #ifdef CONFIG_USER_ONLY
3203                     gen_op_check_align_T0_1();
3204 #endif
3205                     gen_st_asi(insn, 2);
3206                     break;
3207                 case 0x17:
3208 #ifndef TARGET_SPARC64
3209                     if (IS_IMM)
3210                         goto illegal_insn;
3211                     if (!supervisor(dc))
3212                         goto priv_insn;
3213 #endif
3214                     if (rd & 1)
3215                         goto illegal_insn;
3216                     gen_op_check_align_T0_7();
3217                     flush_T2(dc);
3218                     gen_movl_reg_T2(rd + 1);
3219                     gen_stda_asi(insn);
3220                     break;
3221 #endif
3222 #ifdef TARGET_SPARC64
3223                 case 0x0e: /* V9 stx */
3224                     gen_op_check_align_T0_7();
3225                     gen_op_ldst(stx);
3226                     break;
3227                 case 0x1e: /* V9 stxa */
3228                     gen_op_check_align_T0_7();
3229                     gen_st_asi(insn, 8);
3230                     break;
3231 #endif
3232                 default:
3233                     goto illegal_insn;
3234                 }
3235             } else if (xop > 0x23 && xop < 0x28) {
3236                 if (gen_trap_ifnofpu(dc))
3237                     goto jmp_insn;
3238                 switch (xop) {
3239                 case 0x24:
3240 #ifdef CONFIG_USER_ONLY
3241                     gen_op_check_align_T0_3();
3242 #endif
3243                     gen_op_load_fpr_FT0(rd);
3244                     gen_op_ldst(stf);
3245                     break;
3246                 case 0x25: /* stfsr, V9 stxfsr */
3247 #ifdef CONFIG_USER_ONLY
3248                     gen_op_check_align_T0_3();
3249 #endif
3250                     gen_op_stfsr();
3251                     gen_op_ldst(stf);
3252                     break;
3253 #if !defined(CONFIG_USER_ONLY)
3254                 case 0x26: /* stdfq */
3255                     if (!supervisor(dc))
3256                         goto priv_insn;
3257                     if (gen_trap_ifnofpu(dc))
3258                         goto jmp_insn;
3259                     goto nfq_insn;
3260 #endif
3261                 case 0x27:
3262                     gen_op_check_align_T0_7();
3263                     gen_op_load_fpr_DT0(DFPREG(rd));
3264                     gen_op_ldst(stdf);
3265                     break;
3266                 default:
3267                     goto illegal_insn;
3268                 }
3269             } else if (xop > 0x33 && xop < 0x3f) {
3270                 switch (xop) {
3271 #ifdef TARGET_SPARC64
3272                 case 0x34: /* V9 stfa */
3273 #ifdef CONFIG_USER_ONLY
3274                     gen_op_check_align_T0_3();
3275 #endif
3276                     gen_op_load_fpr_FT0(rd);
3277                     gen_stf_asi(insn, 4);
3278                     break;
3279                 case 0x37: /* V9 stdfa */
3280                     gen_op_check_align_T0_3();
3281                     gen_op_load_fpr_DT0(DFPREG(rd));
3282                     gen_stf_asi(insn, 8);
3283                     break;
3284                 case 0x3c: /* V9 casa */
3285 #ifdef CONFIG_USER_ONLY
3286                     gen_op_check_align_T0_3();
3287 #endif
3288                     flush_T2(dc);
3289                     gen_movl_reg_T2(rd);
3290                     gen_cas_asi(insn);
3291                     gen_movl_T1_reg(rd);
3292                     break;
3293                 case 0x3e: /* V9 casxa */
3294                     gen_op_check_align_T0_7();
3295                     flush_T2(dc);
3296                     gen_movl_reg_T2(rd);
3297                     gen_casx_asi(insn);
3298                     gen_movl_T1_reg(rd);
3299                     break;
3300                 case 0x36: /* V9 stqfa */
3301                     goto nfpu_insn;
3302 #else
3303                 case 0x34: /* stc */
3304                 case 0x35: /* stcsr */
3305                 case 0x36: /* stdcq */
3306                 case 0x37: /* stdc */
3307                     goto ncp_insn;
3308 #endif
3309                 default:
3310                     goto illegal_insn;
3311                 }
3312             }
3313             else
3314                 goto illegal_insn;
3315         }
3316         break;
3317     }
3318     /* default case for non jump instructions */
3319     if (dc->npc == DYNAMIC_PC) {
3320         dc->pc = DYNAMIC_PC;
3321         gen_op_next_insn();
3322     } else if (dc->npc == JUMP_PC) {
3323         /* we can do a static jump */
3324         gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
3325         dc->is_br = 1;
3326     } else {
3327         dc->pc = dc->npc;
3328         dc->npc = dc->npc + 4;
3329     }
3330  jmp_insn:
3331     return;
3332  illegal_insn:
3333     save_state(dc);
3334     gen_op_exception(TT_ILL_INSN);
3335     dc->is_br = 1;
3336     return;
3337 #if !defined(CONFIG_USER_ONLY)
3338  priv_insn:
3339     save_state(dc);
3340     gen_op_exception(TT_PRIV_INSN);
3341     dc->is_br = 1;
3342     return;
3343 #endif
3344  nfpu_insn:
3345     save_state(dc);
3346     gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3347     dc->is_br = 1;
3348     return;
3349 #if !defined(CONFIG_USER_ONLY)
3350  nfq_insn:
3351     save_state(dc);
3352     gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3353     dc->is_br = 1;
3354     return;
3355 #endif
3356 #ifndef TARGET_SPARC64
3357  ncp_insn:
3358     save_state(dc);
3359     gen_op_exception(TT_NCP_INSN);
3360     dc->is_br = 1;
3361     return;
3362 #endif
3363 }
3364
3365 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3366                                                  int spc, CPUSPARCState *env)
3367 {
3368     target_ulong pc_start, last_pc;
3369     uint16_t *gen_opc_end;
3370     DisasContext dc1, *dc = &dc1;
3371     int j, lj = -1;
3372
3373     memset(dc, 0, sizeof(DisasContext));
3374     dc->tb = tb;
3375     pc_start = tb->pc;
3376     dc->pc = pc_start;
3377     last_pc = dc->pc;
3378     dc->npc = (target_ulong) tb->cs_base;
3379 #if defined(CONFIG_USER_ONLY)
3380     dc->mem_idx = 0;
3381     dc->fpu_enabled = 1;
3382 #else
3383     dc->mem_idx = ((env->psrs) != 0);
3384 #ifdef TARGET_SPARC64
3385     dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3386 #else
3387     dc->fpu_enabled = ((env->psref) != 0);
3388 #endif
3389 #endif
3390     gen_opc_ptr = gen_opc_buf;
3391     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3392     gen_opparam_ptr = gen_opparam_buf;
3393     nb_gen_labels = 0;
3394
3395     do {
3396         if (env->nb_breakpoints > 0) {
3397             for(j = 0; j < env->nb_breakpoints; j++) {
3398                 if (env->breakpoints[j] == dc->pc) {
3399                     if (dc->pc != pc_start)
3400                         save_state(dc);
3401                     gen_op_debug();
3402                     gen_op_movl_T0_0();
3403                     gen_op_exit_tb();
3404                     dc->is_br = 1;
3405                     goto exit_gen_loop;
3406                 }
3407             }
3408         }
3409         if (spc) {
3410             if (loglevel > 0)
3411                 fprintf(logfile, "Search PC...\n");
3412             j = gen_opc_ptr - gen_opc_buf;
3413             if (lj < j) {
3414                 lj++;
3415                 while (lj < j)
3416                     gen_opc_instr_start[lj++] = 0;
3417                 gen_opc_pc[lj] = dc->pc;
3418                 gen_opc_npc[lj] = dc->npc;
3419                 gen_opc_instr_start[lj] = 1;
3420             }
3421         }
3422         last_pc = dc->pc;
3423         disas_sparc_insn(dc);
3424
3425         if (dc->is_br)
3426             break;
3427         /* if the next PC is different, we abort now */
3428         if (dc->pc != (last_pc + 4))
3429             break;
3430         /* if we reach a page boundary, we stop generation so that the
3431            PC of a TT_TFAULT exception is always in the right page */
3432         if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3433             break;
3434         /* if single step mode, we generate only one instruction and
3435            generate an exception */
3436         if (env->singlestep_enabled) {
3437             gen_jmp_im(dc->pc);
3438             gen_op_movl_T0_0();
3439             gen_op_exit_tb();
3440             break;
3441         }
3442     } while ((gen_opc_ptr < gen_opc_end) &&
3443              (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3444
3445  exit_gen_loop:
3446     if (!dc->is_br) {
3447         if (dc->pc != DYNAMIC_PC &&
3448             (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3449             /* static PC and NPC: we can use direct chaining */
3450             gen_branch(dc, dc->pc, dc->npc);
3451         } else {
3452             if (dc->pc != DYNAMIC_PC)
3453                 gen_jmp_im(dc->pc);
3454             save_npc(dc);
3455             gen_op_movl_T0_0();
3456             gen_op_exit_tb();
3457         }
3458     }
3459     *gen_opc_ptr = INDEX_op_end;
3460     if (spc) {
3461         j = gen_opc_ptr - gen_opc_buf;
3462         lj++;
3463         while (lj <= j)
3464             gen_opc_instr_start[lj++] = 0;
3465 #if 0
3466         if (loglevel > 0) {
3467             page_dump(logfile);
3468         }
3469 #endif
3470         gen_opc_jump_pc[0] = dc->jump_pc[0];
3471         gen_opc_jump_pc[1] = dc->jump_pc[1];
3472     } else {
3473         tb->size = last_pc + 4 - pc_start;
3474     }
3475 #ifdef DEBUG_DISAS
3476     if (loglevel & CPU_LOG_TB_IN_ASM) {
3477         fprintf(logfile, "--------------\n");
3478         fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3479         target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3480         fprintf(logfile, "\n");
3481         if (loglevel & CPU_LOG_TB_OP) {
3482             fprintf(logfile, "OP:\n");
3483             dump_ops(gen_opc_buf, gen_opparam_buf);
3484             fprintf(logfile, "\n");
3485         }
3486     }
3487 #endif
3488     return 0;
3489 }
3490
3491 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3492 {
3493     return gen_intermediate_code_internal(tb, 0, env);
3494 }
3495
3496 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3497 {
3498     return gen_intermediate_code_internal(tb, 1, env);
3499 }
3500
3501 extern int ram_size;
3502
3503 void cpu_reset(CPUSPARCState *env)
3504 {
3505     tlb_flush(env, 1);
3506     env->cwp = 0;
3507     env->wim = 1;
3508     env->regwptr = env->regbase + (env->cwp * 16);
3509 #if defined(CONFIG_USER_ONLY)
3510     env->user_mode_only = 1;
3511 #ifdef TARGET_SPARC64
3512     env->cleanwin = NWINDOWS - 2;
3513     env->cansave = NWINDOWS - 2;
3514     env->pstate = PS_RMO | PS_PEF | PS_IE;
3515     env->asi = 0x82; // Primary no-fault
3516 #endif
3517 #else
3518     env->psret = 0;
3519     env->psrs = 1;
3520     env->psrps = 1;
3521 #ifdef TARGET_SPARC64
3522     env->pstate = PS_PRIV;
3523     env->pc = 0x1fff0000000ULL;
3524 #else
3525     env->pc = 0;
3526     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3527     env->mmuregs[0] |= MMU_BM;
3528 #endif
3529     env->npc = env->pc + 4;
3530 #endif
3531 }
3532
3533 CPUSPARCState *cpu_sparc_init(void)
3534 {
3535     CPUSPARCState *env;
3536
3537     env = qemu_mallocz(sizeof(CPUSPARCState));
3538     if (!env)
3539         return NULL;
3540     cpu_exec_init(env);
3541     cpu_reset(env);
3542     return (env);
3543 }
3544
3545 static const sparc_def_t sparc_defs[] = {
3546 #ifdef TARGET_SPARC64
3547     {
3548         .name = "TI UltraSparc II",
3549         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3550                        | (MAXTL << 8) | (NWINDOWS - 1)),
3551         .fpu_version = 0x00000000,
3552         .mmu_version = 0,
3553     },
3554 #else
3555     {
3556         .name = "Fujitsu MB86904",
3557         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3558         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3559         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3560     },
3561     {
3562         .name = "Fujitsu MB86907",
3563         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3564         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3565         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3566     },
3567     {
3568         .name = "TI MicroSparc I",
3569         .iu_version = 0x41000000,
3570         .fpu_version = 4 << 17,
3571         .mmu_version = 0x41000000,
3572     },
3573     {
3574         .name = "TI SuperSparc II",
3575         .iu_version = 0x40000000,
3576         .fpu_version = 0 << 17,
3577         .mmu_version = 0x04000000,
3578     },
3579     {
3580         .name = "Ross RT620",
3581         .iu_version = 0x1e000000,
3582         .fpu_version = 1 << 17,
3583         .mmu_version = 0x17000000,
3584     },
3585 #endif
3586 };
3587
3588 int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3589 {
3590     int ret;
3591     unsigned int i;
3592
3593     ret = -1;
3594     *def = NULL;
3595     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3596         if (strcasecmp(name, sparc_defs[i].name) == 0) {
3597             *def = &sparc_defs[i];
3598             ret = 0;
3599             break;
3600         }
3601     }
3602
3603     return ret;
3604 }
3605
3606 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3607 {
3608     unsigned int i;
3609
3610     for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3611         (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3612                        sparc_defs[i].name,
3613                        sparc_defs[i].iu_version,
3614                        sparc_defs[i].fpu_version,
3615                        sparc_defs[i].mmu_version);
3616     }
3617 }
3618
3619 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3620 {
3621     env->version = def->iu_version;
3622     env->fsr = def->fpu_version;
3623 #if !defined(TARGET_SPARC64)
3624     env->mmuregs[0] |= def->mmu_version;
3625 #endif
3626     return 0;
3627 }
3628
3629 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3630
3631 void cpu_dump_state(CPUState *env, FILE *f,
3632                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3633                     int flags)
3634 {
3635     int i, x;
3636
3637     cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3638     cpu_fprintf(f, "General Registers:\n");
3639     for (i = 0; i < 4; i++)
3640         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3641     cpu_fprintf(f, "\n");
3642     for (; i < 8; i++)
3643         cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3644     cpu_fprintf(f, "\nCurrent Register Window:\n");
3645     for (x = 0; x < 3; x++) {
3646         for (i = 0; i < 4; i++)
3647             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3648                     (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3649                     env->regwptr[i + x * 8]);
3650         cpu_fprintf(f, "\n");
3651         for (; i < 8; i++)
3652             cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3653                     (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3654                     env->regwptr[i + x * 8]);
3655         cpu_fprintf(f, "\n");
3656     }
3657     cpu_fprintf(f, "\nFloating Point Registers:\n");
3658     for (i = 0; i < 32; i++) {
3659         if ((i & 3) == 0)
3660             cpu_fprintf(f, "%%f%02d:", i);
3661         cpu_fprintf(f, " %016lf", env->fpr[i]);
3662         if ((i & 3) == 3)
3663             cpu_fprintf(f, "\n");
3664     }
3665 #ifdef TARGET_SPARC64
3666     cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3667                 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3668     cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3669                 env->cansave, env->canrestore, env->otherwin, env->wstate,
3670                 env->cleanwin, NWINDOWS - 1 - env->cwp);
3671 #else
3672     cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3673             GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3674             GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3675             env->psrs?'S':'-', env->psrps?'P':'-',
3676             env->psret?'E':'-', env->wim);
3677 #endif
3678     cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3679 }
3680
3681 #if defined(CONFIG_USER_ONLY)
3682 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3683 {
3684     return addr;
3685 }
3686
3687 #else
3688 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3689                                  int *access_index, target_ulong address, int rw,
3690                                  int is_user);
3691
3692 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3693 {
3694     target_phys_addr_t phys_addr;
3695     int prot, access_index;
3696
3697     if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
3698         if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3699             return -1;
3700     if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3701         return -1;
3702     return phys_addr;
3703 }
3704 #endif
3705
3706 void helper_flush(target_ulong addr)
3707 {
3708     addr &= ~7;
3709     tb_invalidate_page_range(addr, addr + 8);
3710 }