5 #ifdef USE_INT_TO_FLOAT_HELPERS
8 FT0 = (float) *((int32_t *)&FT1);
13 DT0 = (double) *((int32_t *)&FT1);
34 if (isnan(FT0) || isnan(FT1)) {
35 T0 = FSR_FCC1 | FSR_FCC0;
36 } else if (FT0 < FT1) {
38 } else if (FT0 > FT1) {
48 if (isnan(DT0) || isnan(DT1)) {
49 T0 = FSR_FCC1 | FSR_FCC0;
50 } else if (DT0 < DT1) {
52 } else if (DT0 > DT1) {
60 void helper_ld_asi(int asi, int size, int sign)
63 case 3: /* MMU probe */
66 case 4: /* read MMU regs */
68 int temp, reg = (T0 >> 8) & 0xf;
70 temp = env->mmuregs[reg];
71 if (reg == 3 || reg == 4) /* Fault status, addr cleared on read*/
72 env->mmuregs[reg] = 0;
76 case 0x20 ... 0x2f: /* MMU passthrough */
80 cpu_physical_memory_read(T0, (void *) &temp, size);
91 void helper_st_asi(int asi, int size, int sign)
94 case 3: /* MMU flush */
96 case 4: /* write MMU regs */
98 int reg = (T0 >> 8) & 0xf;
100 env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
101 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
103 env->mmuregs[reg] = T1;
106 case 0x20 ... 0x2f: /* MMU passthrough */
111 cpu_physical_memory_write(T0, (void *) &temp, size);
120 void do_ldd_raw(uint32_t addr)
122 T1 = ldl_raw((void *) addr);
123 T0 = ldl_raw((void *) (addr + 4));
126 #if !defined(CONFIG_USER_ONLY)
127 void do_ldd_user(uint32_t addr)
129 T1 = ldl_user((void *) addr);
130 T0 = ldl_user((void *) (addr + 4));
132 void do_ldd_kernel(uint32_t addr)
134 T1 = ldl_kernel((void *) addr);
135 T0 = ldl_kernel((void *) (addr + 4));
144 cwp = (env->cwp + 1) & (NWINDOWS - 1);
145 if (env->wim & (1 << cwp)) {
146 raise_exception(TT_WIN_UNF);
149 env->psrs = env->psrps;
152 void helper_ldfsr(void)
154 switch (env->fsr & FSR_RD_MASK) {
156 fesetround(FE_TONEAREST);
159 fesetround(FE_TOWARDZERO);
162 fesetround(FE_UPWARD);
165 fesetround(FE_DOWNWARD);