6 void raise_exception(int tt)
8 env->exception_index = tt;
12 #ifdef USE_INT_TO_FLOAT_HELPERS
15 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
20 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
26 FT0 = float32_abs(FT1);
32 DT0 = float64_abs(DT1);
38 FT0 = float32_sqrt(FT1, &env->fp_status);
43 DT0 = float64_sqrt(DT1, &env->fp_status);
46 #define GEN_FCMP(name, size, reg1, reg2, FS) \
47 void glue(do_, name) (void) \
49 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
50 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
51 case float_relation_unordered: \
52 T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
53 if (env->fsr & FSR_NVM) { \
55 raise_exception(TT_FP_EXCP); \
57 env->fsr |= FSR_NVA; \
60 case float_relation_less: \
61 T0 = FSR_FCC0 << FS; \
63 case float_relation_greater: \
64 T0 = FSR_FCC1 << FS; \
73 GEN_FCMP(fcmps, float32, FT0, FT1, 0);
74 GEN_FCMP(fcmpd, float64, DT0, DT1, 0);
77 GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22);
78 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22);
80 GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24);
81 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24);
83 GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26);
84 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26);
87 #if defined(CONFIG_USER_ONLY)
88 void helper_ld_asi(int asi, int size, int sign)
92 void helper_st_asi(int asi, int size, int sign)
96 #ifndef TARGET_SPARC64
97 void helper_ld_asi(int asi, int size, int sign)
102 case 3: /* MMU probe */
106 mmulev = (T0 >> 8) & 15;
110 ret = mmu_probe(env, T0, mmulev);
114 printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
118 case 4: /* read MMU regs */
120 int reg = (T0 >> 8) & 0xf;
122 ret = env->mmuregs[reg];
123 if (reg == 3) /* Fault status cleared on read */
124 env->mmuregs[reg] = 0;
126 printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
130 case 0x20 ... 0x2f: /* MMU passthrough */
136 ret = lduw_phys(T0 & ~1);
140 ret = ldl_phys(T0 & ~3);
143 ret = ldl_phys(T0 & ~3);
144 T0 = ldl_phys((T0 + 4) & ~3);
155 void helper_st_asi(int asi, int size, int sign)
158 case 3: /* MMU flush */
162 mmulev = (T0 >> 8) & 15;
164 printf("mmu flush level %d\n", mmulev);
167 case 0: // flush page
168 tlb_flush_page(env, T0 & 0xfffff000);
170 case 1: // flush segment (256k)
171 case 2: // flush region (16M)
172 case 3: // flush context (4G)
173 case 4: // flush entire
184 case 4: /* write MMU regs */
186 int reg = (T0 >> 8) & 0xf;
189 oldreg = env->mmuregs[reg];
192 env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
193 env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
194 // Mappings generated during no-fault mode or MMU
195 // disabled mode are invalid in normal mode
196 if (oldreg != env->mmuregs[reg])
200 env->mmuregs[reg] = T1;
201 if (oldreg != env->mmuregs[reg]) {
202 /* we flush when the MMU context changes because
203 QEMU has no MMU context support */
211 env->mmuregs[reg] = T1;
215 if (oldreg != env->mmuregs[reg]) {
216 printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
222 case 0x17: /* Block copy, sta access */
225 // address (T0) = dst
227 uint32_t src = T1, dst = T0;
232 cpu_physical_memory_read(src, (void *) &temp, 32);
233 cpu_physical_memory_write(dst, (void *) &temp, 32);
236 case 0x1f: /* Block fill, stda access */
239 // address (T0) = dst
245 val = (((uint64_t)T1) << 32) | T2;
248 for (i = 0; i < 32; i += 8, dst += 8) {
249 cpu_physical_memory_write(dst, (void *) &val, 8);
253 case 0x20 ... 0x2f: /* MMU passthrough */
260 stw_phys(T0 & ~1, T1);
264 stl_phys(T0 & ~3, T1);
267 stl_phys(T0 & ~3, T1);
268 stl_phys((T0 + 4) & ~3, T2);
280 void helper_ld_asi(int asi, int size, int sign)
284 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
285 raise_exception(TT_PRIV_ACT);
289 case 0x15: // Bypass, non-cacheable
296 ret = lduw_phys(T0 & ~1);
299 ret = ldl_phys(T0 & ~3);
303 ret = ldq_phys(T0 & ~7);
308 case 0x04: // Nucleus
309 case 0x0c: // Nucleus Little Endian (LE)
310 case 0x10: // As if user primary
311 case 0x11: // As if user secondary
312 case 0x18: // As if user primary LE
313 case 0x19: // As if user secondary LE
314 case 0x1c: // Bypass LE
315 case 0x1d: // Bypass, non-cacheable LE
316 case 0x24: // Nucleus quad LDD 128 bit atomic
317 case 0x2c: // Nucleus quad LDD 128 bit atomic
318 case 0x4a: // UPA config
319 case 0x82: // Primary no-fault
320 case 0x83: // Secondary no-fault
321 case 0x88: // Primary LE
322 case 0x89: // Secondary LE
323 case 0x8a: // Primary no-fault LE
324 case 0x8b: // Secondary no-fault LE
330 case 0x50: // I-MMU regs
332 int reg = (T0 >> 3) & 0xf;
334 ret = env->immuregs[reg];
337 case 0x51: // I-MMU 8k TSB pointer
338 case 0x52: // I-MMU 64k TSB pointer
339 case 0x55: // I-MMU data access
342 case 0x56: // I-MMU tag read
346 for (i = 0; i < 64; i++) {
347 // Valid, ctx match, vaddr match
348 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
349 env->itlb_tag[i] == T0) {
350 ret = env->itlb_tag[i];
356 case 0x58: // D-MMU regs
358 int reg = (T0 >> 3) & 0xf;
360 ret = env->dmmuregs[reg];
363 case 0x5e: // D-MMU tag read
367 for (i = 0; i < 64; i++) {
368 // Valid, ctx match, vaddr match
369 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
370 env->dtlb_tag[i] == T0) {
371 ret = env->dtlb_tag[i];
377 case 0x59: // D-MMU 8k TSB pointer
378 case 0x5a: // D-MMU 64k TSB pointer
379 case 0x5b: // D-MMU data pointer
380 case 0x5d: // D-MMU data access
381 case 0x48: // Interrupt dispatch, RO
382 case 0x49: // Interrupt data receive
383 case 0x7f: // Incoming interrupt vector, RO
386 case 0x54: // I-MMU data in, WO
387 case 0x57: // I-MMU demap, WO
388 case 0x5c: // D-MMU data in, WO
389 case 0x5f: // D-MMU demap, WO
390 case 0x77: // Interrupt vector, WO
398 void helper_st_asi(int asi, int size, int sign)
400 if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
401 raise_exception(TT_PRIV_ACT);
405 case 0x15: // Bypass, non-cacheable
412 stw_phys(T0 & ~1, T1);
415 stl_phys(T0 & ~3, T1);
419 stq_phys(T0 & ~7, T1);
424 case 0x04: // Nucleus
425 case 0x0c: // Nucleus Little Endian (LE)
426 case 0x10: // As if user primary
427 case 0x11: // As if user secondary
428 case 0x18: // As if user primary LE
429 case 0x19: // As if user secondary LE
430 case 0x1c: // Bypass LE
431 case 0x1d: // Bypass, non-cacheable LE
432 case 0x24: // Nucleus quad LDD 128 bit atomic
433 case 0x2c: // Nucleus quad LDD 128 bit atomic
434 case 0x4a: // UPA config
435 case 0x88: // Primary LE
436 case 0x89: // Secondary LE
444 env->lsu = T1 & (DMMU_E | IMMU_E);
445 // Mappings generated during D/I MMU disabled mode are
446 // invalid in normal mode
447 if (oldreg != env->lsu) {
449 printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
456 case 0x50: // I-MMU regs
458 int reg = (T0 >> 3) & 0xf;
461 oldreg = env->immuregs[reg];
466 case 1: // Not in I-MMU
473 T1 = 0; // Clear SFSR
475 case 5: // TSB access
476 case 6: // Tag access
480 env->immuregs[reg] = T1;
482 if (oldreg != env->immuregs[reg]) {
483 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
489 case 0x54: // I-MMU data in
493 // Try finding an invalid entry
494 for (i = 0; i < 64; i++) {
495 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
496 env->itlb_tag[i] = env->immuregs[6];
497 env->itlb_tte[i] = T1;
501 // Try finding an unlocked entry
502 for (i = 0; i < 64; i++) {
503 if ((env->itlb_tte[i] & 0x40) == 0) {
504 env->itlb_tag[i] = env->immuregs[6];
505 env->itlb_tte[i] = T1;
512 case 0x55: // I-MMU data access
514 unsigned int i = (T0 >> 3) & 0x3f;
516 env->itlb_tag[i] = env->immuregs[6];
517 env->itlb_tte[i] = T1;
520 case 0x57: // I-MMU demap
523 case 0x58: // D-MMU regs
525 int reg = (T0 >> 3) & 0xf;
528 oldreg = env->dmmuregs[reg];
535 T1 = 0; // Clear SFSR, Fault address
536 env->dmmuregs[4] = 0;
538 env->dmmuregs[reg] = T1;
540 case 1: // Primary context
541 case 2: // Secondary context
542 case 5: // TSB access
543 case 6: // Tag access
544 case 7: // Virtual Watchpoint
545 case 8: // Physical Watchpoint
549 env->dmmuregs[reg] = T1;
551 if (oldreg != env->dmmuregs[reg]) {
552 printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
558 case 0x5c: // D-MMU data in
562 // Try finding an invalid entry
563 for (i = 0; i < 64; i++) {
564 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
565 env->dtlb_tag[i] = env->dmmuregs[6];
566 env->dtlb_tte[i] = T1;
570 // Try finding an unlocked entry
571 for (i = 0; i < 64; i++) {
572 if ((env->dtlb_tte[i] & 0x40) == 0) {
573 env->dtlb_tag[i] = env->dmmuregs[6];
574 env->dtlb_tte[i] = T1;
581 case 0x5d: // D-MMU data access
583 unsigned int i = (T0 >> 3) & 0x3f;
585 env->dtlb_tag[i] = env->dmmuregs[6];
586 env->dtlb_tte[i] = T1;
589 case 0x5f: // D-MMU demap
590 case 0x49: // Interrupt data receive
593 case 0x51: // I-MMU 8k TSB pointer, RO
594 case 0x52: // I-MMU 64k TSB pointer, RO
595 case 0x56: // I-MMU tag read, RO
596 case 0x59: // D-MMU 8k TSB pointer, RO
597 case 0x5a: // D-MMU 64k TSB pointer, RO
598 case 0x5b: // D-MMU data pointer, RO
599 case 0x5e: // D-MMU tag read, RO
600 case 0x48: // Interrupt dispatch, RO
601 case 0x7f: // Incoming interrupt vector, RO
602 case 0x82: // Primary no-fault, RO
603 case 0x83: // Secondary no-fault, RO
604 case 0x8a: // Primary no-fault LE, RO
605 case 0x8b: // Secondary no-fault LE, RO
611 #endif /* !CONFIG_USER_ONLY */
613 #ifndef TARGET_SPARC64
619 cwp = (env->cwp + 1) & (NWINDOWS - 1);
620 if (env->wim & (1 << cwp)) {
621 raise_exception(TT_WIN_UNF);
624 env->psrs = env->psrps;
628 void helper_ldfsr(void)
631 switch (env->fsr & FSR_RD_MASK) {
633 rnd_mode = float_round_nearest_even;
637 rnd_mode = float_round_to_zero;
640 rnd_mode = float_round_up;
643 rnd_mode = float_round_down;
646 set_float_rounding_mode(rnd_mode, &env->fp_status);
651 env->exception_index = EXCP_DEBUG;
655 #ifndef TARGET_SPARC64
670 T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
671 T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
672 T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
673 T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
674 T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
675 T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
678 static inline uint64_t *get_gregset(uint64_t pstate)
695 uint64_t new_pstate, pstate_regs, new_pstate_regs;
698 new_pstate = T0 & 0xf3f;
699 pstate_regs = env->pstate & 0xc01;
700 new_pstate_regs = new_pstate & 0xc01;
701 if (new_pstate_regs != pstate_regs) {
702 // Switch global register bank
703 src = get_gregset(new_pstate_regs);
704 dst = get_gregset(pstate_regs);
705 memcpy32(dst, env->gregs);
706 memcpy32(env->gregs, src);
708 env->pstate = new_pstate;
714 env->pc = env->tnpc[env->tl];
715 env->npc = env->tnpc[env->tl] + 4;
716 PUT_CCR(env, env->tstate[env->tl] >> 32);
717 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
718 env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
719 set_cwp(env->tstate[env->tl] & 0xff);
725 env->pc = env->tpc[env->tl];
726 env->npc = env->tnpc[env->tl];
727 PUT_CCR(env, env->tstate[env->tl] >> 32);
728 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
729 env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
730 set_cwp(env->tstate[env->tl] & 0xff);
734 void set_cwp(int new_cwp)
736 /* put the modified wrap registers at their proper location */
737 if (env->cwp == (NWINDOWS - 1))
738 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
740 /* put the wrap registers at their temporary location */
741 if (new_cwp == (NWINDOWS - 1))
742 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
743 env->regwptr = env->regbase + (new_cwp * 16);
744 REGWPTR = env->regwptr;
747 void cpu_set_cwp(CPUState *env1, int new_cwp)
751 target_ulong *saved_regwptr;
756 saved_regwptr = REGWPTR;
762 REGWPTR = saved_regwptr;
766 #ifdef TARGET_SPARC64
767 void do_interrupt(int intno)
770 if (loglevel & CPU_LOG_INT) {
772 fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
775 env->npc, env->regwptr[6]);
776 cpu_dump_state(env, logfile, fprintf, 0);
782 fprintf(logfile, " code=");
783 ptr = (uint8_t *)env->pc;
784 for(i = 0; i < 16; i++) {
785 fprintf(logfile, " %02x", ldub(ptr + i));
787 fprintf(logfile, "\n");
793 #if !defined(CONFIG_USER_ONLY)
794 if (env->tl == MAXTL) {
795 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
799 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
800 ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff);
801 env->tpc[env->tl] = env->pc;
802 env->tnpc[env->tl] = env->npc;
803 env->tt[env->tl] = intno;
804 env->pstate = PS_PEF | PS_PRIV | PS_AG;
805 env->tbr &= ~0x7fffULL;
806 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
807 if (env->tl < MAXTL - 1) {
810 env->pstate |= PS_RED;
811 if (env->tl != MAXTL)
815 env->npc = env->pc + 4;
816 env->exception_index = 0;
819 void do_interrupt(int intno)
824 if (loglevel & CPU_LOG_INT) {
826 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
829 env->npc, env->regwptr[6]);
830 cpu_dump_state(env, logfile, fprintf, 0);
836 fprintf(logfile, " code=");
837 ptr = (uint8_t *)env->pc;
838 for(i = 0; i < 16; i++) {
839 fprintf(logfile, " %02x", ldub(ptr + i));
841 fprintf(logfile, "\n");
847 #if !defined(CONFIG_USER_ONLY)
848 if (env->psret == 0) {
849 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
854 cwp = (env->cwp - 1) & (NWINDOWS - 1);
856 env->regwptr[9] = env->pc;
857 env->regwptr[10] = env->npc;
858 env->psrps = env->psrs;
860 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
862 env->npc = env->pc + 4;
863 env->exception_index = 0;
867 #if !defined(CONFIG_USER_ONLY)
869 #define MMUSUFFIX _mmu
870 #define GETPC() (__builtin_return_address(0))
873 #include "softmmu_template.h"
876 #include "softmmu_template.h"
879 #include "softmmu_template.h"
882 #include "softmmu_template.h"
885 /* try to fill the TLB and return an exception if error. If retaddr is
886 NULL, it means that the function was called in C code (i.e. not
887 from generated code or from helper.c) */
888 /* XXX: fix it to restore all registers */
889 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
891 TranslationBlock *tb;
896 /* XXX: hack to restore env in all cases, even if not called from
899 env = cpu_single_env;
901 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
904 /* now we have a real cpu fault */
905 pc = (unsigned long)retaddr;
908 /* the PC is inside the translated code. It means that we have
909 a virtual CPU fault */
910 cpu_restore_state(tb, env, pc, (void *)T2);