4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 /* Sparc MMU emulation */
37 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
41 spin_lock(&global_cpu_lock);
46 spin_unlock(&global_cpu_lock);
49 #if defined(CONFIG_USER_ONLY)
51 int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
52 int is_user, int is_softmmu)
55 env->exception_index = TT_TFAULT;
57 env->exception_index = TT_DFAULT;
63 #ifndef TARGET_SPARC64
65 * Sparc V8 Reference MMU (SRMMU)
67 static const int access_table[8][8] = {
68 { 0, 0, 0, 0, 2, 0, 3, 3 },
69 { 0, 0, 0, 0, 2, 0, 0, 0 },
70 { 2, 2, 0, 0, 0, 2, 3, 3 },
71 { 2, 2, 0, 0, 0, 2, 0, 0 },
72 { 2, 0, 2, 0, 2, 2, 3, 3 },
73 { 2, 0, 2, 0, 2, 0, 2, 0 },
74 { 2, 2, 2, 0, 2, 2, 3, 3 },
75 { 2, 2, 2, 0, 2, 2, 2, 0 }
78 static const int perm_table[2][8] = {
81 PAGE_READ | PAGE_WRITE,
82 PAGE_READ | PAGE_EXEC,
83 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
85 PAGE_READ | PAGE_WRITE,
86 PAGE_READ | PAGE_EXEC,
87 PAGE_READ | PAGE_WRITE | PAGE_EXEC
91 PAGE_READ | PAGE_WRITE,
92 PAGE_READ | PAGE_EXEC,
93 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
101 int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
102 int *access_index, target_ulong address, int rw,
105 int access_perms = 0;
106 target_phys_addr_t pde_ptr;
108 target_ulong virt_addr;
109 int error_code = 0, is_dirty;
110 unsigned long page_offset;
112 virt_addr = address & TARGET_PAGE_MASK;
113 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
115 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
119 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
120 *physical = 0xfffff000;
122 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
123 /* Context base + context number */
124 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
125 pde = ldl_phys(pde_ptr);
128 switch (pde & PTE_ENTRYTYPE_MASK) {
130 case 0: /* Invalid */
132 case 2: /* L0 PTE, maybe should not happen? */
133 case 3: /* Reserved */
136 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
137 pde = ldl_phys(pde_ptr);
139 switch (pde & PTE_ENTRYTYPE_MASK) {
141 case 0: /* Invalid */
142 return (1 << 8) | (1 << 2);
143 case 3: /* Reserved */
144 return (1 << 8) | (4 << 2);
146 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
147 pde = ldl_phys(pde_ptr);
149 switch (pde & PTE_ENTRYTYPE_MASK) {
151 case 0: /* Invalid */
152 return (2 << 8) | (1 << 2);
153 case 3: /* Reserved */
154 return (2 << 8) | (4 << 2);
156 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
157 pde = ldl_phys(pde_ptr);
159 switch (pde & PTE_ENTRYTYPE_MASK) {
161 case 0: /* Invalid */
162 return (3 << 8) | (1 << 2);
163 case 1: /* PDE, should not happen */
164 case 3: /* Reserved */
165 return (3 << 8) | (4 << 2);
167 virt_addr = address & TARGET_PAGE_MASK;
168 page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
172 virt_addr = address & ~0x3ffff;
173 page_offset = address & 0x3ffff;
177 virt_addr = address & ~0xffffff;
178 page_offset = address & 0xffffff;
182 /* update page modified and dirty bits */
183 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
184 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
185 pde |= PG_ACCESSED_MASK;
187 pde |= PG_MODIFIED_MASK;
188 stl_phys_notdirty(pde_ptr, pde);
191 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
192 error_code = access_table[*access_index][access_perms];
193 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
196 /* the page can be put in the TLB */
197 *prot = perm_table[is_user][access_perms];
198 if (!(pde & PG_MODIFIED_MASK)) {
199 /* only set write access if already dirty... otherwise wait
201 *prot &= ~PAGE_WRITE;
204 /* Even if large ptes, we map only one 4KB page in the cache to
205 avoid filling it too fast */
206 *physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
210 /* Perform address translation */
211 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
212 int is_user, int is_softmmu)
214 target_phys_addr_t paddr;
216 int error_code = 0, prot, ret = 0, access_index;
218 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
219 if (error_code == 0) {
220 vaddr = address & TARGET_PAGE_MASK;
221 paddr &= TARGET_PAGE_MASK;
223 printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
225 ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
229 if (env->mmuregs[3]) /* Fault status register */
230 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
231 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
232 env->mmuregs[4] = address; /* Fault address register */
234 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
235 // No fault mode: if a mapping is available, just override
236 // permissions. If no mapping is available, redirect accesses to
237 // neverland. Fake/overridden mappings will be flushed when
238 // switching to normal mode.
239 vaddr = address & TARGET_PAGE_MASK;
240 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
241 ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
245 env->exception_index = TT_TFAULT;
247 env->exception_index = TT_DFAULT;
252 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
254 target_phys_addr_t pde_ptr;
257 /* Context base + context number */
258 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
259 pde = ldl_phys(pde_ptr);
261 switch (pde & PTE_ENTRYTYPE_MASK) {
263 case 0: /* Invalid */
264 case 2: /* PTE, maybe should not happen? */
265 case 3: /* Reserved */
270 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
271 pde = ldl_phys(pde_ptr);
273 switch (pde & PTE_ENTRYTYPE_MASK) {
275 case 0: /* Invalid */
276 case 3: /* Reserved */
283 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
284 pde = ldl_phys(pde_ptr);
286 switch (pde & PTE_ENTRYTYPE_MASK) {
288 case 0: /* Invalid */
289 case 3: /* Reserved */
296 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
297 pde = ldl_phys(pde_ptr);
299 switch (pde & PTE_ENTRYTYPE_MASK) {
301 case 0: /* Invalid */
302 case 1: /* PDE, should not happen */
303 case 3: /* Reserved */
315 void dump_mmu(CPUState *env)
317 target_ulong va, va1, va2;
318 unsigned int n, m, o;
319 target_phys_addr_t pde_ptr, pa;
322 printf("MMU dump:\n");
323 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
324 pde = ldl_phys(pde_ptr);
325 printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
326 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
327 pde_ptr = mmu_probe(env, va, 2);
329 pa = cpu_get_phys_page_debug(env, va);
330 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
331 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
332 pde_ptr = mmu_probe(env, va1, 1);
334 pa = cpu_get_phys_page_debug(env, va1);
335 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
336 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
337 pde_ptr = mmu_probe(env, va2, 0);
339 pa = cpu_get_phys_page_debug(env, va2);
340 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
347 printf("MMU dump ends\n");
349 #endif /* DEBUG_MMU */
351 #else /* !TARGET_SPARC64 */
353 * UltraSparc IIi I/DMMUs
355 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
356 int *access_index, target_ulong address, int rw,
362 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
364 *prot = PAGE_READ | PAGE_WRITE;
368 for (i = 0; i < 64; i++) {
369 switch ((env->dtlb_tte[i] >> 61) & 3) {
372 mask = 0xffffffffffffe000ULL;
375 mask = 0xffffffffffff0000ULL;
378 mask = 0xfffffffffff80000ULL;
381 mask = 0xffffffffffc00000ULL;
384 // ctx match, vaddr match?
385 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
386 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
388 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
389 ((env->dtlb_tte[i] & 0x4) && is_user) ||
390 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
391 if (env->dmmuregs[3]) /* Fault status register */
392 env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
393 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
394 env->dmmuregs[4] = address; /* Fault address register */
395 env->exception_index = TT_DFAULT;
397 printf("DFAULT at 0x%" PRIx64 "\n", address);
401 *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
403 if (env->dtlb_tte[i] & 0x2)
409 printf("DMISS at 0x%" PRIx64 "\n", address);
411 env->exception_index = TT_DMISS;
415 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
416 int *access_index, target_ulong address, int rw,
422 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
428 for (i = 0; i < 64; i++) {
429 switch ((env->itlb_tte[i] >> 61) & 3) {
432 mask = 0xffffffffffffe000ULL;
435 mask = 0xffffffffffff0000ULL;
438 mask = 0xfffffffffff80000ULL;
441 mask = 0xffffffffffc00000ULL;
444 // ctx match, vaddr match?
445 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
446 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
448 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
449 ((env->itlb_tte[i] & 0x4) && is_user)) {
450 if (env->immuregs[3]) /* Fault status register */
451 env->immuregs[3] = 2; /* overflow (not read before another fault) */
452 env->immuregs[3] |= (is_user << 3) | 1;
453 env->exception_index = TT_TFAULT;
455 printf("TFAULT at 0x%" PRIx64 "\n", address);
459 *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
465 printf("TMISS at 0x%" PRIx64 "\n", address);
467 env->exception_index = TT_TMISS;
471 int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
472 int *access_index, target_ulong address, int rw,
476 return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
478 return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
481 /* Perform address translation */
482 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
483 int is_user, int is_softmmu)
485 target_ulong virt_addr, vaddr;
486 target_phys_addr_t paddr;
487 int error_code = 0, prot, ret = 0, access_index;
489 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
490 if (error_code == 0) {
491 virt_addr = address & TARGET_PAGE_MASK;
492 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
494 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
496 ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
504 void dump_mmu(CPUState *env)
509 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
510 if ((env->lsu & DMMU_E) == 0) {
511 printf("DMMU disabled\n");
513 printf("DMMU dump:\n");
514 for (i = 0; i < 64; i++) {
515 switch ((env->dtlb_tte[i] >> 61) & 3) {
530 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
531 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
532 env->dtlb_tag[i] & ~0x1fffULL,
533 env->dtlb_tte[i] & 0x1ffffffe000ULL,
535 env->dtlb_tte[i] & 0x4? "priv": "user",
536 env->dtlb_tte[i] & 0x2? "RW": "RO",
537 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
538 env->dtlb_tag[i] & 0x1fffULL);
542 if ((env->lsu & IMMU_E) == 0) {
543 printf("IMMU disabled\n");
545 printf("IMMU dump:\n");
546 for (i = 0; i < 64; i++) {
547 switch ((env->itlb_tte[i] >> 61) & 3) {
562 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
563 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
564 env->itlb_tag[i] & ~0x1fffULL,
565 env->itlb_tte[i] & 0x1ffffffe000ULL,
567 env->itlb_tte[i] & 0x4? "priv": "user",
568 env->itlb_tte[i] & 0x40? "locked": "unlocked",
569 env->itlb_tag[i] & 0x1fffULL);
574 #endif /* DEBUG_MMU */
576 #endif /* TARGET_SPARC64 */
577 #endif /* !CONFIG_USER_ONLY */
579 void memcpy32(target_ulong *dst, const target_ulong *src)