6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 12 /* XXX */
18 #include "softfloat.h"
20 #define TARGET_HAS_ICE 1
22 #if !defined(TARGET_SPARC64)
23 #define ELF_MACHINE EM_SPARC
25 #define ELF_MACHINE EM_SPARCV9
28 /*#define EXCP_INTERRUPT 0x100*/
30 /* trap definitions */
31 #ifndef TARGET_SPARC64
32 #define TT_TFAULT 0x01
33 #define TT_ILL_INSN 0x02
34 #define TT_PRIV_INSN 0x03
35 #define TT_NFPU_INSN 0x04
36 #define TT_WIN_OVF 0x05
37 #define TT_WIN_UNF 0x06
38 #define TT_UNALIGNED 0x07
39 #define TT_FP_EXCP 0x08
40 #define TT_DFAULT 0x09
42 #define TT_EXTINT 0x10
43 #define TT_DIV_ZERO 0x2a
44 #define TT_NCP_INSN 0x24
47 #define TT_TFAULT 0x08
49 #define TT_ILL_INSN 0x10
50 #define TT_PRIV_INSN 0x11
51 #define TT_NFPU_INSN 0x20
52 #define TT_FP_EXCP 0x21
54 #define TT_CLRWIN 0x24
55 #define TT_DIV_ZERO 0x28
56 #define TT_DFAULT 0x30
59 #define TT_UNALIGNED 0x34
60 #define TT_PRIV_ACT 0x37
61 #define TT_EXTINT 0x40
64 #define TT_WOTHER 0x10
68 #define PSR_NEG (1<<23)
69 #define PSR_ZERO (1<<22)
70 #define PSR_OVF (1<<21)
71 #define PSR_CARRY (1<<20)
72 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
73 #define PSR_EF (1<<12)
80 /* Trap base register */
81 #define TBR_BASE_MASK 0xfffff000
83 #if defined(TARGET_SPARC64)
89 #define PS_PRIV (1<<2)
93 #define FPRS_FEF (1<<2)
97 #define FSR_RD1 (1<<31)
98 #define FSR_RD0 (1<<30)
99 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
100 #define FSR_RD_NEAREST 0
101 #define FSR_RD_ZERO FSR_RD0
102 #define FSR_RD_POS FSR_RD1
103 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
105 #define FSR_NVM (1<<27)
106 #define FSR_OFM (1<<26)
107 #define FSR_UFM (1<<25)
108 #define FSR_DZM (1<<24)
109 #define FSR_NXM (1<<23)
110 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
112 #define FSR_NVA (1<<9)
113 #define FSR_OFA (1<<8)
114 #define FSR_UFA (1<<7)
115 #define FSR_DZA (1<<6)
116 #define FSR_NXA (1<<5)
117 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
119 #define FSR_NVC (1<<4)
120 #define FSR_OFC (1<<3)
121 #define FSR_UFC (1<<2)
122 #define FSR_DZC (1<<1)
123 #define FSR_NXC (1<<0)
124 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
126 #define FSR_FTT2 (1<<16)
127 #define FSR_FTT1 (1<<15)
128 #define FSR_FTT0 (1<<14)
129 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
130 #define FSR_FTT_IEEE_EXCP (1 << 14)
131 #define FSR_FTT_UNIMPFPOP (3 << 14)
132 #define FSR_FTT_SEQ_ERROR (4 << 14)
133 #define FSR_FTT_INVAL_FPR (6 << 14)
135 #define FSR_FCC1 (1<<11)
136 #define FSR_FCC0 (1<<10)
140 #define MMU_NF (1<<1)
142 #define PTE_ENTRYTYPE_MASK 3
143 #define PTE_ACCESS_MASK 0x1c
144 #define PTE_ACCESS_SHIFT 2
145 #define PTE_PPN_SHIFT 7
146 #define PTE_ADDR_MASK 0xffffff00
148 #define PG_ACCESSED_BIT 5
149 #define PG_MODIFIED_BIT 6
150 #define PG_CACHE_BIT 7
152 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
153 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
154 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
156 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
159 typedef struct sparc_def_t sparc_def_t;
161 typedef struct CPUSPARCState {
162 target_ulong gregs[8]; /* general registers */
163 target_ulong *regwptr; /* pointer to current register window */
164 float32 fpr[TARGET_FPREGS]; /* floating point registers */
165 target_ulong pc; /* program counter */
166 target_ulong npc; /* next program counter */
167 target_ulong y; /* multiply/divide register */
168 uint32_t psr; /* processor state register */
169 target_ulong fsr; /* FPU state register */
170 uint32_t cwp; /* index of current register window (extracted
172 uint32_t wim; /* window invalid mask */
173 target_ulong tbr; /* trap base register */
174 int psrs; /* supervisor mode (extracted from PSR) */
175 int psrps; /* previous supervisor mode */
176 int psret; /* enable traps */
177 uint32_t psrpil; /* interrupt level */
178 int psref; /* enable fpu */
179 target_ulong version;
184 int interrupt_request;
186 /* NOTE: we allow 8 more registers to handle wrapping */
187 target_ulong regbase[NWINDOWS * 16 + 8];
192 #if defined(TARGET_SPARC64)
196 uint64_t immuregs[16];
197 uint64_t dmmuregs[16];
198 uint64_t itlb_tag[64];
199 uint64_t itlb_tte[64];
200 uint64_t dtlb_tag[64];
201 uint64_t dtlb_tte[64];
203 uint32_t mmuregs[16];
205 /* temporary float registers */
208 float_status fp_status;
209 #if defined(TARGET_SPARC64)
213 uint64_t tnpc[MAXTL];
214 uint64_t tstate[MAXTL];
216 uint32_t xcc; /* Extended integer condition codes */
220 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
221 uint64_t agregs[8]; /* alternate general registers */
222 uint64_t bgregs[8]; /* backup for normal global registers */
223 uint64_t igregs[8]; /* interrupt general registers */
224 uint64_t mgregs[8]; /* mmu general registers */
226 uint64_t tick_cmpr, stick_cmpr;
229 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
233 #if defined(TARGET_SPARC64)
234 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
235 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
236 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
238 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
239 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
240 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
243 #define GET_FSR32(env) (env->fsr)
244 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
245 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
249 CPUSPARCState *cpu_sparc_init(void);
250 int cpu_sparc_exec(CPUSPARCState *s);
251 int cpu_sparc_close(CPUSPARCState *s);
252 int sparc_find_by_name (const unsigned char *name, const sparc_def_t **def);
253 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
255 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
257 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
258 (env->psref? PSR_EF : 0) | \
259 (env->psrpil << 8) | \
260 (env->psrs? PSR_S : 0) | \
261 (env->psrps? PSR_PS : 0) | \
262 (env->psret? PSR_ET : 0) | env->cwp)
264 #ifndef NO_CPU_IO_DEFS
265 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
268 #define PUT_PSR(env, val) do { int _tmp = val; \
269 env->psr = _tmp & PSR_ICC; \
270 env->psref = (_tmp & PSR_EF)? 1 : 0; \
271 env->psrpil = (_tmp & PSR_PIL) >> 8; \
272 env->psrs = (_tmp & PSR_S)? 1 : 0; \
273 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
274 env->psret = (_tmp & PSR_ET)? 1 : 0; \
275 cpu_set_cwp(env, _tmp & PSR_CWP); \
278 #ifdef TARGET_SPARC64
279 #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
280 #define PUT_CCR(env, val) do { int _tmp = val; \
281 env->xcc = _tmp >> 4; \
282 env->psr = (_tmp & 0xf) << 20; \
286 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);