2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 //#define DO_SINGLE_STEP
31 //#define PPC_DEBUG_DISAS
33 #ifdef USE_DIRECT_JUMP
36 #define TBPARAM(x) (long)(x)
40 #define DEF(s, n, copy_size) INDEX_op_ ## s,
46 static uint16_t *gen_opc_ptr;
47 static uint32_t *gen_opparam_ptr;
51 #define GEN8(func, NAME) \
52 static GenOpFunc *NAME ## _table [8] = { \
53 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
54 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
56 static inline void func(int n) \
58 NAME ## _table[n](); \
61 #define GEN16(func, NAME) \
62 static GenOpFunc *NAME ## _table [16] = { \
63 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
64 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
65 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
66 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
68 static inline void func(int n) \
70 NAME ## _table[n](); \
73 #define GEN32(func, NAME) \
74 static GenOpFunc *NAME ## _table [32] = { \
75 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
76 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
77 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
78 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
79 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
80 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
81 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
82 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
84 static inline void func(int n) \
86 NAME ## _table[n](); \
89 /* Condition register moves */
90 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
91 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
92 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
93 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
95 /* Floating point condition and status register moves */
96 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
97 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
98 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
99 static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
100 &gen_op_store_T0_fpscri_fpscr0,
101 &gen_op_store_T0_fpscri_fpscr1,
102 &gen_op_store_T0_fpscri_fpscr2,
103 &gen_op_store_T0_fpscri_fpscr3,
104 &gen_op_store_T0_fpscri_fpscr4,
105 &gen_op_store_T0_fpscri_fpscr5,
106 &gen_op_store_T0_fpscri_fpscr6,
107 &gen_op_store_T0_fpscri_fpscr7,
109 static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
111 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
114 /* Segment register moves */
115 GEN16(gen_op_load_sr, gen_op_load_sr);
116 GEN16(gen_op_store_sr, gen_op_store_sr);
118 /* General purpose registers moves */
119 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
120 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
121 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
123 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
124 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
125 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
127 /* floating point registers moves */
128 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
129 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
130 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
131 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
132 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
133 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
135 static uint8_t spr_access[1024 / 2];
137 /* internal defines */
138 typedef struct DisasContext {
139 struct TranslationBlock *tb;
143 /* Routine used to access memory */
145 /* Translation flags */
146 #if !defined(CONFIG_USER_ONLY)
150 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
151 int singlestep_enabled;
154 struct opc_handler_t {
157 /* instruction type */
160 void (*handler)(DisasContext *ctx);
163 #define RET_EXCP(ctx, excp, error) \
165 if ((ctx)->exception == EXCP_NONE) { \
166 gen_op_update_nip((ctx)->nip); \
168 gen_op_raise_exception_err((excp), (error)); \
169 ctx->exception = (excp); \
172 #define RET_INVAL(ctx) \
173 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
175 #define RET_PRIVOPC(ctx) \
176 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
178 #define RET_PRIVREG(ctx) \
179 RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
181 /* Stop translation */
182 static inline void RET_STOP (DisasContext *ctx)
184 gen_op_update_nip((ctx)->nip);
185 ctx->exception = EXCP_MTMSR;
188 /* No need to update nip here, as execution flow will change */
189 static inline void RET_CHG_FLOW (DisasContext *ctx)
191 ctx->exception = EXCP_MTMSR;
194 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
195 static void gen_##name (DisasContext *ctx); \
196 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
197 static void gen_##name (DisasContext *ctx)
199 typedef struct opcode_t {
200 unsigned char opc1, opc2, opc3;
201 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
202 unsigned char pad[5];
204 unsigned char pad[1];
206 opc_handler_t handler;
207 const unsigned char *oname;
210 /*** Instruction decoding ***/
211 #define EXTRACT_HELPER(name, shift, nb) \
212 static inline uint32_t name (uint32_t opcode) \
214 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
217 #define EXTRACT_SHELPER(name, shift, nb) \
218 static inline int32_t name (uint32_t opcode) \
220 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
224 EXTRACT_HELPER(opc1, 26, 6);
226 EXTRACT_HELPER(opc2, 1, 5);
228 EXTRACT_HELPER(opc3, 6, 5);
229 /* Update Cr0 flags */
230 EXTRACT_HELPER(Rc, 0, 1);
232 EXTRACT_HELPER(rD, 21, 5);
234 EXTRACT_HELPER(rS, 21, 5);
236 EXTRACT_HELPER(rA, 16, 5);
238 EXTRACT_HELPER(rB, 11, 5);
240 EXTRACT_HELPER(rC, 6, 5);
242 EXTRACT_HELPER(crfD, 23, 3);
243 EXTRACT_HELPER(crfS, 18, 3);
244 EXTRACT_HELPER(crbD, 21, 5);
245 EXTRACT_HELPER(crbA, 16, 5);
246 EXTRACT_HELPER(crbB, 11, 5);
248 EXTRACT_HELPER(_SPR, 11, 10);
249 static inline uint32_t SPR (uint32_t opcode)
251 uint32_t sprn = _SPR(opcode);
253 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
255 /*** Get constants ***/
256 EXTRACT_HELPER(IMM, 12, 8);
257 /* 16 bits signed immediate value */
258 EXTRACT_SHELPER(SIMM, 0, 16);
259 /* 16 bits unsigned immediate value */
260 EXTRACT_HELPER(UIMM, 0, 16);
262 EXTRACT_HELPER(NB, 11, 5);
264 EXTRACT_HELPER(SH, 11, 5);
266 EXTRACT_HELPER(MB, 6, 5);
268 EXTRACT_HELPER(ME, 1, 5);
270 EXTRACT_HELPER(TO, 21, 5);
272 EXTRACT_HELPER(CRM, 12, 8);
273 EXTRACT_HELPER(FM, 17, 8);
274 EXTRACT_HELPER(SR, 16, 4);
275 EXTRACT_HELPER(FPIMM, 20, 4);
277 /*** Jump target decoding ***/
279 EXTRACT_SHELPER(d, 0, 16);
280 /* Immediate address */
281 static inline uint32_t LI (uint32_t opcode)
283 return (opcode >> 0) & 0x03FFFFFC;
286 static inline uint32_t BD (uint32_t opcode)
288 return (opcode >> 0) & 0xFFFC;
291 EXTRACT_HELPER(BO, 21, 5);
292 EXTRACT_HELPER(BI, 16, 5);
293 /* Absolute/relative address */
294 EXTRACT_HELPER(AA, 1, 1);
296 EXTRACT_HELPER(LK, 0, 1);
298 /* Create a mask between <start> and <end> bits */
299 static inline uint32_t MASK (uint32_t start, uint32_t end)
303 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
310 #if HOST_LONG_BITS == 64
315 #if defined(__APPLE__)
316 #define OPCODES_SECTION \
317 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
319 #define OPCODES_SECTION \
320 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
323 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
324 OPCODES_SECTION opcode_t opc_##name = { \
332 .handler = &gen_##name, \
334 .oname = stringify(name), \
337 #define GEN_OPCODE_MARK(name) \
338 OPCODES_SECTION opcode_t opc_##name = { \
344 .inval = 0x00000000, \
348 .oname = stringify(name), \
351 /* Start opcode list */
352 GEN_OPCODE_MARK(start);
354 /* Invalid instruction */
355 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
360 static opc_handler_t invalid_handler = {
363 .handler = gen_invalid,
366 /*** Integer arithmetic ***/
367 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
368 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
370 gen_op_load_gpr_T0(rA(ctx->opcode)); \
371 gen_op_load_gpr_T1(rB(ctx->opcode)); \
373 if (Rc(ctx->opcode) != 0) \
375 gen_op_store_T0_gpr(rD(ctx->opcode)); \
378 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
379 GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
381 gen_op_load_gpr_T0(rA(ctx->opcode)); \
382 gen_op_load_gpr_T1(rB(ctx->opcode)); \
384 if (Rc(ctx->opcode) != 0) \
386 gen_op_store_T0_gpr(rD(ctx->opcode)); \
389 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
390 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
392 gen_op_load_gpr_T0(rA(ctx->opcode)); \
394 if (Rc(ctx->opcode) != 0) \
396 gen_op_store_T0_gpr(rD(ctx->opcode)); \
398 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
399 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
401 gen_op_load_gpr_T0(rA(ctx->opcode)); \
403 if (Rc(ctx->opcode) != 0) \
405 gen_op_store_T0_gpr(rD(ctx->opcode)); \
408 /* Two operands arithmetic functions */
409 #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
410 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
411 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
413 /* Two operands arithmetic functions with no overflow allowed */
414 #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
415 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
417 /* One operand arithmetic functions */
418 #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
419 __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
420 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
422 /* add add. addo addo. */
423 GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
424 /* addc addc. addco addco. */
425 GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
426 /* adde adde. addeo addeo. */
427 GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
428 /* addme addme. addmeo addmeo. */
429 GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
430 /* addze addze. addzeo addzeo. */
431 GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
432 /* divw divw. divwo divwo. */
433 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
434 /* divwu divwu. divwuo divwuo. */
435 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
437 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
439 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
440 /* mullw mullw. mullwo mullwo. */
441 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
442 /* neg neg. nego nego. */
443 GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
444 /* subf subf. subfo subfo. */
445 GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
446 /* subfc subfc. subfco subfco. */
447 GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
448 /* subfe subfe. subfeo subfeo. */
449 GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
450 /* subfme subfme. subfmeo subfmeo. */
451 GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
452 /* subfze subfze. subfzeo subfzeo. */
453 GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
455 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
457 int32_t simm = SIMM(ctx->opcode);
459 if (rA(ctx->opcode) == 0) {
462 gen_op_load_gpr_T0(rA(ctx->opcode));
465 gen_op_store_T0_gpr(rD(ctx->opcode));
468 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
470 gen_op_load_gpr_T0(rA(ctx->opcode));
471 gen_op_addic(SIMM(ctx->opcode));
472 gen_op_store_T0_gpr(rD(ctx->opcode));
475 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
477 gen_op_load_gpr_T0(rA(ctx->opcode));
478 gen_op_addic(SIMM(ctx->opcode));
480 gen_op_store_T0_gpr(rD(ctx->opcode));
483 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
485 int32_t simm = SIMM(ctx->opcode);
487 if (rA(ctx->opcode) == 0) {
488 gen_op_set_T0(simm << 16);
490 gen_op_load_gpr_T0(rA(ctx->opcode));
491 gen_op_addi(simm << 16);
493 gen_op_store_T0_gpr(rD(ctx->opcode));
496 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
498 gen_op_load_gpr_T0(rA(ctx->opcode));
499 gen_op_mulli(SIMM(ctx->opcode));
500 gen_op_store_T0_gpr(rD(ctx->opcode));
503 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
505 gen_op_load_gpr_T0(rA(ctx->opcode));
506 gen_op_subfic(SIMM(ctx->opcode));
507 gen_op_store_T0_gpr(rD(ctx->opcode));
510 /*** Integer comparison ***/
511 #define GEN_CMP(name, opc) \
512 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
514 gen_op_load_gpr_T0(rA(ctx->opcode)); \
515 gen_op_load_gpr_T1(rB(ctx->opcode)); \
517 gen_op_store_T0_crf(crfD(ctx->opcode)); \
523 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
525 gen_op_load_gpr_T0(rA(ctx->opcode));
526 gen_op_cmpi(SIMM(ctx->opcode));
527 gen_op_store_T0_crf(crfD(ctx->opcode));
532 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
534 gen_op_load_gpr_T0(rA(ctx->opcode));
535 gen_op_cmpli(UIMM(ctx->opcode));
536 gen_op_store_T0_crf(crfD(ctx->opcode));
539 /*** Integer logical ***/
540 #define __GEN_LOGICAL2(name, opc2, opc3) \
541 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
543 gen_op_load_gpr_T0(rS(ctx->opcode)); \
544 gen_op_load_gpr_T1(rB(ctx->opcode)); \
546 if (Rc(ctx->opcode) != 0) \
548 gen_op_store_T0_gpr(rA(ctx->opcode)); \
550 #define GEN_LOGICAL2(name, opc) \
551 __GEN_LOGICAL2(name, 0x1C, opc)
553 #define GEN_LOGICAL1(name, opc) \
554 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
556 gen_op_load_gpr_T0(rS(ctx->opcode)); \
558 if (Rc(ctx->opcode) != 0) \
560 gen_op_store_T0_gpr(rA(ctx->opcode)); \
564 GEN_LOGICAL2(and, 0x00);
566 GEN_LOGICAL2(andc, 0x01);
568 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
570 gen_op_load_gpr_T0(rS(ctx->opcode));
571 gen_op_andi_(UIMM(ctx->opcode));
573 gen_op_store_T0_gpr(rA(ctx->opcode));
576 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
578 gen_op_load_gpr_T0(rS(ctx->opcode));
579 gen_op_andi_(UIMM(ctx->opcode) << 16);
581 gen_op_store_T0_gpr(rA(ctx->opcode));
585 GEN_LOGICAL1(cntlzw, 0x00);
587 GEN_LOGICAL2(eqv, 0x08);
589 GEN_LOGICAL1(extsb, 0x1D);
591 GEN_LOGICAL1(extsh, 0x1C);
593 GEN_LOGICAL2(nand, 0x0E);
595 GEN_LOGICAL2(nor, 0x03);
598 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
600 gen_op_load_gpr_T0(rS(ctx->opcode));
601 /* Optimisation for mr case */
602 if (rS(ctx->opcode) != rB(ctx->opcode)) {
603 gen_op_load_gpr_T1(rB(ctx->opcode));
606 if (Rc(ctx->opcode) != 0)
608 gen_op_store_T0_gpr(rA(ctx->opcode));
612 GEN_LOGICAL2(orc, 0x0C);
614 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
616 gen_op_load_gpr_T0(rS(ctx->opcode));
617 /* Optimisation for "set to zero" case */
618 if (rS(ctx->opcode) != rB(ctx->opcode)) {
619 gen_op_load_gpr_T1(rB(ctx->opcode));
624 if (Rc(ctx->opcode) != 0)
626 gen_op_store_T0_gpr(rA(ctx->opcode));
629 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
631 uint32_t uimm = UIMM(ctx->opcode);
633 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
637 gen_op_load_gpr_T0(rS(ctx->opcode));
640 gen_op_store_T0_gpr(rA(ctx->opcode));
643 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
645 uint32_t uimm = UIMM(ctx->opcode);
647 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
651 gen_op_load_gpr_T0(rS(ctx->opcode));
653 gen_op_ori(uimm << 16);
654 gen_op_store_T0_gpr(rA(ctx->opcode));
657 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
659 uint32_t uimm = UIMM(ctx->opcode);
661 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
665 gen_op_load_gpr_T0(rS(ctx->opcode));
668 gen_op_store_T0_gpr(rA(ctx->opcode));
672 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
674 uint32_t uimm = UIMM(ctx->opcode);
676 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
680 gen_op_load_gpr_T0(rS(ctx->opcode));
682 gen_op_xori(uimm << 16);
683 gen_op_store_T0_gpr(rA(ctx->opcode));
686 /*** Integer rotate ***/
687 /* rlwimi & rlwimi. */
688 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
692 mb = MB(ctx->opcode);
693 me = ME(ctx->opcode);
694 gen_op_load_gpr_T0(rS(ctx->opcode));
695 gen_op_load_gpr_T1(rA(ctx->opcode));
696 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
697 if (Rc(ctx->opcode) != 0)
699 gen_op_store_T0_gpr(rA(ctx->opcode));
701 /* rlwinm & rlwinm. */
702 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
706 sh = SH(ctx->opcode);
707 mb = MB(ctx->opcode);
708 me = ME(ctx->opcode);
709 gen_op_load_gpr_T0(rS(ctx->opcode));
712 gen_op_andi_(MASK(mb, me));
721 } else if (me == (31 - sh)) {
726 } else if (me == 31) {
728 if (sh == (32 - mb)) {
734 gen_op_rlwinm(sh, MASK(mb, me));
736 if (Rc(ctx->opcode) != 0)
738 gen_op_store_T0_gpr(rA(ctx->opcode));
741 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
745 mb = MB(ctx->opcode);
746 me = ME(ctx->opcode);
747 gen_op_load_gpr_T0(rS(ctx->opcode));
748 gen_op_load_gpr_T1(rB(ctx->opcode));
749 if (mb == 0 && me == 31) {
753 gen_op_rlwnm(MASK(mb, me));
755 if (Rc(ctx->opcode) != 0)
757 gen_op_store_T0_gpr(rA(ctx->opcode));
760 /*** Integer shift ***/
762 __GEN_LOGICAL2(slw, 0x18, 0x00);
764 __GEN_LOGICAL2(sraw, 0x18, 0x18);
766 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
768 gen_op_load_gpr_T0(rS(ctx->opcode));
769 if (SH(ctx->opcode) != 0)
770 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
771 if (Rc(ctx->opcode) != 0)
773 gen_op_store_T0_gpr(rA(ctx->opcode));
776 __GEN_LOGICAL2(srw, 0x18, 0x10);
778 /*** Floating-Point arithmetic ***/
779 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
780 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
782 if (!ctx->fpu_enabled) { \
783 RET_EXCP(ctx, EXCP_NO_FP, 0); \
786 gen_op_reset_scrfx(); \
787 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
788 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
789 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
794 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
795 if (Rc(ctx->opcode)) \
799 #define GEN_FLOAT_ACB(name, op2) \
800 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
801 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
803 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
804 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
806 if (!ctx->fpu_enabled) { \
807 RET_EXCP(ctx, EXCP_NO_FP, 0); \
810 gen_op_reset_scrfx(); \
811 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
812 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
817 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
818 if (Rc(ctx->opcode)) \
821 #define GEN_FLOAT_AB(name, op2, inval) \
822 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
823 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
825 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
826 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
828 if (!ctx->fpu_enabled) { \
829 RET_EXCP(ctx, EXCP_NO_FP, 0); \
832 gen_op_reset_scrfx(); \
833 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
834 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
839 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
840 if (Rc(ctx->opcode)) \
843 #define GEN_FLOAT_AC(name, op2, inval) \
844 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
845 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
847 #define GEN_FLOAT_B(name, op2, op3) \
848 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
850 if (!ctx->fpu_enabled) { \
851 RET_EXCP(ctx, EXCP_NO_FP, 0); \
854 gen_op_reset_scrfx(); \
855 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
857 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
858 if (Rc(ctx->opcode)) \
862 #define GEN_FLOAT_BS(name, op1, op2) \
863 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
865 if (!ctx->fpu_enabled) { \
866 RET_EXCP(ctx, EXCP_NO_FP, 0); \
869 gen_op_reset_scrfx(); \
870 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
872 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
873 if (Rc(ctx->opcode)) \
878 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
880 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
882 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
885 GEN_FLOAT_BS(res, 0x3B, 0x18);
888 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
891 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
893 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
896 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
898 if (!ctx->fpu_enabled) {
899 RET_EXCP(ctx, EXCP_NO_FP, 0);
902 gen_op_reset_scrfx();
903 gen_op_load_fpr_FT0(rB(ctx->opcode));
905 gen_op_store_FT0_fpr(rD(ctx->opcode));
910 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
912 if (!ctx->fpu_enabled) {
913 RET_EXCP(ctx, EXCP_NO_FP, 0);
916 gen_op_reset_scrfx();
917 gen_op_load_fpr_FT0(rB(ctx->opcode));
920 gen_op_store_FT0_fpr(rD(ctx->opcode));
925 /*** Floating-Point multiply-and-add ***/
927 GEN_FLOAT_ACB(madd, 0x1D);
929 GEN_FLOAT_ACB(msub, 0x1C);
930 /* fnmadd - fnmadds */
931 GEN_FLOAT_ACB(nmadd, 0x1F);
932 /* fnmsub - fnmsubs */
933 GEN_FLOAT_ACB(nmsub, 0x1E);
935 /*** Floating-Point round & convert ***/
937 GEN_FLOAT_B(ctiw, 0x0E, 0x00);
939 GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
941 GEN_FLOAT_B(rsp, 0x0C, 0x00);
943 /*** Floating-Point compare ***/
945 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
947 if (!ctx->fpu_enabled) {
948 RET_EXCP(ctx, EXCP_NO_FP, 0);
951 gen_op_reset_scrfx();
952 gen_op_load_fpr_FT0(rA(ctx->opcode));
953 gen_op_load_fpr_FT1(rB(ctx->opcode));
955 gen_op_store_T0_crf(crfD(ctx->opcode));
959 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
961 if (!ctx->fpu_enabled) {
962 RET_EXCP(ctx, EXCP_NO_FP, 0);
965 gen_op_reset_scrfx();
966 gen_op_load_fpr_FT0(rA(ctx->opcode));
967 gen_op_load_fpr_FT1(rB(ctx->opcode));
969 gen_op_store_T0_crf(crfD(ctx->opcode));
972 /*** Floating-point move ***/
974 GEN_FLOAT_B(abs, 0x08, 0x08);
977 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
979 if (!ctx->fpu_enabled) {
980 RET_EXCP(ctx, EXCP_NO_FP, 0);
983 gen_op_reset_scrfx();
984 gen_op_load_fpr_FT0(rB(ctx->opcode));
985 gen_op_store_FT0_fpr(rD(ctx->opcode));
991 GEN_FLOAT_B(nabs, 0x08, 0x04);
993 GEN_FLOAT_B(neg, 0x08, 0x01);
995 /*** Floating-Point status & ctrl register ***/
997 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
999 if (!ctx->fpu_enabled) {
1000 RET_EXCP(ctx, EXCP_NO_FP, 0);
1003 gen_op_load_fpscr_T0(crfS(ctx->opcode));
1004 gen_op_store_T0_crf(crfD(ctx->opcode));
1005 gen_op_clear_fpscr(crfS(ctx->opcode));
1009 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1011 if (!ctx->fpu_enabled) {
1012 RET_EXCP(ctx, EXCP_NO_FP, 0);
1015 gen_op_load_fpscr();
1016 gen_op_store_FT0_fpr(rD(ctx->opcode));
1017 if (Rc(ctx->opcode))
1022 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1026 if (!ctx->fpu_enabled) {
1027 RET_EXCP(ctx, EXCP_NO_FP, 0);
1030 crb = crbD(ctx->opcode) >> 2;
1031 gen_op_load_fpscr_T0(crb);
1032 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1033 gen_op_store_T0_fpscr(crb);
1034 if (Rc(ctx->opcode))
1039 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1043 if (!ctx->fpu_enabled) {
1044 RET_EXCP(ctx, EXCP_NO_FP, 0);
1047 crb = crbD(ctx->opcode) >> 2;
1048 gen_op_load_fpscr_T0(crb);
1049 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1050 gen_op_store_T0_fpscr(crb);
1051 if (Rc(ctx->opcode))
1056 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1058 if (!ctx->fpu_enabled) {
1059 RET_EXCP(ctx, EXCP_NO_FP, 0);
1062 gen_op_load_fpr_FT0(rB(ctx->opcode));
1063 gen_op_store_fpscr(FM(ctx->opcode));
1064 if (Rc(ctx->opcode))
1069 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1071 if (!ctx->fpu_enabled) {
1072 RET_EXCP(ctx, EXCP_NO_FP, 0);
1075 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1076 if (Rc(ctx->opcode))
1080 /*** Integer load ***/
1081 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1082 #if defined(CONFIG_USER_ONLY)
1083 #define OP_LD_TABLE(width) \
1084 static GenOpFunc *gen_op_l##width[] = { \
1085 &gen_op_l##width##_raw, \
1086 &gen_op_l##width##_le_raw, \
1088 #define OP_ST_TABLE(width) \
1089 static GenOpFunc *gen_op_st##width[] = { \
1090 &gen_op_st##width##_raw, \
1091 &gen_op_st##width##_le_raw, \
1093 /* Byte access routine are endian safe */
1094 #define gen_op_stb_le_raw gen_op_stb_raw
1095 #define gen_op_lbz_le_raw gen_op_lbz_raw
1097 #define OP_LD_TABLE(width) \
1098 static GenOpFunc *gen_op_l##width[] = { \
1099 &gen_op_l##width##_user, \
1100 &gen_op_l##width##_le_user, \
1101 &gen_op_l##width##_kernel, \
1102 &gen_op_l##width##_le_kernel, \
1104 #define OP_ST_TABLE(width) \
1105 static GenOpFunc *gen_op_st##width[] = { \
1106 &gen_op_st##width##_user, \
1107 &gen_op_st##width##_le_user, \
1108 &gen_op_st##width##_kernel, \
1109 &gen_op_st##width##_le_kernel, \
1111 /* Byte access routine are endian safe */
1112 #define gen_op_stb_le_user gen_op_stb_user
1113 #define gen_op_lbz_le_user gen_op_lbz_user
1114 #define gen_op_stb_le_kernel gen_op_stb_kernel
1115 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
1118 #define GEN_LD(width, opc) \
1119 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1121 uint32_t simm = SIMM(ctx->opcode); \
1122 if (rA(ctx->opcode) == 0) { \
1123 gen_op_set_T0(simm); \
1125 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1127 gen_op_addi(simm); \
1129 op_ldst(l##width); \
1130 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1133 #define GEN_LDU(width, opc) \
1134 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1136 uint32_t simm = SIMM(ctx->opcode); \
1137 if (rA(ctx->opcode) == 0 || \
1138 rA(ctx->opcode) == rD(ctx->opcode)) { \
1142 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1144 gen_op_addi(simm); \
1145 op_ldst(l##width); \
1146 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1150 #define GEN_LDUX(width, opc) \
1151 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1153 if (rA(ctx->opcode) == 0 || \
1154 rA(ctx->opcode) == rD(ctx->opcode)) { \
1158 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1159 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1161 op_ldst(l##width); \
1162 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1163 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1166 #define GEN_LDX(width, opc2, opc3) \
1167 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1169 if (rA(ctx->opcode) == 0) { \
1170 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1172 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1173 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1176 op_ldst(l##width); \
1177 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1180 #define GEN_LDS(width, op) \
1181 OP_LD_TABLE(width); \
1182 GEN_LD(width, op | 0x20); \
1183 GEN_LDU(width, op | 0x21); \
1184 GEN_LDUX(width, op | 0x01); \
1185 GEN_LDX(width, 0x17, op | 0x00)
1187 /* lbz lbzu lbzux lbzx */
1189 /* lha lhau lhaux lhax */
1191 /* lhz lhzu lhzux lhzx */
1193 /* lwz lwzu lwzux lwzx */
1196 /*** Integer store ***/
1197 #define GEN_ST(width, opc) \
1198 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1200 uint32_t simm = SIMM(ctx->opcode); \
1201 if (rA(ctx->opcode) == 0) { \
1202 gen_op_set_T0(simm); \
1204 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1206 gen_op_addi(simm); \
1208 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1209 op_ldst(st##width); \
1212 #define GEN_STU(width, opc) \
1213 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1215 uint32_t simm = SIMM(ctx->opcode); \
1216 if (rA(ctx->opcode) == 0) { \
1220 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1222 gen_op_addi(simm); \
1223 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1224 op_ldst(st##width); \
1225 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1228 #define GEN_STUX(width, opc) \
1229 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1231 if (rA(ctx->opcode) == 0) { \
1235 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1236 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1238 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1239 op_ldst(st##width); \
1240 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1243 #define GEN_STX(width, opc2, opc3) \
1244 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1246 if (rA(ctx->opcode) == 0) { \
1247 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1249 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1250 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1253 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1254 op_ldst(st##width); \
1257 #define GEN_STS(width, op) \
1258 OP_ST_TABLE(width); \
1259 GEN_ST(width, op | 0x20); \
1260 GEN_STU(width, op | 0x21); \
1261 GEN_STUX(width, op | 0x01); \
1262 GEN_STX(width, 0x17, op | 0x00)
1264 /* stb stbu stbux stbx */
1266 /* sth sthu sthux sthx */
1268 /* stw stwu stwux stwx */
1271 /*** Integer load and store with byte reverse ***/
1274 GEN_LDX(hbr, 0x16, 0x18);
1277 GEN_LDX(wbr, 0x16, 0x10);
1280 GEN_STX(hbr, 0x16, 0x1C);
1283 GEN_STX(wbr, 0x16, 0x14);
1285 /*** Integer load and store multiple ***/
1286 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1287 #if defined(CONFIG_USER_ONLY)
1288 static GenOpFunc1 *gen_op_lmw[] = {
1292 static GenOpFunc1 *gen_op_stmw[] = {
1294 &gen_op_stmw_le_raw,
1297 static GenOpFunc1 *gen_op_lmw[] = {
1299 &gen_op_lmw_le_user,
1301 &gen_op_lmw_le_kernel,
1303 static GenOpFunc1 *gen_op_stmw[] = {
1305 &gen_op_stmw_le_user,
1306 &gen_op_stmw_kernel,
1307 &gen_op_stmw_le_kernel,
1312 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1314 int simm = SIMM(ctx->opcode);
1316 if (rA(ctx->opcode) == 0) {
1317 gen_op_set_T0(simm);
1319 gen_op_load_gpr_T0(rA(ctx->opcode));
1323 op_ldstm(lmw, rD(ctx->opcode));
1327 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1329 int simm = SIMM(ctx->opcode);
1331 if (rA(ctx->opcode) == 0) {
1332 gen_op_set_T0(simm);
1334 gen_op_load_gpr_T0(rA(ctx->opcode));
1338 op_ldstm(stmw, rS(ctx->opcode));
1341 /*** Integer load and store strings ***/
1342 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1343 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1344 #if defined(CONFIG_USER_ONLY)
1345 static GenOpFunc1 *gen_op_lswi[] = {
1347 &gen_op_lswi_le_raw,
1349 static GenOpFunc3 *gen_op_lswx[] = {
1351 &gen_op_lswx_le_raw,
1353 static GenOpFunc1 *gen_op_stsw[] = {
1355 &gen_op_stsw_le_raw,
1358 static GenOpFunc1 *gen_op_lswi[] = {
1360 &gen_op_lswi_le_user,
1361 &gen_op_lswi_kernel,
1362 &gen_op_lswi_le_kernel,
1364 static GenOpFunc3 *gen_op_lswx[] = {
1366 &gen_op_lswx_le_user,
1367 &gen_op_lswx_kernel,
1368 &gen_op_lswx_le_kernel,
1370 static GenOpFunc1 *gen_op_stsw[] = {
1372 &gen_op_stsw_le_user,
1373 &gen_op_stsw_kernel,
1374 &gen_op_stsw_le_kernel,
1379 /* PowerPC32 specification says we must generate an exception if
1380 * rA is in the range of registers to be loaded.
1381 * In an other hand, IBM says this is valid, but rA won't be loaded.
1382 * For now, I'll follow the spec...
1384 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1386 int nb = NB(ctx->opcode);
1387 int start = rD(ctx->opcode);
1388 int ra = rA(ctx->opcode);
1394 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1395 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1396 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1402 gen_op_load_gpr_T0(ra);
1405 /* NIP cannot be restored if the memory exception comes from an helper */
1406 gen_op_update_nip((ctx)->nip - 4);
1407 op_ldsts(lswi, start);
1411 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1413 int ra = rA(ctx->opcode);
1414 int rb = rB(ctx->opcode);
1417 gen_op_load_gpr_T0(rb);
1420 gen_op_load_gpr_T0(ra);
1421 gen_op_load_gpr_T1(rb);
1424 gen_op_load_xer_bc();
1425 /* NIP cannot be restored if the memory exception comes from an helper */
1426 gen_op_update_nip((ctx)->nip - 4);
1427 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1431 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1433 int nb = NB(ctx->opcode);
1435 if (rA(ctx->opcode) == 0) {
1438 gen_op_load_gpr_T0(rA(ctx->opcode));
1443 /* NIP cannot be restored if the memory exception comes from an helper */
1444 gen_op_update_nip((ctx)->nip - 4);
1445 op_ldsts(stsw, rS(ctx->opcode));
1449 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1451 int ra = rA(ctx->opcode);
1454 gen_op_load_gpr_T0(rB(ctx->opcode));
1455 ra = rB(ctx->opcode);
1457 gen_op_load_gpr_T0(ra);
1458 gen_op_load_gpr_T1(rB(ctx->opcode));
1461 gen_op_load_xer_bc();
1462 /* NIP cannot be restored if the memory exception comes from an helper */
1463 gen_op_update_nip((ctx)->nip - 4);
1464 op_ldsts(stsw, rS(ctx->opcode));
1467 /*** Memory synchronisation ***/
1469 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1474 GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1478 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1479 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1480 #if defined(CONFIG_USER_ONLY)
1481 static GenOpFunc *gen_op_lwarx[] = {
1483 &gen_op_lwarx_le_raw,
1485 static GenOpFunc *gen_op_stwcx[] = {
1487 &gen_op_stwcx_le_raw,
1490 static GenOpFunc *gen_op_lwarx[] = {
1492 &gen_op_lwarx_le_user,
1493 &gen_op_lwarx_kernel,
1494 &gen_op_lwarx_le_kernel,
1496 static GenOpFunc *gen_op_stwcx[] = {
1498 &gen_op_stwcx_le_user,
1499 &gen_op_stwcx_kernel,
1500 &gen_op_stwcx_le_kernel,
1505 GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1507 if (rA(ctx->opcode) == 0) {
1508 gen_op_load_gpr_T0(rB(ctx->opcode));
1510 gen_op_load_gpr_T0(rA(ctx->opcode));
1511 gen_op_load_gpr_T1(rB(ctx->opcode));
1515 gen_op_store_T1_gpr(rD(ctx->opcode));
1519 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1521 if (rA(ctx->opcode) == 0) {
1522 gen_op_load_gpr_T0(rB(ctx->opcode));
1524 gen_op_load_gpr_T0(rA(ctx->opcode));
1525 gen_op_load_gpr_T1(rB(ctx->opcode));
1528 gen_op_load_gpr_T1(rS(ctx->opcode));
1533 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1537 /*** Floating-point load ***/
1538 #define GEN_LDF(width, opc) \
1539 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1541 uint32_t simm = SIMM(ctx->opcode); \
1542 if (!ctx->fpu_enabled) { \
1543 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1546 if (rA(ctx->opcode) == 0) { \
1547 gen_op_set_T0(simm); \
1549 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1551 gen_op_addi(simm); \
1553 op_ldst(l##width); \
1554 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1557 #define GEN_LDUF(width, opc) \
1558 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1560 uint32_t simm = SIMM(ctx->opcode); \
1561 if (!ctx->fpu_enabled) { \
1562 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1565 if (rA(ctx->opcode) == 0 || \
1566 rA(ctx->opcode) == rD(ctx->opcode)) { \
1570 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1572 gen_op_addi(simm); \
1573 op_ldst(l##width); \
1574 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1575 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1578 #define GEN_LDUXF(width, opc) \
1579 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
1581 if (!ctx->fpu_enabled) { \
1582 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1585 if (rA(ctx->opcode) == 0 || \
1586 rA(ctx->opcode) == rD(ctx->opcode)) { \
1590 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1591 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1593 op_ldst(l##width); \
1594 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1595 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1598 #define GEN_LDXF(width, opc2, opc3) \
1599 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
1601 if (!ctx->fpu_enabled) { \
1602 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1605 if (rA(ctx->opcode) == 0) { \
1606 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1608 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1609 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1612 op_ldst(l##width); \
1613 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1616 #define GEN_LDFS(width, op) \
1617 OP_LD_TABLE(width); \
1618 GEN_LDF(width, op | 0x20); \
1619 GEN_LDUF(width, op | 0x21); \
1620 GEN_LDUXF(width, op | 0x01); \
1621 GEN_LDXF(width, 0x17, op | 0x00)
1623 /* lfd lfdu lfdux lfdx */
1625 /* lfs lfsu lfsux lfsx */
1628 /*** Floating-point store ***/
1629 #define GEN_STF(width, opc) \
1630 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1632 uint32_t simm = SIMM(ctx->opcode); \
1633 if (!ctx->fpu_enabled) { \
1634 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1637 if (rA(ctx->opcode) == 0) { \
1638 gen_op_set_T0(simm); \
1640 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1642 gen_op_addi(simm); \
1644 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1645 op_ldst(st##width); \
1648 #define GEN_STUF(width, opc) \
1649 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1651 uint32_t simm = SIMM(ctx->opcode); \
1652 if (!ctx->fpu_enabled) { \
1653 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1656 if (rA(ctx->opcode) == 0) { \
1660 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1662 gen_op_addi(simm); \
1663 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1664 op_ldst(st##width); \
1665 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1668 #define GEN_STUXF(width, opc) \
1669 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
1671 if (!ctx->fpu_enabled) { \
1672 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1675 if (rA(ctx->opcode) == 0) { \
1679 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1680 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1682 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1683 op_ldst(st##width); \
1684 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1687 #define GEN_STXF(width, opc2, opc3) \
1688 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
1690 if (!ctx->fpu_enabled) { \
1691 RET_EXCP(ctx, EXCP_NO_FP, 0); \
1694 if (rA(ctx->opcode) == 0) { \
1695 gen_op_load_gpr_T0(rB(ctx->opcode)); \
1697 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1698 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1701 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1702 op_ldst(st##width); \
1705 #define GEN_STFS(width, op) \
1706 OP_ST_TABLE(width); \
1707 GEN_STF(width, op | 0x20); \
1708 GEN_STUF(width, op | 0x21); \
1709 GEN_STUXF(width, op | 0x01); \
1710 GEN_STXF(width, 0x17, op | 0x00)
1712 /* stfd stfdu stfdux stfdx */
1714 /* stfs stfsu stfsux stfsx */
1719 GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1721 if (!ctx->fpu_enabled) {
1722 RET_EXCP(ctx, EXCP_NO_FP, 0);
1730 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1732 TranslationBlock *tb;
1734 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1736 gen_op_goto_tb0(TBPARAM(tb));
1738 gen_op_goto_tb1(TBPARAM(tb));
1739 gen_op_set_T1(dest);
1741 gen_op_set_T0((long)tb + n);
1742 if (ctx->singlestep_enabled)
1746 gen_op_set_T1(dest);
1748 if (ctx->singlestep_enabled)
1756 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1758 uint32_t li, target;
1760 /* sign extend LI */
1761 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1763 if (AA(ctx->opcode) == 0)
1764 target = ctx->nip + li - 4;
1767 if (LK(ctx->opcode)) {
1768 gen_op_setlr(ctx->nip);
1770 gen_goto_tb(ctx, 0, target);
1771 ctx->exception = EXCP_BRANCH;
1778 static inline void gen_bcond(DisasContext *ctx, int type)
1780 uint32_t target = 0;
1781 uint32_t bo = BO(ctx->opcode);
1782 uint32_t bi = BI(ctx->opcode);
1786 if ((bo & 0x4) == 0)
1790 li = (int32_t)((int16_t)(BD(ctx->opcode)));
1791 if (AA(ctx->opcode) == 0) {
1792 target = ctx->nip + li - 4;
1798 gen_op_movl_T1_ctr();
1802 gen_op_movl_T1_lr();
1805 if (LK(ctx->opcode)) {
1806 gen_op_setlr(ctx->nip);
1809 /* No CR condition */
1820 if (type == BCOND_IM) {
1821 gen_goto_tb(ctx, 0, target);
1828 mask = 1 << (3 - (bi & 0x03));
1829 gen_op_load_crf_T0(bi >> 2);
1833 gen_op_test_ctr_true(mask);
1836 gen_op_test_ctrz_true(mask);
1841 gen_op_test_true(mask);
1847 gen_op_test_ctr_false(mask);
1850 gen_op_test_ctrz_false(mask);
1855 gen_op_test_false(mask);
1860 if (type == BCOND_IM) {
1861 int l1 = gen_new_label();
1863 gen_goto_tb(ctx, 0, target);
1865 gen_goto_tb(ctx, 1, ctx->nip);
1867 gen_op_btest_T1(ctx->nip);
1870 ctx->exception = EXCP_BRANCH;
1873 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1875 gen_bcond(ctx, BCOND_IM);
1878 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1880 gen_bcond(ctx, BCOND_CTR);
1883 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1885 gen_bcond(ctx, BCOND_LR);
1888 /*** Condition register logical ***/
1889 #define GEN_CRLOGIC(op, opc) \
1890 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1892 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1893 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1894 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1895 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1897 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1898 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1899 3 - (crbD(ctx->opcode) & 0x03)); \
1900 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1904 GEN_CRLOGIC(and, 0x08)
1906 GEN_CRLOGIC(andc, 0x04)
1908 GEN_CRLOGIC(eqv, 0x09)
1910 GEN_CRLOGIC(nand, 0x07)
1912 GEN_CRLOGIC(nor, 0x01)
1914 GEN_CRLOGIC(or, 0x0E)
1916 GEN_CRLOGIC(orc, 0x0D)
1918 GEN_CRLOGIC(xor, 0x06)
1920 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1922 gen_op_load_crf_T0(crfS(ctx->opcode));
1923 gen_op_store_T0_crf(crfD(ctx->opcode));
1926 /*** System linkage ***/
1927 /* rfi (supervisor only) */
1928 GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1930 #if defined(CONFIG_USER_ONLY)
1933 /* Restore CPU state */
1934 if (!ctx->supervisor) {
1944 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1946 #if defined(CONFIG_USER_ONLY)
1947 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1949 RET_EXCP(ctx, EXCP_SYSCALL, 0);
1955 GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1957 gen_op_load_gpr_T0(rA(ctx->opcode));
1958 gen_op_load_gpr_T1(rB(ctx->opcode));
1959 gen_op_tw(TO(ctx->opcode));
1963 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1965 gen_op_load_gpr_T0(rA(ctx->opcode));
1967 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1968 SIMM(ctx->opcode), TO(ctx->opcode));
1970 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1973 /*** Processor control ***/
1974 static inline int check_spr_access (int spr, int rw, int supervisor)
1976 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1979 if (spr != LR && spr != CTR) {
1981 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1982 SPR_ENCODE(spr), supervisor, rw, rights,
1983 (rights >> ((2 * supervisor) + rw)) & 1);
1985 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1986 SPR_ENCODE(spr), supervisor, rw, rights,
1987 (rights >> ((2 * supervisor) + rw)) & 1);
1993 rights = rights >> (2 * supervisor);
1994 rights = rights >> rw;
2000 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
2002 gen_op_load_xer_cr();
2003 gen_op_store_T0_crf(crfD(ctx->opcode));
2004 gen_op_clear_xer_cr();
2008 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
2011 gen_op_store_T0_gpr(rD(ctx->opcode));
2015 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
2017 #if defined(CONFIG_USER_ONLY)
2020 if (!ctx->supervisor) {
2025 gen_op_store_T0_gpr(rD(ctx->opcode));
2030 #define SPR_NOACCESS ((void *)(-1))
2032 static void spr_noaccess (void *opaque, int sprn)
2034 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
2035 printf("ERROR: try to access SPR %d !\n", sprn);
2037 #define SPR_NOACCESS (&spr_noaccess)
2041 static inline void gen_op_mfspr (DisasContext *ctx)
2043 void (*read_cb)(void *opaque, int sprn);
2044 uint32_t sprn = SPR(ctx->opcode);
2046 #if !defined(CONFIG_USER_ONLY)
2047 if (ctx->supervisor)
2048 read_cb = ctx->spr_cb[sprn].oea_read;
2051 read_cb = ctx->spr_cb[sprn].uea_read;
2052 if (read_cb != NULL) {
2053 if (read_cb != SPR_NOACCESS) {
2054 (*read_cb)(ctx, sprn);
2055 gen_op_store_T0_gpr(rD(ctx->opcode));
2057 /* Privilege exception */
2059 fprintf(logfile, "Trying to read priviledged spr %d %03x\n",
2062 printf("Trying to read priviledged spr %d %03x\n", sprn, sprn);
2068 fprintf(logfile, "Trying to read invalid spr %d %03x\n",
2071 printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
2072 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2076 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
2082 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB)
2088 /* The mask should be 0x00100801, but Mac OS X 10.4 use an alternate form */
2089 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
2091 gen_op_load_gpr_T0(rS(ctx->opcode));
2092 gen_op_store_cr(CRM(ctx->opcode));
2096 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2098 #if defined(CONFIG_USER_ONLY)
2101 if (!ctx->supervisor) {
2105 gen_op_update_nip((ctx)->nip);
2106 gen_op_load_gpr_T0(rS(ctx->opcode));
2108 /* Must stop the translation as machine state (may have) changed */
2114 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2116 void (*write_cb)(void *opaque, int sprn);
2117 uint32_t sprn = SPR(ctx->opcode);
2119 #if !defined(CONFIG_USER_ONLY)
2120 if (ctx->supervisor)
2121 write_cb = ctx->spr_cb[sprn].oea_write;
2124 write_cb = ctx->spr_cb[sprn].uea_write;
2125 if (write_cb != NULL) {
2126 if (write_cb != SPR_NOACCESS) {
2127 gen_op_load_gpr_T0(rS(ctx->opcode));
2128 (*write_cb)(ctx, sprn);
2130 /* Privilege exception */
2132 fprintf(logfile, "Trying to write priviledged spr %d %03x\n",
2135 printf("Trying to write priviledged spr %d %03x\n", sprn, sprn);
2141 fprintf(logfile, "Trying to write invalid spr %d %03x\n",
2144 printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
2145 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2149 /*** Cache management ***/
2150 /* For now, all those will be implemented as nop:
2151 * this is valid, regarding the PowerPC specs...
2152 * We just have to flush tb while invalidating instruction cache lines...
2155 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2157 if (rA(ctx->opcode) == 0) {
2158 gen_op_load_gpr_T0(rB(ctx->opcode));
2160 gen_op_load_gpr_T0(rA(ctx->opcode));
2161 gen_op_load_gpr_T1(rB(ctx->opcode));
2167 /* dcbi (Supervisor only) */
2168 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2170 #if defined(CONFIG_USER_ONLY)
2173 if (!ctx->supervisor) {
2177 if (rA(ctx->opcode) == 0) {
2178 gen_op_load_gpr_T0(rB(ctx->opcode));
2180 gen_op_load_gpr_T0(rA(ctx->opcode));
2181 gen_op_load_gpr_T1(rB(ctx->opcode));
2190 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2192 if (rA(ctx->opcode) == 0) {
2193 gen_op_load_gpr_T0(rB(ctx->opcode));
2195 gen_op_load_gpr_T0(rA(ctx->opcode));
2196 gen_op_load_gpr_T1(rB(ctx->opcode));
2203 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2208 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2213 #if defined(CONFIG_USER_ONLY)
2214 #define op_dcbz() gen_op_dcbz_raw()
2216 #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2217 static GenOpFunc *gen_op_dcbz[] = {
2220 &gen_op_dcbz_kernel,
2221 &gen_op_dcbz_kernel,
2225 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2227 if (rA(ctx->opcode) == 0) {
2228 gen_op_load_gpr_T0(rB(ctx->opcode));
2230 gen_op_load_gpr_T0(rA(ctx->opcode));
2231 gen_op_load_gpr_T1(rB(ctx->opcode));
2235 gen_op_check_reservation();
2239 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2241 if (rA(ctx->opcode) == 0) {
2242 gen_op_load_gpr_T0(rB(ctx->opcode));
2244 gen_op_load_gpr_T0(rA(ctx->opcode));
2245 gen_op_load_gpr_T1(rB(ctx->opcode));
2253 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
2257 /*** Segment register manipulation ***/
2258 /* Supervisor only: */
2260 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2262 #if defined(CONFIG_USER_ONLY)
2265 if (!ctx->supervisor) {
2269 gen_op_load_sr(SR(ctx->opcode));
2270 gen_op_store_T0_gpr(rD(ctx->opcode));
2275 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2277 #if defined(CONFIG_USER_ONLY)
2280 if (!ctx->supervisor) {
2284 gen_op_load_gpr_T1(rB(ctx->opcode));
2286 gen_op_store_T0_gpr(rD(ctx->opcode));
2291 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2293 #if defined(CONFIG_USER_ONLY)
2296 if (!ctx->supervisor) {
2300 gen_op_load_gpr_T0(rS(ctx->opcode));
2301 gen_op_store_sr(SR(ctx->opcode));
2307 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2309 #if defined(CONFIG_USER_ONLY)
2312 if (!ctx->supervisor) {
2316 gen_op_load_gpr_T0(rS(ctx->opcode));
2317 gen_op_load_gpr_T1(rB(ctx->opcode));
2318 gen_op_store_srin();
2323 /*** Lookaside buffer management ***/
2324 /* Optional & supervisor only: */
2326 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
2328 #if defined(CONFIG_USER_ONLY)
2331 if (!ctx->supervisor) {
2333 fprintf(logfile, "%s: ! supervisor\n", __func__);
2343 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2345 #if defined(CONFIG_USER_ONLY)
2348 if (!ctx->supervisor) {
2352 gen_op_load_gpr_T0(rB(ctx->opcode));
2359 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2361 #if defined(CONFIG_USER_ONLY)
2364 if (!ctx->supervisor) {
2368 /* This has no effect: it should ensure that all previous
2369 * tlbie have completed
2375 /*** External control ***/
2377 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2378 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2379 #if defined(CONFIG_USER_ONLY)
2380 static GenOpFunc *gen_op_eciwx[] = {
2382 &gen_op_eciwx_le_raw,
2384 static GenOpFunc *gen_op_ecowx[] = {
2386 &gen_op_ecowx_le_raw,
2389 static GenOpFunc *gen_op_eciwx[] = {
2391 &gen_op_eciwx_le_user,
2392 &gen_op_eciwx_kernel,
2393 &gen_op_eciwx_le_kernel,
2395 static GenOpFunc *gen_op_ecowx[] = {
2397 &gen_op_ecowx_le_user,
2398 &gen_op_ecowx_kernel,
2399 &gen_op_ecowx_le_kernel,
2404 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2406 /* Should check EAR[E] & alignment ! */
2407 if (rA(ctx->opcode) == 0) {
2408 gen_op_load_gpr_T0(rB(ctx->opcode));
2410 gen_op_load_gpr_T0(rA(ctx->opcode));
2411 gen_op_load_gpr_T1(rB(ctx->opcode));
2415 gen_op_store_T0_gpr(rD(ctx->opcode));
2419 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2421 /* Should check EAR[E] & alignment ! */
2422 if (rA(ctx->opcode) == 0) {
2423 gen_op_load_gpr_T0(rB(ctx->opcode));
2425 gen_op_load_gpr_T0(rA(ctx->opcode));
2426 gen_op_load_gpr_T1(rB(ctx->opcode));
2429 gen_op_load_gpr_T2(rS(ctx->opcode));
2433 /* End opcode list */
2434 GEN_OPCODE_MARK(end);
2436 #include "translate_init.c"
2438 /*****************************************************************************/
2439 /* Misc PowerPC helpers */
2440 void cpu_dump_state(CPUState *env, FILE *f,
2441 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2444 #if defined(TARGET_PPC64) || 1
2446 #define REGX "%016" PRIx64
2451 #define REGX "%08" PRIx64
2458 cpu_fprintf(f, "NIP " REGX " LR " REGX " CTR " REGX "\n",
2459 env->nip, env->lr, env->ctr);
2460 cpu_fprintf(f, "MSR " REGX FILL " XER %08x TB %08x %08x DECR %08x\n",
2461 do_load_msr(env), do_load_xer(env), cpu_ppc_load_tbu(env),
2462 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
2463 for (i = 0; i < 32; i++) {
2464 if ((i & (RGPL - 1)) == 0)
2465 cpu_fprintf(f, "GPR%02d", i);
2466 cpu_fprintf(f, " " REGX, env->gpr[i]);
2467 if ((i & (RGPL - 1)) == (RGPL - 1))
2468 cpu_fprintf(f, "\n");
2470 cpu_fprintf(f, "CR ");
2471 for (i = 0; i < 8; i++)
2472 cpu_fprintf(f, "%01x", env->crf[i]);
2473 cpu_fprintf(f, " [");
2474 for (i = 0; i < 8; i++) {
2476 if (env->crf[i] & 0x08)
2478 else if (env->crf[i] & 0x04)
2480 else if (env->crf[i] & 0x02)
2482 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
2484 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
2485 for (i = 0; i < 32; i++) {
2486 if ((i & (RFPL - 1)) == 0)
2487 cpu_fprintf(f, "FPR%02d", i);
2488 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
2489 if ((i & (RFPL - 1)) == (RFPL - 1))
2490 cpu_fprintf(f, "\n");
2492 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
2494 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
2502 /*****************************************************************************/
2503 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2506 DisasContext ctx, *ctxp = &ctx;
2507 opc_handler_t **table, *handler;
2508 target_ulong pc_start;
2509 uint16_t *gen_opc_end;
2513 gen_opc_ptr = gen_opc_buf;
2514 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2515 gen_opparam_ptr = gen_opparam_buf;
2519 ctx.exception = EXCP_NONE;
2520 ctx.spr_cb = env->spr_cb;
2521 #if defined(CONFIG_USER_ONLY)
2522 ctx.mem_idx = msr_le;
2524 ctx.supervisor = 1 - msr_pr;
2525 ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le;
2527 ctx.fpu_enabled = msr_fp;
2528 ctx.singlestep_enabled = env->singlestep_enabled;
2529 #if defined (DO_SINGLE_STEP) && 0
2530 /* Single step trace mode */
2533 /* Set env in case of segfault during code fetch */
2534 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
2535 if (env->nb_breakpoints > 0) {
2536 for(j = 0; j < env->nb_breakpoints; j++) {
2537 if (env->breakpoints[j] == ctx.nip) {
2538 gen_op_update_nip(ctx.nip);
2545 j = gen_opc_ptr - gen_opc_buf;
2549 gen_opc_instr_start[lj++] = 0;
2550 gen_opc_pc[lj] = ctx.nip;
2551 gen_opc_instr_start[lj] = 1;
2554 #if defined PPC_DEBUG_DISAS
2555 if (loglevel & CPU_LOG_TB_IN_ASM) {
2556 fprintf(logfile, "----------------\n");
2557 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
2558 ctx.nip, 1 - msr_pr, msr_ir);
2561 ctx.opcode = ldl_code(ctx.nip);
2563 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
2564 ((ctx.opcode & 0x00FF0000) >> 8) |
2565 ((ctx.opcode & 0x0000FF00) << 8) |
2566 ((ctx.opcode & 0x000000FF) << 24);
2568 #if defined PPC_DEBUG_DISAS
2569 if (loglevel & CPU_LOG_TB_IN_ASM) {
2570 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
2571 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
2572 opc3(ctx.opcode), msr_le ? "little" : "big");
2576 table = env->opcodes;
2577 handler = table[opc1(ctx.opcode)];
2578 if (is_indirect_opcode(handler)) {
2579 table = ind_table(handler);
2580 handler = table[opc2(ctx.opcode)];
2581 if (is_indirect_opcode(handler)) {
2582 table = ind_table(handler);
2583 handler = table[opc3(ctx.opcode)];
2586 /* Is opcode *REALLY* valid ? */
2587 if (handler->handler == &gen_invalid) {
2589 fprintf(logfile, "invalid/unsupported opcode: "
2590 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2591 opc1(ctx.opcode), opc2(ctx.opcode),
2592 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2594 printf("invalid/unsupported opcode: "
2595 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2596 opc1(ctx.opcode), opc2(ctx.opcode),
2597 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2600 if ((ctx.opcode & handler->inval) != 0) {
2602 fprintf(logfile, "invalid bits: %08x for opcode: "
2603 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
2604 ctx.opcode & handler->inval, opc1(ctx.opcode),
2605 opc2(ctx.opcode), opc3(ctx.opcode),
2606 ctx.opcode, ctx.nip - 4);
2608 printf("invalid bits: %08x for opcode: "
2609 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
2610 ctx.opcode & handler->inval, opc1(ctx.opcode),
2611 opc2(ctx.opcode), opc3(ctx.opcode),
2612 ctx.opcode, ctx.nip - 4);
2618 (*(handler->handler))(&ctx);
2619 /* Check trace mode exceptions */
2620 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
2621 /* Check in single step trace mode
2622 * we need to stop except if:
2623 * - rfi, trap or syscall
2624 * - first instruction of an exception handler
2626 (msr_se && (ctx.nip < 0x100 ||
2628 (ctx.nip & 0xFC) != 0x04) &&
2629 ctx.exception != EXCP_SYSCALL &&
2630 ctx.exception != EXCP_SYSCALL_USER &&
2631 ctx.exception != EXCP_TRAP)) {
2632 RET_EXCP(ctxp, EXCP_TRACE, 0);
2635 /* if we reach a page boundary or are single stepping, stop
2638 if (((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2639 (env->singlestep_enabled)) {
2642 #if defined (DO_SINGLE_STEP)
2646 if (ctx.exception == EXCP_NONE) {
2647 gen_goto_tb(&ctx, 0, ctx.nip);
2648 } else if (ctx.exception != EXCP_BRANCH) {
2652 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
2653 * do bad business and then qemu crashes !
2657 /* Generate the return instruction */
2659 *gen_opc_ptr = INDEX_op_end;
2661 j = gen_opc_ptr - gen_opc_buf;
2664 gen_opc_instr_start[lj++] = 0;
2672 tb->size = ctx.nip - pc_start;
2675 if (loglevel & CPU_LOG_TB_CPU) {
2676 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
2677 cpu_dump_state(env, logfile, fprintf, 0);
2679 if (loglevel & CPU_LOG_TB_IN_ASM) {
2680 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2681 target_disas(logfile, pc_start, ctx.nip - pc_start, msr_le);
2682 fprintf(logfile, "\n");
2684 if (loglevel & CPU_LOG_TB_OP) {
2685 fprintf(logfile, "OP:\n");
2686 dump_ops(gen_opc_buf, gen_opparam_buf);
2687 fprintf(logfile, "\n");
2693 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2695 return gen_intermediate_code_internal(env, tb, 0);
2698 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2700 return gen_intermediate_code_internal(env, tb, 1);