2 * PowerPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if !defined (__CPU_PPC_H__)
26 #if defined (TARGET_PPC64)
27 typedef uint64_t ppc_gpr_t;
28 #define TARGET_GPR_BITS 64
29 #define TARGET_LONG_BITS 64
30 #define REGX "%016" PRIx64
31 #define TARGET_PAGE_BITS 12
32 #elif defined(TARGET_PPCEMB)
33 /* BookE have 36 bits physical address space */
34 #define TARGET_PHYS_ADDR_BITS 64
35 /* GPR are 64 bits: used by vector extension */
36 typedef uint64_t ppc_gpr_t;
37 #define TARGET_GPR_BITS 64
38 #define TARGET_LONG_BITS 32
39 #define REGX "%016" PRIx64
40 #if defined(CONFIG_USER_ONLY)
41 /* It looks like a lot of Linux programs assume page size
42 * is 4kB long. This is evil, but we have to deal with it...
44 #define TARGET_PAGE_BITS 12
46 /* Pages can be 1 kB small */
47 #define TARGET_PAGE_BITS 10
50 #if (HOST_LONG_BITS >= 64)
51 /* When using 64 bits temporary registers,
52 * we can use 64 bits GPR with no extra cost
53 * It's even an optimization as it will prevent
54 * the compiler to do unuseful masking in the micro-ops.
56 typedef uint64_t ppc_gpr_t;
57 #define TARGET_GPR_BITS 64
58 #define REGX "%08" PRIx64
60 typedef uint32_t ppc_gpr_t;
61 #define TARGET_GPR_BITS 32
62 #define REGX "%08" PRIx32
64 #define TARGET_LONG_BITS 32
65 #define TARGET_PAGE_BITS 12
70 #define ADDRX TARGET_FMT_lx
71 #define PADDRX TARGET_FMT_plx
75 #include "softfloat.h"
77 #define TARGET_HAS_ICE 1
79 #if defined (TARGET_PPC64)
80 #define ELF_MACHINE EM_PPC64
82 #define ELF_MACHINE EM_PPC
85 /*****************************************************************************/
88 POWERPC_MMU_UNKNOWN = 0,
89 /* Standard 32 bits PowerPC MMU */
91 /* PowerPC 6xx MMU with software TLB */
93 /* PowerPC 74xx MMU with software TLB */
94 POWERPC_MMU_SOFT_74xx,
95 /* PowerPC 4xx MMU with software TLB */
97 /* PowerPC 4xx MMU with software TLB and zones protections */
98 POWERPC_MMU_SOFT_4xx_Z,
99 /* PowerPC 4xx MMU in real mode only */
100 POWERPC_MMU_REAL_4xx,
101 /* BookE MMU model */
103 /* BookE FSL MMU model */
104 POWERPC_MMU_BOOKE_FSL,
105 #if defined(TARGET_PPC64)
106 /* 64 bits PowerPC MMU */
108 #endif /* defined(TARGET_PPC64) */
111 /*****************************************************************************/
112 /* Exception model */
114 POWERPC_EXCP_UNKNOWN = 0,
115 /* Standard PowerPC exception model */
117 /* PowerPC 40x exception model */
119 /* PowerPC 601 exception model */
121 /* PowerPC 602 exception model */
123 /* PowerPC 603 exception model */
125 /* PowerPC 603e exception model */
127 /* PowerPC G2 exception model */
129 /* PowerPC 604 exception model */
131 /* PowerPC 7x0 exception model */
133 /* PowerPC 7x5 exception model */
135 /* PowerPC 74xx exception model */
137 /* BookE exception model */
139 #if defined(TARGET_PPC64)
140 /* PowerPC 970 exception model */
142 #endif /* defined(TARGET_PPC64) */
145 /*****************************************************************************/
146 /* Exception vectors definitions */
148 POWERPC_EXCP_NONE = -1,
149 /* The 64 first entries are used by the PowerPC embedded specification */
150 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
151 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
152 POWERPC_EXCP_DSI = 2, /* Data storage exception */
153 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
154 POWERPC_EXCP_EXTERNAL = 4, /* External input */
155 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
156 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
157 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
158 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
159 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
160 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
161 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
162 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
163 POWERPC_EXCP_DTLB = 13, /* Data TLB error */
164 POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */
165 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
166 /* Vectors 16 to 31 are reserved */
167 #if defined(TARGET_PPCEMB)
168 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
169 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
170 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
171 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
172 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
173 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
174 #endif /* defined(TARGET_PPCEMB) */
175 /* Vectors 38 to 63 are reserved */
176 /* Exceptions defined in the PowerPC server specification */
177 POWERPC_EXCP_RESET = 64, /* System reset exception */
178 #if defined(TARGET_PPC64) /* PowerPC 64 */
179 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
180 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
181 #endif /* defined(TARGET_PPC64) */
182 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
183 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
184 #endif /* defined(TARGET_PPC64H) */
185 POWERPC_EXCP_TRACE = 68, /* Trace exception */
186 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
187 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
188 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
189 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
190 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
191 #endif /* defined(TARGET_PPC64H) */
192 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
193 /* 40x specific exceptions */
194 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
195 /* 601 specific exceptions */
196 POWERPC_EXCP_IO = 75, /* IO error exception */
197 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
198 /* 602 specific exceptions */
199 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
200 /* 602/603 specific exceptions */
201 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */
202 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
203 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
204 /* Exceptions available on most PowerPC */
205 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
206 POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */
207 POWERPC_EXCP_SMI = 83, /* System management interrupt */
208 POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */
209 /* 7xx/74xx specific exceptions */
210 POWERPC_EXCP_THERM = 85, /* Thermal interrupt */
211 /* 74xx specific exceptions */
212 POWERPC_EXCP_VPUA = 86, /* Vector assist exception */
213 /* 970FX specific exceptions */
214 POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */
215 POWERPC_EXCP_MAINT = 88, /* Maintenance exception */
217 POWERPC_EXCP_NB = 96,
218 /* Qemu exceptions: used internally during code translation */
219 POWERPC_EXCP_STOP = 0x200, /* stop translation */
220 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
221 /* Qemu exceptions: special cases we want to stop translation */
222 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
223 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
226 /* Exceptions error codes */
228 /* Exception subtypes for POWERPC_EXCP_ALIGN */
229 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
230 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
231 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
232 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
233 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
234 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
235 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
237 POWERPC_EXCP_FP = 0x10,
238 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
239 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
240 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
241 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
242 POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
243 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
244 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
245 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
246 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
247 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
248 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
249 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
250 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
251 /* Invalid instruction */
252 POWERPC_EXCP_INVAL = 0x20,
253 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
254 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
255 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
256 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
257 /* Privileged instruction */
258 POWERPC_EXCP_PRIV = 0x30,
259 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
260 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
262 POWERPC_EXCP_TRAP = 0x40,
265 /*****************************************************************************/
266 /* Input pins model */
268 PPC_FLAGS_INPUT_UNKNOWN = 0,
269 /* PowerPC 6xx bus */
272 PPC_FLAGS_INPUT_BookE,
273 /* PowerPC 405 bus */
275 /* PowerPC 970 bus */
277 /* PowerPC 401 bus */
281 #define PPC_INPUT(env) (env->bus_model)
283 /*****************************************************************************/
284 typedef struct ppc_def_t ppc_def_t;
285 typedef struct opc_handler_t opc_handler_t;
287 /*****************************************************************************/
288 /* Types used to describe some PowerPC registers */
289 typedef struct CPUPPCState CPUPPCState;
290 typedef struct ppc_tb_t ppc_tb_t;
291 typedef struct ppc_spr_t ppc_spr_t;
292 typedef struct ppc_dcr_t ppc_dcr_t;
293 typedef union ppc_avr_t ppc_avr_t;
294 typedef union ppc_tlb_t ppc_tlb_t;
296 /* SPR access micro-ops generations callbacks */
298 void (*uea_read)(void *opaque, int spr_num);
299 void (*uea_write)(void *opaque, int spr_num);
300 #if !defined(CONFIG_USER_ONLY)
301 void (*oea_read)(void *opaque, int spr_num);
302 void (*oea_write)(void *opaque, int spr_num);
303 #if defined(TARGET_PPC64H)
304 void (*hea_read)(void *opaque, int spr_num);
305 void (*hea_write)(void *opaque, int spr_num);
308 const unsigned char *name;
311 /* Altivec registers (128 bits) */
319 /* Software TLB cache */
320 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
321 struct ppc6xx_tlb_t {
327 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
328 struct ppcemb_tlb_t {
329 target_phys_addr_t RPN;
334 uint32_t attr; /* Storage attributes */
342 /*****************************************************************************/
343 /* Machine state register bits definition */
344 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
345 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
346 #define MSR_HV 60 /* hypervisor state hflags */
347 #define MSR_CM 31 /* Computation mode for BookE hflags */
348 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
349 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
350 #define MSR_VR 25 /* altivec available x hflags */
351 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
352 #define MSR_AP 23 /* Access privilege state on 602 hflags */
353 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
354 #define MSR_KEY 19 /* key bit on 603e */
355 #define MSR_POW 18 /* Power management */
356 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
357 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
358 #define MSR_ILE 16 /* Interrupt little-endian mode */
359 #define MSR_EE 15 /* External interrupt enable */
360 #define MSR_PR 14 /* Problem state hflags */
361 #define MSR_FP 13 /* Floating point available hflags */
362 #define MSR_ME 12 /* Machine check interrupt enable */
363 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
364 #define MSR_SE 10 /* Single-step trace enable x hflags */
365 #define MSR_DWE 10 /* Debug wait enable on 405 x */
366 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
367 #define MSR_BE 9 /* Branch trace enable x hflags */
368 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
369 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
370 #define MSR_AL 7 /* AL bit on POWER */
371 #define MSR_EP 3 /* Exception prefix on 601 */
372 #define MSR_IR 5 /* Instruction relocate */
373 #define MSR_DR 4 /* Data relocate */
374 #define MSR_PE 3 /* Protection enable on 403 */
375 #define MSR_PX 2 /* Protection exclusive on 403 x */
376 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
377 #define MSR_RI 1 /* Recoverable interrupt 1 */
378 #define MSR_LE 0 /* Little-endian mode 1 hflags */
379 #define msr_sf env->msr[MSR_SF]
380 #define msr_isf env->msr[MSR_ISF]
381 #define msr_hv env->msr[MSR_HV]
382 #define msr_cm env->msr[MSR_CM]
383 #define msr_icm env->msr[MSR_ICM]
384 #define msr_ucle env->msr[MSR_UCLE]
385 #define msr_vr env->msr[MSR_VR]
386 #define msr_spe env->msr[MSR_SPE]
387 #define msr_ap env->msr[MSR_AP]
388 #define msr_sa env->msr[MSR_SA]
389 #define msr_key env->msr[MSR_KEY]
390 #define msr_pow env->msr[MSR_POW]
391 #define msr_tgpr env->msr[MSR_TGPR]
392 #define msr_ce env->msr[MSR_CE]
393 #define msr_ile env->msr[MSR_ILE]
394 #define msr_ee env->msr[MSR_EE]
395 #define msr_pr env->msr[MSR_PR]
396 #define msr_fp env->msr[MSR_FP]
397 #define msr_me env->msr[MSR_ME]
398 #define msr_fe0 env->msr[MSR_FE0]
399 #define msr_se env->msr[MSR_SE]
400 #define msr_dwe env->msr[MSR_DWE]
401 #define msr_uble env->msr[MSR_UBLE]
402 #define msr_be env->msr[MSR_BE]
403 #define msr_de env->msr[MSR_DE]
404 #define msr_fe1 env->msr[MSR_FE1]
405 #define msr_al env->msr[MSR_AL]
406 #define msr_ir env->msr[MSR_IR]
407 #define msr_dr env->msr[MSR_DR]
408 #define msr_pe env->msr[MSR_PE]
409 #define msr_ep env->msr[MSR_EP]
410 #define msr_px env->msr[MSR_PX]
411 #define msr_pmm env->msr[MSR_PMM]
412 #define msr_ri env->msr[MSR_RI]
413 #define msr_le env->msr[MSR_LE]
416 POWERPC_FLAG_NONE = 0x00000000,
417 /* Flag for MSR bit 25 signification (VRE/SPE) */
418 POWERPC_FLAG_SPE = 0x00000001,
419 POWERPC_FLAG_VRE = 0x00000002,
420 /* Flag for MSR bit 17 signification (TGPR/CE) */
421 POWERPC_FLAG_TGPR = 0x00000004,
422 POWERPC_FLAG_CE = 0x00000008,
423 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
424 POWERPC_FLAG_SE = 0x00000010,
425 POWERPC_FLAG_DWE = 0x00000020,
426 POWERPC_FLAG_UBLE = 0x00000040,
427 /* Flag for MSR bit 9 signification (BE/DE) */
428 POWERPC_FLAG_BE = 0x00000080,
429 POWERPC_FLAG_DE = 0x00000100,
430 /* Flag for MSR but 2 signification (PX/PMM) */
431 POWERPC_FLAG_PX = 0x00000200,
432 POWERPC_FLAG_PMM = 0x00000400,
435 #if defined(TARGET_PPC64H)
436 #define NB_MMU_MODES 3
438 #define NB_MMU_MODES 2
441 /*****************************************************************************/
442 /* The whole PowerPC CPU context */
444 /* First are the most commonly used resources
445 * during translated code execution
447 #if TARGET_GPR_BITS > HOST_LONG_BITS
448 /* temporary fixed-point registers
449 * used to emulate 64 bits target on 32 bits hosts
451 ppc_gpr_t t0, t1, t2;
453 ppc_avr_t avr0, avr1, avr2;
455 /* general purpose registers */
461 /* condition register */
464 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
466 /* Reservation address */
467 target_ulong reserve;
469 /* Those ones are used in supervisor mode only */
470 /* machine state register */
472 /* temporary general purpose registers */
473 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
475 /* Floating point execution context */
476 /* temporary float registers */
480 float_status fp_status;
481 /* floating point registers */
483 /* floating point status and control register */
488 int halted; /* TRUE if the CPU is in suspend state */
490 int access_type; /* when a memory exception occurs, the access
491 type is stored here */
493 /* MMU context - only relevant for full system emulation */
494 #if !defined(CONFIG_USER_ONLY)
495 #if defined(TARGET_PPC64)
496 /* Address space register */
498 /* PowerPC 64 SLB area */
501 /* segment registers */
506 target_ulong DBAT[2][8];
507 target_ulong IBAT[2][8];
508 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
509 int nb_tlb; /* Total number of TLB */
510 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
511 int nb_ways; /* Number of ways in the TLB set */
512 int last_way; /* Last used way used to allocate TLB in a LRU way */
513 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
514 int nb_pids; /* Number of available PID registers */
515 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
516 /* 403 dedicated access protection registers */
520 /* Other registers */
521 /* Special purpose registers */
522 target_ulong spr[1024];
523 ppc_spr_t spr_cb[1024];
524 /* Altivec registers */
527 #if defined(TARGET_PPCEMB)
530 float_status spe_status;
534 /* Internal devices resources */
535 /* Time base and decrementer */
537 /* Device control registers */
540 int dcache_line_size;
541 int icache_line_size;
543 /* Those resources are used during exception processing */
544 /* CPU model definition */
545 target_ulong msr_mask;
555 int interrupt_request;
556 uint32_t pending_interrupts;
557 #if !defined(CONFIG_USER_ONLY)
558 /* This is the IRQ controller, which is implementation dependant
559 * and only relevant when emulating a complete machine.
561 uint32_t irq_input_state;
563 /* Exception vectors */
564 target_ulong excp_vectors[POWERPC_EXCP_NB];
565 target_ulong excp_prefix;
566 target_ulong ivor_mask;
567 target_ulong ivpr_mask;
568 target_ulong hreset_vector;
571 /* Those resources are used only during code translation */
572 /* Next instruction pointer */
575 /* opcode handlers */
576 opc_handler_t *opcodes[0x40];
578 /* Those resources are used only in Qemu core */
580 int user_mode_only; /* user mode only simulation */
581 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
582 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
584 /* Power management */
587 /* temporary hack to handle OSI calls (only used if non NULL) */
588 int (*osi_call)(struct CPUPPCState *env);
591 /* Context used internally during MMU translations */
592 typedef struct mmu_ctx_t mmu_ctx_t;
594 target_phys_addr_t raddr; /* Real address */
595 int prot; /* Protection bits */
596 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
597 target_ulong ptem; /* Virtual segment ID | API */
598 int key; /* Access key */
601 /*****************************************************************************/
602 CPUPPCState *cpu_ppc_init (void);
603 int cpu_ppc_exec (CPUPPCState *s);
604 void cpu_ppc_close (CPUPPCState *s);
605 /* you can call this signal handler from your SIGBUS and SIGSEGV
606 signal handlers to inform the virtual CPU of exceptions. non zero
607 is returned if the signal was handled by the virtual CPU. */
608 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
611 void do_interrupt (CPUPPCState *env);
612 void ppc_hw_interrupt (CPUPPCState *env);
613 void cpu_loop_exit (void);
615 void dump_stack (CPUPPCState *env);
617 #if !defined(CONFIG_USER_ONLY)
618 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
619 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
620 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
621 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
622 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
623 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
624 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
625 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
626 target_ulong do_load_sdr1 (CPUPPCState *env);
627 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
628 #if defined(TARGET_PPC64)
629 target_ulong ppc_load_asr (CPUPPCState *env);
630 void ppc_store_asr (CPUPPCState *env, target_ulong value);
631 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
632 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
633 #endif /* defined(TARGET_PPC64) */
635 target_ulong do_load_sr (CPUPPCState *env, int srnum);
637 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
638 #endif /* !defined(CONFIG_USER_ONLY) */
639 target_ulong ppc_load_xer (CPUPPCState *env);
640 void ppc_store_xer (CPUPPCState *env, target_ulong value);
641 target_ulong do_load_msr (CPUPPCState *env);
642 int do_store_msr (CPUPPCState *env, target_ulong value);
643 #if defined(TARGET_PPC64)
644 int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
647 void do_compute_hflags (CPUPPCState *env);
648 void cpu_ppc_reset (void *opaque);
649 CPUPPCState *cpu_ppc_init (void);
650 void cpu_ppc_close(CPUPPCState *env);
652 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
653 int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
654 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
655 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
657 /* Time-base and decrementer management */
658 #ifndef NO_CPU_IO_DEFS
659 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
660 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
661 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
662 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
663 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
664 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
665 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
666 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
667 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
668 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
669 #if defined(TARGET_PPC64H)
670 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
671 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
672 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
673 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
675 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
676 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
677 #if !defined(CONFIG_USER_ONLY)
678 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
679 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
680 target_ulong load_40x_pit (CPUPPCState *env);
681 void store_40x_pit (CPUPPCState *env, target_ulong val);
682 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
683 void store_40x_sler (CPUPPCState *env, uint32_t val);
684 void store_booke_tcr (CPUPPCState *env, target_ulong val);
685 void store_booke_tsr (CPUPPCState *env, target_ulong val);
686 void ppc_tlb_invalidate_all (CPUPPCState *env);
687 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
688 #if defined(TARGET_PPC64)
689 void ppc_slb_invalidate_all (CPUPPCState *env);
690 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
692 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
696 /* Device control registers */
697 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
698 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
700 #define CPUState CPUPPCState
701 #define cpu_init cpu_ppc_init
702 #define cpu_exec cpu_ppc_exec
703 #define cpu_gen_code cpu_ppc_gen_code
704 #define cpu_signal_handler cpu_ppc_signal_handler
705 #define cpu_list ppc_cpu_list
707 /* MMU modes definitions */
708 #define MMU_MODE0_SUFFIX _user
709 #define MMU_MODE1_SUFFIX _kernel
710 #if defined(TARGET_PPC64H)
711 #define MMU_MODE2_SUFFIX _hypv
713 #define MMU_USER_IDX 0
714 static inline int cpu_mmu_index (CPUState *env)
721 /*****************************************************************************/
722 /* Registers definitions */
728 #define xer_so env->xer[4]
729 #define xer_ov env->xer[6]
730 #define xer_ca env->xer[2]
731 #define xer_cmp env->xer[1]
732 #define xer_bc env->xer[0]
734 /* SPR definitions */
735 #define SPR_MQ (0x000)
736 #define SPR_XER (0x001)
737 #define SPR_601_VRTCU (0x004)
738 #define SPR_601_VRTCL (0x005)
739 #define SPR_601_UDECR (0x006)
740 #define SPR_LR (0x008)
741 #define SPR_CTR (0x009)
742 #define SPR_DSISR (0x012)
743 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
744 #define SPR_601_RTCU (0x014)
745 #define SPR_601_RTCL (0x015)
746 #define SPR_DECR (0x016)
747 #define SPR_SDR1 (0x019)
748 #define SPR_SRR0 (0x01A)
749 #define SPR_SRR1 (0x01B)
750 #define SPR_AMR (0x01D)
751 #define SPR_BOOKE_PID (0x030)
752 #define SPR_BOOKE_DECAR (0x036)
753 #define SPR_BOOKE_CSRR0 (0x03A)
754 #define SPR_BOOKE_CSRR1 (0x03B)
755 #define SPR_BOOKE_DEAR (0x03D)
756 #define SPR_BOOKE_ESR (0x03E)
757 #define SPR_BOOKE_IVPR (0x03F)
758 #define SPR_8xx_EIE (0x050)
759 #define SPR_8xx_EID (0x051)
760 #define SPR_8xx_NRE (0x052)
761 #define SPR_CTRL (0x088)
762 #define SPR_58x_CMPA (0x090)
763 #define SPR_58x_CMPB (0x091)
764 #define SPR_58x_CMPC (0x092)
765 #define SPR_58x_CMPD (0x093)
766 #define SPR_58x_ICR (0x094)
767 #define SPR_58x_DER (0x094)
768 #define SPR_58x_COUNTA (0x096)
769 #define SPR_58x_COUNTB (0x097)
770 #define SPR_UCTRL (0x098)
771 #define SPR_58x_CMPE (0x098)
772 #define SPR_58x_CMPF (0x099)
773 #define SPR_58x_CMPG (0x09A)
774 #define SPR_58x_CMPH (0x09B)
775 #define SPR_58x_LCTRL1 (0x09C)
776 #define SPR_58x_LCTRL2 (0x09D)
777 #define SPR_58x_ICTRL (0x09E)
778 #define SPR_58x_BAR (0x09F)
779 #define SPR_VRSAVE (0x100)
780 #define SPR_USPRG0 (0x100)
781 #define SPR_USPRG1 (0x101)
782 #define SPR_USPRG2 (0x102)
783 #define SPR_USPRG3 (0x103)
784 #define SPR_USPRG4 (0x104)
785 #define SPR_USPRG5 (0x105)
786 #define SPR_USPRG6 (0x106)
787 #define SPR_USPRG7 (0x107)
788 #define SPR_VTBL (0x10C)
789 #define SPR_VTBU (0x10D)
790 #define SPR_SPRG0 (0x110)
791 #define SPR_SPRG1 (0x111)
792 #define SPR_SPRG2 (0x112)
793 #define SPR_SPRG3 (0x113)
794 #define SPR_SPRG4 (0x114)
795 #define SPR_SCOMC (0x114)
796 #define SPR_SPRG5 (0x115)
797 #define SPR_SCOMD (0x115)
798 #define SPR_SPRG6 (0x116)
799 #define SPR_SPRG7 (0x117)
800 #define SPR_ASR (0x118)
801 #define SPR_EAR (0x11A)
802 #define SPR_TBL (0x11C)
803 #define SPR_TBU (0x11D)
804 #define SPR_TBU40 (0x11E)
805 #define SPR_SVR (0x11E)
806 #define SPR_BOOKE_PIR (0x11E)
807 #define SPR_PVR (0x11F)
808 #define SPR_HSPRG0 (0x130)
809 #define SPR_BOOKE_DBSR (0x130)
810 #define SPR_HSPRG1 (0x131)
811 #define SPR_HDSISR (0x132)
812 #define SPR_HDAR (0x133)
813 #define SPR_BOOKE_DBCR0 (0x134)
814 #define SPR_IBCR (0x135)
815 #define SPR_PURR (0x135)
816 #define SPR_BOOKE_DBCR1 (0x135)
817 #define SPR_DBCR (0x136)
818 #define SPR_HDEC (0x136)
819 #define SPR_BOOKE_DBCR2 (0x136)
820 #define SPR_HIOR (0x137)
821 #define SPR_MBAR (0x137)
822 #define SPR_RMOR (0x138)
823 #define SPR_BOOKE_IAC1 (0x138)
824 #define SPR_HRMOR (0x139)
825 #define SPR_BOOKE_IAC2 (0x139)
826 #define SPR_HSRR0 (0x13A)
827 #define SPR_BOOKE_IAC3 (0x13A)
828 #define SPR_HSRR1 (0x13B)
829 #define SPR_BOOKE_IAC4 (0x13B)
830 #define SPR_LPCR (0x13C)
831 #define SPR_BOOKE_DAC1 (0x13C)
832 #define SPR_LPIDR (0x13D)
833 #define SPR_DABR2 (0x13D)
834 #define SPR_BOOKE_DAC2 (0x13D)
835 #define SPR_BOOKE_DVC1 (0x13E)
836 #define SPR_BOOKE_DVC2 (0x13F)
837 #define SPR_BOOKE_TSR (0x150)
838 #define SPR_BOOKE_TCR (0x154)
839 #define SPR_BOOKE_IVOR0 (0x190)
840 #define SPR_BOOKE_IVOR1 (0x191)
841 #define SPR_BOOKE_IVOR2 (0x192)
842 #define SPR_BOOKE_IVOR3 (0x193)
843 #define SPR_BOOKE_IVOR4 (0x194)
844 #define SPR_BOOKE_IVOR5 (0x195)
845 #define SPR_BOOKE_IVOR6 (0x196)
846 #define SPR_BOOKE_IVOR7 (0x197)
847 #define SPR_BOOKE_IVOR8 (0x198)
848 #define SPR_BOOKE_IVOR9 (0x199)
849 #define SPR_BOOKE_IVOR10 (0x19A)
850 #define SPR_BOOKE_IVOR11 (0x19B)
851 #define SPR_BOOKE_IVOR12 (0x19C)
852 #define SPR_BOOKE_IVOR13 (0x19D)
853 #define SPR_BOOKE_IVOR14 (0x19E)
854 #define SPR_BOOKE_IVOR15 (0x19F)
855 #define SPR_BOOKE_SPEFSCR (0x200)
856 #define SPR_E500_BBEAR (0x201)
857 #define SPR_E500_BBTAR (0x202)
858 #define SPR_ATBL (0x20E)
859 #define SPR_ATBU (0x20F)
860 #define SPR_IBAT0U (0x210)
861 #define SPR_BOOKE_IVOR32 (0x210)
862 #define SPR_IBAT0L (0x211)
863 #define SPR_BOOKE_IVOR33 (0x211)
864 #define SPR_IBAT1U (0x212)
865 #define SPR_BOOKE_IVOR34 (0x212)
866 #define SPR_IBAT1L (0x213)
867 #define SPR_BOOKE_IVOR35 (0x213)
868 #define SPR_IBAT2U (0x214)
869 #define SPR_BOOKE_IVOR36 (0x214)
870 #define SPR_IBAT2L (0x215)
871 #define SPR_E500_L1CFG0 (0x215)
872 #define SPR_BOOKE_IVOR37 (0x215)
873 #define SPR_IBAT3U (0x216)
874 #define SPR_E500_L1CFG1 (0x216)
875 #define SPR_IBAT3L (0x217)
876 #define SPR_DBAT0U (0x218)
877 #define SPR_DBAT0L (0x219)
878 #define SPR_DBAT1U (0x21A)
879 #define SPR_DBAT1L (0x21B)
880 #define SPR_DBAT2U (0x21C)
881 #define SPR_DBAT2L (0x21D)
882 #define SPR_DBAT3U (0x21E)
883 #define SPR_DBAT3L (0x21F)
884 #define SPR_IBAT4U (0x230)
885 #define SPR_IBAT4L (0x231)
886 #define SPR_IBAT5U (0x232)
887 #define SPR_IBAT5L (0x233)
888 #define SPR_IBAT6U (0x234)
889 #define SPR_IBAT6L (0x235)
890 #define SPR_IBAT7U (0x236)
891 #define SPR_IBAT7L (0x237)
892 #define SPR_DBAT4U (0x238)
893 #define SPR_DBAT4L (0x239)
894 #define SPR_DBAT5U (0x23A)
895 #define SPR_BOOKE_MCSRR0 (0x23A)
896 #define SPR_DBAT5L (0x23B)
897 #define SPR_BOOKE_MCSRR1 (0x23B)
898 #define SPR_DBAT6U (0x23C)
899 #define SPR_BOOKE_MCSR (0x23C)
900 #define SPR_DBAT6L (0x23D)
901 #define SPR_E500_MCAR (0x23D)
902 #define SPR_DBAT7U (0x23E)
903 #define SPR_BOOKE_DSRR0 (0x23E)
904 #define SPR_DBAT7L (0x23F)
905 #define SPR_BOOKE_DSRR1 (0x23F)
906 #define SPR_BOOKE_SPRG8 (0x25C)
907 #define SPR_BOOKE_SPRG9 (0x25D)
908 #define SPR_BOOKE_MAS0 (0x270)
909 #define SPR_BOOKE_MAS1 (0x271)
910 #define SPR_BOOKE_MAS2 (0x272)
911 #define SPR_BOOKE_MAS3 (0x273)
912 #define SPR_BOOKE_MAS4 (0x274)
913 #define SPR_BOOKE_MAS6 (0x276)
914 #define SPR_BOOKE_PID1 (0x279)
915 #define SPR_BOOKE_PID2 (0x27A)
916 #define SPR_BOOKE_TLB0CFG (0x2B0)
917 #define SPR_BOOKE_TLB1CFG (0x2B1)
918 #define SPR_BOOKE_TLB2CFG (0x2B2)
919 #define SPR_BOOKE_TLB3CFG (0x2B3)
920 #define SPR_BOOKE_EPR (0x2BE)
921 #define SPR_PERF0 (0x300)
922 #define SPR_PERF1 (0x301)
923 #define SPR_PERF2 (0x302)
924 #define SPR_PERF3 (0x303)
925 #define SPR_PERF4 (0x304)
926 #define SPR_PERF5 (0x305)
927 #define SPR_PERF6 (0x306)
928 #define SPR_PERF7 (0x307)
929 #define SPR_PERF8 (0x308)
930 #define SPR_PERF9 (0x309)
931 #define SPR_PERFA (0x30A)
932 #define SPR_PERFB (0x30B)
933 #define SPR_PERFC (0x30C)
934 #define SPR_PERFD (0x30D)
935 #define SPR_PERFE (0x30E)
936 #define SPR_PERFF (0x30F)
937 #define SPR_UPERF0 (0x310)
938 #define SPR_UPERF1 (0x311)
939 #define SPR_UPERF2 (0x312)
940 #define SPR_UPERF3 (0x313)
941 #define SPR_UPERF4 (0x314)
942 #define SPR_UPERF5 (0x315)
943 #define SPR_UPERF6 (0x316)
944 #define SPR_UPERF7 (0x317)
945 #define SPR_UPERF8 (0x318)
946 #define SPR_UPERF9 (0x319)
947 #define SPR_UPERFA (0x31A)
948 #define SPR_UPERFB (0x31B)
949 #define SPR_UPERFC (0x31C)
950 #define SPR_UPERFD (0x31D)
951 #define SPR_UPERFE (0x31E)
952 #define SPR_UPERFF (0x31F)
953 #define SPR_440_INV0 (0x370)
954 #define SPR_440_INV1 (0x371)
955 #define SPR_440_INV2 (0x372)
956 #define SPR_440_INV3 (0x373)
957 #define SPR_440_ITV0 (0x374)
958 #define SPR_440_ITV1 (0x375)
959 #define SPR_440_ITV2 (0x376)
960 #define SPR_440_ITV3 (0x377)
961 #define SPR_440_CCR1 (0x378)
962 #define SPR_DCRIPR (0x37B)
963 #define SPR_PPR (0x380)
964 #define SPR_440_DNV0 (0x390)
965 #define SPR_440_DNV1 (0x391)
966 #define SPR_440_DNV2 (0x392)
967 #define SPR_440_DNV3 (0x393)
968 #define SPR_440_DTV0 (0x394)
969 #define SPR_440_DTV1 (0x395)
970 #define SPR_440_DTV2 (0x396)
971 #define SPR_440_DTV3 (0x397)
972 #define SPR_440_DVLIM (0x398)
973 #define SPR_440_IVLIM (0x399)
974 #define SPR_440_RSTCFG (0x39B)
975 #define SPR_BOOKE_DCDBTRL (0x39C)
976 #define SPR_BOOKE_DCDBTRH (0x39D)
977 #define SPR_BOOKE_ICDBTRL (0x39E)
978 #define SPR_BOOKE_ICDBTRH (0x39F)
979 #define SPR_UMMCR2 (0x3A0)
980 #define SPR_UPMC5 (0x3A1)
981 #define SPR_UPMC6 (0x3A2)
982 #define SPR_UBAMR (0x3A7)
983 #define SPR_UMMCR0 (0x3A8)
984 #define SPR_UPMC1 (0x3A9)
985 #define SPR_UPMC2 (0x3AA)
986 #define SPR_USIAR (0x3AB)
987 #define SPR_UMMCR1 (0x3AC)
988 #define SPR_UPMC3 (0x3AD)
989 #define SPR_UPMC4 (0x3AE)
990 #define SPR_USDA (0x3AF)
991 #define SPR_40x_ZPR (0x3B0)
992 #define SPR_BOOKE_MAS7 (0x3B0)
993 #define SPR_620_PMR0 (0x3B0)
994 #define SPR_MMCR2 (0x3B0)
995 #define SPR_PMC5 (0x3B1)
996 #define SPR_40x_PID (0x3B1)
997 #define SPR_620_PMR1 (0x3B1)
998 #define SPR_PMC6 (0x3B2)
999 #define SPR_440_MMUCR (0x3B2)
1000 #define SPR_620_PMR2 (0x3B2)
1001 #define SPR_4xx_CCR0 (0x3B3)
1002 #define SPR_BOOKE_EPLC (0x3B3)
1003 #define SPR_620_PMR3 (0x3B3)
1004 #define SPR_405_IAC3 (0x3B4)
1005 #define SPR_BOOKE_EPSC (0x3B4)
1006 #define SPR_620_PMR4 (0x3B4)
1007 #define SPR_405_IAC4 (0x3B5)
1008 #define SPR_620_PMR5 (0x3B5)
1009 #define SPR_405_DVC1 (0x3B6)
1010 #define SPR_620_PMR6 (0x3B6)
1011 #define SPR_405_DVC2 (0x3B7)
1012 #define SPR_620_PMR7 (0x3B7)
1013 #define SPR_BAMR (0x3B7)
1014 #define SPR_MMCR0 (0x3B8)
1015 #define SPR_620_PMR8 (0x3B8)
1016 #define SPR_PMC1 (0x3B9)
1017 #define SPR_40x_SGR (0x3B9)
1018 #define SPR_620_PMR9 (0x3B9)
1019 #define SPR_PMC2 (0x3BA)
1020 #define SPR_40x_DCWR (0x3BA)
1021 #define SPR_620_PMRA (0x3BA)
1022 #define SPR_SIAR (0x3BB)
1023 #define SPR_405_SLER (0x3BB)
1024 #define SPR_620_PMRB (0x3BB)
1025 #define SPR_MMCR1 (0x3BC)
1026 #define SPR_405_SU0R (0x3BC)
1027 #define SPR_620_PMRC (0x3BC)
1028 #define SPR_401_SKR (0x3BC)
1029 #define SPR_PMC3 (0x3BD)
1030 #define SPR_405_DBCR1 (0x3BD)
1031 #define SPR_620_PMRD (0x3BD)
1032 #define SPR_PMC4 (0x3BE)
1033 #define SPR_620_PMRE (0x3BE)
1034 #define SPR_SDA (0x3BF)
1035 #define SPR_620_PMRF (0x3BF)
1036 #define SPR_403_VTBL (0x3CC)
1037 #define SPR_403_VTBU (0x3CD)
1038 #define SPR_DMISS (0x3D0)
1039 #define SPR_DCMP (0x3D1)
1040 #define SPR_HASH1 (0x3D2)
1041 #define SPR_HASH2 (0x3D3)
1042 #define SPR_BOOKE_ICDBDR (0x3D3)
1043 #define SPR_TLBMISS (0x3D4)
1044 #define SPR_IMISS (0x3D4)
1045 #define SPR_40x_ESR (0x3D4)
1046 #define SPR_PTEHI (0x3D5)
1047 #define SPR_ICMP (0x3D5)
1048 #define SPR_40x_DEAR (0x3D5)
1049 #define SPR_PTELO (0x3D6)
1050 #define SPR_RPA (0x3D6)
1051 #define SPR_40x_EVPR (0x3D6)
1052 #define SPR_L3PM (0x3D7)
1053 #define SPR_403_CDBCR (0x3D7)
1054 #define SPR_L3OHCR (0x3D8)
1055 #define SPR_TCR (0x3D8)
1056 #define SPR_40x_TSR (0x3D8)
1057 #define SPR_IBR (0x3DA)
1058 #define SPR_40x_TCR (0x3DA)
1059 #define SPR_ESASRR (0x3DB)
1060 #define SPR_40x_PIT (0x3DB)
1061 #define SPR_403_TBL (0x3DC)
1062 #define SPR_403_TBU (0x3DD)
1063 #define SPR_SEBR (0x3DE)
1064 #define SPR_40x_SRR2 (0x3DE)
1065 #define SPR_SER (0x3DF)
1066 #define SPR_40x_SRR3 (0x3DF)
1067 #define SPR_L3ITCR0 (0x3E8)
1068 #define SPR_L3ITCR1 (0x3E9)
1069 #define SPR_L3ITCR2 (0x3EA)
1070 #define SPR_L3ITCR3 (0x3EB)
1071 #define SPR_HID0 (0x3F0)
1072 #define SPR_40x_DBSR (0x3F0)
1073 #define SPR_HID1 (0x3F1)
1074 #define SPR_IABR (0x3F2)
1075 #define SPR_40x_DBCR0 (0x3F2)
1076 #define SPR_601_HID2 (0x3F2)
1077 #define SPR_E500_L1CSR0 (0x3F2)
1078 #define SPR_ICTRL (0x3F3)
1079 #define SPR_HID2 (0x3F3)
1080 #define SPR_E500_L1CSR1 (0x3F3)
1081 #define SPR_440_DBDR (0x3F3)
1082 #define SPR_LDSTDB (0x3F4)
1083 #define SPR_40x_IAC1 (0x3F4)
1084 #define SPR_MMUCSR0 (0x3F4)
1085 #define SPR_DABR (0x3F5)
1086 #define DABR_MASK (~(target_ulong)0x7)
1087 #define SPR_E500_BUCSR (0x3F5)
1088 #define SPR_40x_IAC2 (0x3F5)
1089 #define SPR_601_HID5 (0x3F5)
1090 #define SPR_40x_DAC1 (0x3F6)
1091 #define SPR_MSSCR0 (0x3F6)
1092 #define SPR_970_HID5 (0x3F6)
1093 #define SPR_MSSSR0 (0x3F7)
1094 #define SPR_DABRX (0x3F7)
1095 #define SPR_40x_DAC2 (0x3F7)
1096 #define SPR_MMUCFG (0x3F7)
1097 #define SPR_LDSTCR (0x3F8)
1098 #define SPR_L2PMCR (0x3F8)
1099 #define SPR_750_HID2 (0x3F8)
1100 #define SPR_620_HID8 (0x3F8)
1101 #define SPR_L2CR (0x3F9)
1102 #define SPR_620_HID9 (0x3F9)
1103 #define SPR_L3CR (0x3FA)
1104 #define SPR_IABR2 (0x3FA)
1105 #define SPR_40x_DCCR (0x3FA)
1106 #define SPR_ICTC (0x3FB)
1107 #define SPR_40x_ICCR (0x3FB)
1108 #define SPR_THRM1 (0x3FC)
1109 #define SPR_403_PBL1 (0x3FC)
1110 #define SPR_SP (0x3FD)
1111 #define SPR_THRM2 (0x3FD)
1112 #define SPR_403_PBU1 (0x3FD)
1113 #define SPR_604_HID13 (0x3FD)
1114 #define SPR_LT (0x3FE)
1115 #define SPR_THRM3 (0x3FE)
1116 #define SPR_FPECR (0x3FE)
1117 #define SPR_403_PBL2 (0x3FE)
1118 #define SPR_PIR (0x3FF)
1119 #define SPR_403_PBU2 (0x3FF)
1120 #define SPR_601_HID15 (0x3FF)
1121 #define SPR_604_HID15 (0x3FF)
1122 #define SPR_E500_SVR (0x3FF)
1124 /*****************************************************************************/
1125 /* Memory access type :
1126 * may be needed for precise access rights control and precise exceptions.
1129 /* 1 bit to define user level / supervisor access */
1131 ACCESS_SUPER = 0x01,
1132 /* Type of instruction that generated the access */
1133 ACCESS_CODE = 0x10, /* Code fetch access */
1134 ACCESS_INT = 0x20, /* Integer load/store access */
1135 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1136 ACCESS_RES = 0x40, /* load/store with reservation */
1137 ACCESS_EXT = 0x50, /* external access */
1138 ACCESS_CACHE = 0x60, /* Cache manipulation */
1141 /* Hardware interruption sources:
1142 * all those exception can be raised simulteaneously
1144 /* Input pins definitions */
1146 /* 6xx bus input pins */
1147 PPC6xx_INPUT_HRESET = 0,
1148 PPC6xx_INPUT_SRESET = 1,
1149 PPC6xx_INPUT_CKSTP_IN = 2,
1150 PPC6xx_INPUT_MCP = 3,
1151 PPC6xx_INPUT_SMI = 4,
1152 PPC6xx_INPUT_INT = 5,
1153 PPC6xx_INPUT_TBEN = 6,
1154 PPC6xx_INPUT_WAKEUP = 7,
1159 /* Embedded PowerPC input pins */
1160 PPCBookE_INPUT_HRESET = 0,
1161 PPCBookE_INPUT_SRESET = 1,
1162 PPCBookE_INPUT_CKSTP_IN = 2,
1163 PPCBookE_INPUT_MCP = 3,
1164 PPCBookE_INPUT_SMI = 4,
1165 PPCBookE_INPUT_INT = 5,
1166 PPCBookE_INPUT_CINT = 6,
1171 /* PowerPC 40x input pins */
1172 PPC40x_INPUT_RESET_CORE = 0,
1173 PPC40x_INPUT_RESET_CHIP = 1,
1174 PPC40x_INPUT_RESET_SYS = 2,
1175 PPC40x_INPUT_CINT = 3,
1176 PPC40x_INPUT_INT = 4,
1177 PPC40x_INPUT_HALT = 5,
1178 PPC40x_INPUT_DEBUG = 6,
1182 #if defined(TARGET_PPC64)
1184 /* PowerPC 970 input pins */
1185 PPC970_INPUT_HRESET = 0,
1186 PPC970_INPUT_SRESET = 1,
1187 PPC970_INPUT_CKSTP = 2,
1188 PPC970_INPUT_TBEN = 3,
1189 PPC970_INPUT_MCP = 4,
1190 PPC970_INPUT_INT = 5,
1191 PPC970_INPUT_THINT = 6,
1195 /* Hardware exceptions definitions */
1197 /* External hardware exception sources */
1198 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1199 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1200 PPC_INTERRUPT_MCK, /* Machine check exception */
1201 PPC_INTERRUPT_EXT, /* External interrupt */
1202 PPC_INTERRUPT_SMI, /* System management interrupt */
1203 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1204 PPC_INTERRUPT_DEBUG, /* External debug exception */
1205 PPC_INTERRUPT_THERM, /* Thermal exception */
1206 /* Internal hardware exception sources */
1207 PPC_INTERRUPT_DECR, /* Decrementer exception */
1208 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1209 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1210 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1211 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1212 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1213 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1214 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1217 /*****************************************************************************/
1219 #endif /* !defined (__CPU_PPC_H__) */