2 * PPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if !defined (__CPU_PPC_H__)
23 #define TARGET_LONG_BITS 32
30 #include "softfloat.h"
32 /* Instruction types */
35 PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
36 PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
37 PPC_FLOW = 0x0004, /* CPU has flow control instructions */
38 PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
39 PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
40 PPC_CACHE = 0x0020, /* CPU has cache control instructions */
41 PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
42 PPC_EXTERN = 0x0080, /* CPU has external control instructions */
43 PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
44 PPC_CACHE_OPT= 0x0200,
45 PPC_FLOAT_OPT= 0x0400,
49 #define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
50 PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
52 #define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
53 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT \
55 /* PPC 740/745/750/755 (aka G3) has external access instructions */
56 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
57 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
59 typedef struct ppc_tb_t ppc_tb_t;
61 /* Supervisor mode registers */
62 /* Machine state register */
78 #define msr_pow env->msr[MSR_POW]
79 #define msr_ile env->msr[MSR_ILE]
80 #define msr_ee env->msr[MSR_EE]
81 #define msr_pr env->msr[MSR_PR]
82 #define msr_fp env->msr[MSR_FP]
83 #define msr_me env->msr[MSR_ME]
84 #define msr_fe0 env->msr[MSR_FE0]
85 #define msr_se env->msr[MSR_SE]
86 #define msr_be env->msr[MSR_BE]
87 #define msr_fe1 env->msr[MSR_FE1]
88 #define msr_ip env->msr[MSR_IP]
89 #define msr_ir env->msr[MSR_IR]
90 #define msr_dr env->msr[MSR_DR]
91 #define msr_ri env->msr[MSR_RI]
92 #define msr_le env->msr[MSR_LE]
94 /* Segment registers */
95 typedef struct CPUPPCState {
96 /* general purpose registers */
98 /* floating point registers */
100 /* segment registers */
105 /* Reservation address */
107 /* machine state register */
109 /* condition register */
111 /* floating point status and control register */
114 /* special purpose registers */
123 /* temporary float registers */
127 float_status fp_status;
129 int interrupt_request;
133 int access_type; /* when a memory exception occurs, the access
134 type is stored here */
135 int user_mode_only; /* user mode only simulation */
136 struct TranslationBlock *current_tb; /* currently executing TB */
137 /* soft mmu support */
138 /* in order to avoid passing too many arguments to the memory
139 write helpers, we store some rarely used information in the CPU
141 unsigned long mem_write_pc; /* host pc at which the memory was
143 unsigned long mem_write_vaddr; /* target virtual addr at which the
144 memory was written */
145 /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
146 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
147 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
149 /* ice debug support */
150 uint32_t breakpoints[MAX_BREAKPOINTS];
152 int singlestep_enabled; /* XXX: should use CPU single step mode instead */
154 /* Time base and decrementer */
157 /* Power management */
164 CPUPPCState *cpu_ppc_init(void);
165 int cpu_ppc_exec(CPUPPCState *s);
166 void cpu_ppc_close(CPUPPCState *s);
167 /* you can call this signal handler from your SIGBUS and SIGSEGV
168 signal handlers to inform the virtual CPU of exceptions. non zero
169 is returned if the signal was handled by the virtual CPU. */
171 int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
174 void do_interrupt (CPUPPCState *env);
175 void cpu_loop_exit(void);
177 void dump_stack (CPUPPCState *env);
179 uint32_t _load_xer (CPUPPCState *env);
180 void _store_xer (CPUPPCState *env, uint32_t value);
181 uint32_t _load_msr (CPUPPCState *env);
182 void _store_msr (CPUPPCState *env, uint32_t value);
184 int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
186 /* Time-base and decrementer management */
187 #ifndef NO_CPU_IO_DEFS
188 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
189 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
190 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
191 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
192 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
193 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
196 #define TARGET_PAGE_BITS 12
199 #define ugpr(n) (env->gpr[n])
200 #define fprd(n) (env->fpr[n])
201 #define fprs(n) ((float)env->fpr[n])
202 #define fpru(n) ((uint32_t)env->fpr[n])
203 #define fpri(n) ((int32_t)env->fpr[n])
205 #define SPR_ENCODE(sprn) \
206 (((sprn) >> 5) | (((sprn) & 0x1F) << 5))
209 #define spr(n) env->spr[n]
214 #define xer_so env->xer[3]
215 #define xer_ov env->xer[2]
216 #define xer_ca env->xer[1]
217 #define xer_bc env->xer[0]
219 #define MQ SPR_ENCODE(0)
220 #define XER SPR_ENCODE(1)
221 #define RTCUR SPR_ENCODE(4)
222 #define RTCLR SPR_ENCODE(5)
223 #define LR SPR_ENCODE(8)
224 #define CTR SPR_ENCODE(9)
226 #define V_TBL SPR_ENCODE(268)
227 #define V_TBU SPR_ENCODE(269)
228 /* supervisor mode SPR */
229 #define DSISR SPR_ENCODE(18)
230 #define DAR SPR_ENCODE(19)
231 #define RTCUW SPR_ENCODE(20)
232 #define RTCLW SPR_ENCODE(21)
233 #define DECR SPR_ENCODE(22)
234 #define SDR1 SPR_ENCODE(25)
235 #define SRR0 SPR_ENCODE(26)
236 #define SRR1 SPR_ENCODE(27)
237 #define SPRG0 SPR_ENCODE(272)
238 #define SPRG1 SPR_ENCODE(273)
239 #define SPRG2 SPR_ENCODE(274)
240 #define SPRG3 SPR_ENCODE(275)
241 #define SPRG4 SPR_ENCODE(276)
242 #define SPRG5 SPR_ENCODE(277)
243 #define SPRG6 SPR_ENCODE(278)
244 #define SPRG7 SPR_ENCODE(279)
245 #define ASR SPR_ENCODE(280)
246 #define EAR SPR_ENCODE(282)
247 #define O_TBL SPR_ENCODE(284)
248 #define O_TBU SPR_ENCODE(285)
249 #define PVR SPR_ENCODE(287)
250 #define IBAT0U SPR_ENCODE(528)
251 #define IBAT0L SPR_ENCODE(529)
252 #define IBAT1U SPR_ENCODE(530)
253 #define IBAT1L SPR_ENCODE(531)
254 #define IBAT2U SPR_ENCODE(532)
255 #define IBAT2L SPR_ENCODE(533)
256 #define IBAT3U SPR_ENCODE(534)
257 #define IBAT3L SPR_ENCODE(535)
258 #define DBAT0U SPR_ENCODE(536)
259 #define DBAT0L SPR_ENCODE(537)
260 #define DBAT1U SPR_ENCODE(538)
261 #define DBAT1L SPR_ENCODE(539)
262 #define DBAT2U SPR_ENCODE(540)
263 #define DBAT2L SPR_ENCODE(541)
264 #define DBAT3U SPR_ENCODE(542)
265 #define DBAT3L SPR_ENCODE(543)
266 #define IBAT4U SPR_ENCODE(560)
267 #define IBAT4L SPR_ENCODE(561)
268 #define IBAT5U SPR_ENCODE(562)
269 #define IBAT5L SPR_ENCODE(563)
270 #define IBAT6U SPR_ENCODE(564)
271 #define IBAT6L SPR_ENCODE(565)
272 #define IBAT7U SPR_ENCODE(566)
273 #define IBAT7L SPR_ENCODE(567)
274 #define DBAT4U SPR_ENCODE(568)
275 #define DBAT4L SPR_ENCODE(569)
276 #define DBAT5U SPR_ENCODE(570)
277 #define DBAT5L SPR_ENCODE(571)
278 #define DBAT6U SPR_ENCODE(572)
279 #define DBAT6L SPR_ENCODE(573)
280 #define DBAT7U SPR_ENCODE(574)
281 #define DBAT7L SPR_ENCODE(575)
282 #define UMMCR0 SPR_ENCODE(936)
283 #define UPMC1 SPR_ENCODE(937)
284 #define UPMC2 SPR_ENCODE(938)
285 #define USIA SPR_ENCODE(939)
286 #define UMMCR1 SPR_ENCODE(940)
287 #define UPMC3 SPR_ENCODE(941)
288 #define UPMC4 SPR_ENCODE(942)
289 #define MMCR0 SPR_ENCODE(952)
290 #define PMC1 SPR_ENCODE(953)
291 #define PMC2 SPR_ENCODE(954)
292 #define SIA SPR_ENCODE(955)
293 #define MMCR1 SPR_ENCODE(956)
294 #define PMC3 SPR_ENCODE(957)
295 #define PMC4 SPR_ENCODE(958)
296 #define SDA SPR_ENCODE(959)
297 #define DMISS SPR_ENCODE(976)
298 #define DCMP SPR_ENCODE(977)
299 #define DHASH1 SPR_ENCODE(978)
300 #define DHASH2 SPR_ENCODE(979)
301 #define IMISS SPR_ENCODE(980)
302 #define ICMP SPR_ENCODE(981)
303 #define RPA SPR_ENCODE(982)
304 #define TCR SPR_ENCODE(984)
305 #define IBR SPR_ENCODE(986)
306 #define ESASRR SPR_ENCODE(987)
307 #define SEBR SPR_ENCODE(990)
308 #define SER SPR_ENCODE(991)
309 #define HID0 SPR_ENCODE(1008)
310 #define HID1 SPR_ENCODE(1009)
311 #define IABR SPR_ENCODE(1010)
312 #define HID2 SPR_ENCODE(1011)
313 #define DABR SPR_ENCODE(1013)
314 #define L2PM SPR_ENCODE(1016)
315 #define L2CR SPR_ENCODE(1017)
316 #define ICTC SPR_ENCODE(1019)
317 #define THRM1 SPR_ENCODE(1020)
318 #define THRM2 SPR_ENCODE(1021)
319 #define THRM3 SPR_ENCODE(1022)
320 #define SP SPR_ENCODE(1021)
321 #define SPR_LP SPR_ENCODE(1022)
322 #define DABR_MASK 0xFFFFFFF8
323 #define FPECR SPR_ENCODE(1022)
324 #define PIR SPR_ENCODE(1023)
326 /* Memory access type :
327 * may be needed for precise access rights control and precise exceptions.
330 /* 1 bit to define user level / supervisor access */
333 /* Type of instruction that generated the access */
334 ACCESS_CODE = 0x10, /* Code fetch access */
335 ACCESS_INT = 0x20, /* Integer load/store access */
336 ACCESS_FLOAT = 0x30, /* floating point load/store access */
337 ACCESS_RES = 0x40, /* load/store with reservation */
338 ACCESS_EXT = 0x50, /* external access */
339 ACCESS_CACHE = 0x60, /* Cache manipulation */
342 /*****************************************************************************/
346 /* PPC hardware exceptions : exception vector / 0x100 */
347 EXCP_RESET = 0x01, /* System reset */
348 EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
349 EXCP_DSI = 0x03, /* Impossible memory access */
350 EXCP_ISI = 0x04, /* Impossible instruction fetch */
351 EXCP_EXTERNAL = 0x05, /* External interruption */
352 EXCP_ALIGN = 0x06, /* Alignment exception */
353 EXCP_PROGRAM = 0x07, /* Program exception */
354 EXCP_NO_FP = 0x08, /* No floating point */
355 EXCP_DECR = 0x09, /* Decrementer exception */
356 EXCP_RESA = 0x0A, /* Implementation specific */
357 EXCP_RESB = 0x0B, /* Implementation specific */
358 EXCP_SYSCALL = 0x0C, /* System call */
359 EXCP_TRACE = 0x0D, /* Trace exception (optional) */
360 EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
361 /* MPC740/745/750 & IBM 750 */
362 EXCP_PERF = 0x0F, /* Performance monitor */
363 EXCP_IABR = 0x13, /* Instruction address breakpoint */
364 EXCP_SMI = 0x14, /* System management interrupt */
365 EXCP_THRM = 0x15, /* Thermal management interrupt */
367 EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
368 EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
369 EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
372 EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
373 EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
374 /* Special cases where we want to stop translation */
375 EXCP_MTMSR = 0x104, /* mtmsr instruction: */
376 /* may change privilege level */
377 EXCP_BRANCH = 0x108, /* branch instruction */
378 EXCP_RFI = 0x10C, /* return from interrupt */
379 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
383 /* Exception subtypes for EXCP_DSI */
384 EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
385 EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
386 EXCP_DSI_PROT = 0x03, /* Memory protection violation */
387 EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
388 EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
389 /* flags for EXCP_DSI */
390 EXCP_DSI_DIRECT = 0x10,
391 EXCP_DSI_STORE = 0x20,
392 EXCP_DSI_ECXW = 0x40,
393 /* Exception subtypes for EXCP_ISI */
394 EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
395 EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
396 EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
397 EXCP_ISI_PROT = 0x04, /* Memory protection violation */
398 EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from *
399 * a direct store segment */
400 /* Exception subtypes for EXCP_ALIGN */
401 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
402 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
403 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
404 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
405 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
406 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
407 /* Exception subtypes for EXCP_PROGRAM */
410 EXCP_FP_OX = 0x01, /* FP overflow */
411 EXCP_FP_UX = 0x02, /* FP underflow */
412 EXCP_FP_ZX = 0x03, /* FP divide by zero */
413 EXCP_FP_XX = 0x04, /* FP inexact */
414 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
415 EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
416 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
417 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
418 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
419 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
420 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
421 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
422 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
423 /* Invalid instruction */
425 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
426 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
427 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
428 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
429 /* Privileged instruction */
431 EXCP_PRIV_OPC = 0x01,
432 EXCP_PRIV_REG = 0x02,
437 /*****************************************************************************/
439 #endif /* !defined (__CPU_PPC_H__) */