2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define MIPS_DEBUG_DISAS
34 //#define MIPS_DEBUG_SIGN_EXTENSIONS
35 //#define MIPS_SINGLE_STEP
37 #ifdef USE_DIRECT_JUMP
40 #define TBPARAM(x) (long)(x)
44 #define DEF(s, n, copy_size) INDEX_op_ ## s,
50 static uint16_t *gen_opc_ptr;
51 static uint32_t *gen_opparam_ptr;
55 /* MIPS major opcodes */
56 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
59 /* indirect opcode tables */
60 OPC_SPECIAL = (0x00 << 26),
61 OPC_REGIMM = (0x01 << 26),
62 OPC_CP0 = (0x10 << 26),
63 OPC_CP1 = (0x11 << 26),
64 OPC_CP2 = (0x12 << 26),
65 OPC_CP3 = (0x13 << 26),
66 OPC_SPECIAL2 = (0x1C << 26),
67 OPC_SPECIAL3 = (0x1F << 26),
68 /* arithmetic with immediate */
69 OPC_ADDI = (0x08 << 26),
70 OPC_ADDIU = (0x09 << 26),
71 OPC_SLTI = (0x0A << 26),
72 OPC_SLTIU = (0x0B << 26),
73 OPC_ANDI = (0x0C << 26),
74 OPC_ORI = (0x0D << 26),
75 OPC_XORI = (0x0E << 26),
76 OPC_LUI = (0x0F << 26),
77 OPC_DADDI = (0x18 << 26),
78 OPC_DADDIU = (0x19 << 26),
79 /* Jump and branches */
81 OPC_JAL = (0x03 << 26),
82 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
83 OPC_BEQL = (0x14 << 26),
84 OPC_BNE = (0x05 << 26),
85 OPC_BNEL = (0x15 << 26),
86 OPC_BLEZ = (0x06 << 26),
87 OPC_BLEZL = (0x16 << 26),
88 OPC_BGTZ = (0x07 << 26),
89 OPC_BGTZL = (0x17 << 26),
90 OPC_JALX = (0x1D << 26), /* MIPS 16 only */
92 OPC_LDL = (0x1A << 26),
93 OPC_LDR = (0x1B << 26),
94 OPC_LB = (0x20 << 26),
95 OPC_LH = (0x21 << 26),
96 OPC_LWL = (0x22 << 26),
97 OPC_LW = (0x23 << 26),
98 OPC_LBU = (0x24 << 26),
99 OPC_LHU = (0x25 << 26),
100 OPC_LWR = (0x26 << 26),
101 OPC_LWU = (0x27 << 26),
102 OPC_SB = (0x28 << 26),
103 OPC_SH = (0x29 << 26),
104 OPC_SWL = (0x2A << 26),
105 OPC_SW = (0x2B << 26),
106 OPC_SDL = (0x2C << 26),
107 OPC_SDR = (0x2D << 26),
108 OPC_SWR = (0x2E << 26),
109 OPC_LL = (0x30 << 26),
110 OPC_LLD = (0x34 << 26),
111 OPC_LD = (0x37 << 26),
112 OPC_SC = (0x38 << 26),
113 OPC_SCD = (0x3C << 26),
114 OPC_SD = (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1 = (0x31 << 26),
117 OPC_LWC2 = (0x32 << 26),
118 OPC_LDC1 = (0x35 << 26),
119 OPC_LDC2 = (0x36 << 26),
120 OPC_SWC1 = (0x39 << 26),
121 OPC_SWC2 = (0x3A << 26),
122 OPC_SDC1 = (0x3D << 26),
123 OPC_SDC2 = (0x3E << 26),
124 /* MDMX ASE specific */
125 OPC_MDMX = (0x1E << 26),
126 /* Cache and prefetch */
127 OPC_CACHE = (0x2F << 26),
128 OPC_PREF = (0x33 << 26),
129 /* Reserved major opcode */
130 OPC_MAJOR3B_RESERVED = (0x3B << 26),
133 /* MIPS special opcodes */
134 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
138 OPC_SLL = 0x00 | OPC_SPECIAL,
139 /* NOP is SLL r0, r0, 0 */
140 /* SSNOP is SLL r0, r0, 1 */
141 /* EHB is SLL r0, r0, 3 */
142 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
143 OPC_SRA = 0x03 | OPC_SPECIAL,
144 OPC_SLLV = 0x04 | OPC_SPECIAL,
145 OPC_SRLV = 0x06 | OPC_SPECIAL,
146 OPC_SRAV = 0x07 | OPC_SPECIAL,
147 OPC_DSLLV = 0x14 | OPC_SPECIAL,
148 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
149 OPC_DSRAV = 0x17 | OPC_SPECIAL,
150 OPC_DSLL = 0x38 | OPC_SPECIAL,
151 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
152 OPC_DSRA = 0x3B | OPC_SPECIAL,
153 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
154 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
155 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
156 /* Multiplication / division */
157 OPC_MULT = 0x18 | OPC_SPECIAL,
158 OPC_MULTU = 0x19 | OPC_SPECIAL,
159 OPC_DIV = 0x1A | OPC_SPECIAL,
160 OPC_DIVU = 0x1B | OPC_SPECIAL,
161 OPC_DMULT = 0x1C | OPC_SPECIAL,
162 OPC_DMULTU = 0x1D | OPC_SPECIAL,
163 OPC_DDIV = 0x1E | OPC_SPECIAL,
164 OPC_DDIVU = 0x1F | OPC_SPECIAL,
165 /* 2 registers arithmetic / logic */
166 OPC_ADD = 0x20 | OPC_SPECIAL,
167 OPC_ADDU = 0x21 | OPC_SPECIAL,
168 OPC_SUB = 0x22 | OPC_SPECIAL,
169 OPC_SUBU = 0x23 | OPC_SPECIAL,
170 OPC_AND = 0x24 | OPC_SPECIAL,
171 OPC_OR = 0x25 | OPC_SPECIAL,
172 OPC_XOR = 0x26 | OPC_SPECIAL,
173 OPC_NOR = 0x27 | OPC_SPECIAL,
174 OPC_SLT = 0x2A | OPC_SPECIAL,
175 OPC_SLTU = 0x2B | OPC_SPECIAL,
176 OPC_DADD = 0x2C | OPC_SPECIAL,
177 OPC_DADDU = 0x2D | OPC_SPECIAL,
178 OPC_DSUB = 0x2E | OPC_SPECIAL,
179 OPC_DSUBU = 0x2F | OPC_SPECIAL,
181 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
182 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
184 OPC_TGE = 0x30 | OPC_SPECIAL,
185 OPC_TGEU = 0x31 | OPC_SPECIAL,
186 OPC_TLT = 0x32 | OPC_SPECIAL,
187 OPC_TLTU = 0x33 | OPC_SPECIAL,
188 OPC_TEQ = 0x34 | OPC_SPECIAL,
189 OPC_TNE = 0x36 | OPC_SPECIAL,
190 /* HI / LO registers load & stores */
191 OPC_MFHI = 0x10 | OPC_SPECIAL,
192 OPC_MTHI = 0x11 | OPC_SPECIAL,
193 OPC_MFLO = 0x12 | OPC_SPECIAL,
194 OPC_MTLO = 0x13 | OPC_SPECIAL,
195 /* Conditional moves */
196 OPC_MOVZ = 0x0A | OPC_SPECIAL,
197 OPC_MOVN = 0x0B | OPC_SPECIAL,
199 OPC_MOVCI = 0x01 | OPC_SPECIAL,
202 OPC_PMON = 0x05 | OPC_SPECIAL, /* inofficial */
203 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
204 OPC_BREAK = 0x0D | OPC_SPECIAL,
205 OPC_SPIM = 0x0E | OPC_SPECIAL, /* inofficial */
206 OPC_SYNC = 0x0F | OPC_SPECIAL,
208 OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
209 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
210 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
211 OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
212 OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
213 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
214 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
217 /* REGIMM (rt field) opcodes */
218 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
221 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
222 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
223 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
224 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
225 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
226 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
227 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
228 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
229 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
230 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
231 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
232 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
233 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
234 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
235 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
238 /* Special2 opcodes */
239 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
242 /* Multiply & xxx operations */
243 OPC_MADD = 0x00 | OPC_SPECIAL2,
244 OPC_MADDU = 0x01 | OPC_SPECIAL2,
245 OPC_MUL = 0x02 | OPC_SPECIAL2,
246 OPC_MSUB = 0x04 | OPC_SPECIAL2,
247 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
249 OPC_CLZ = 0x20 | OPC_SPECIAL2,
250 OPC_CLO = 0x21 | OPC_SPECIAL2,
251 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
252 OPC_DCLO = 0x25 | OPC_SPECIAL2,
254 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
257 /* Special3 opcodes */
258 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
261 OPC_EXT = 0x00 | OPC_SPECIAL3,
262 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
263 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
264 OPC_DEXT = 0x03 | OPC_SPECIAL3,
265 OPC_INS = 0x04 | OPC_SPECIAL3,
266 OPC_DINSM = 0x05 | OPC_SPECIAL3,
267 OPC_DINSU = 0x06 | OPC_SPECIAL3,
268 OPC_DINS = 0x07 | OPC_SPECIAL3,
269 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
270 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
271 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
275 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
278 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
279 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
280 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
284 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
287 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
288 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
291 /* Coprocessor 0 (rs field) */
292 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
295 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
296 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
297 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
298 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
299 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
300 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
301 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
302 OPC_C0 = (0x10 << 21) | OPC_CP0,
303 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
304 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
308 #define MASK_MFMC0(op) MASK_CP0(op) | (op & ((0x0C << 11) | (1 << 5)))
311 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
312 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
315 /* Coprocessor 0 (with rs == C0) */
316 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
319 OPC_TLBR = 0x01 | OPC_C0,
320 OPC_TLBWI = 0x02 | OPC_C0,
321 OPC_TLBWR = 0x06 | OPC_C0,
322 OPC_TLBP = 0x08 | OPC_C0,
323 OPC_RFE = 0x10 | OPC_C0,
324 OPC_ERET = 0x18 | OPC_C0,
325 OPC_DERET = 0x1F | OPC_C0,
326 OPC_WAIT = 0x20 | OPC_C0,
329 /* Coprocessor 1 (rs field) */
330 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
333 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
334 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
335 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
336 OPC_MFHCI = (0x03 << 21) | OPC_CP1,
337 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
338 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
339 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
340 OPC_MTHCI = (0x07 << 21) | OPC_CP1,
341 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
342 OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
343 OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
344 OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
345 OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
346 OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
347 OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
351 OPC_BC1F = (0x00 << 16) | OPC_BC1,
352 OPC_BC1T = (0x01 << 16) | OPC_BC1,
353 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
354 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
357 #define MASK_CP1_BCOND(op) MASK_CP1(op) | (op & (0x3 << 16))
358 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
360 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
361 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
363 const unsigned char *regnames[] =
364 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
365 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
366 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
367 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
369 /* Warning: no function for r0 register (hard wired to zero) */
370 #define GEN32(func, NAME) \
371 static GenOpFunc *NAME ## _table [32] = { \
372 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
373 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
374 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
375 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
376 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
377 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
378 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
379 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
381 static inline void func(int n) \
383 NAME ## _table[n](); \
386 /* General purpose registers moves */
387 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
388 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
389 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
391 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
392 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
396 static const char *fregnames[] =
397 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
398 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
399 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
400 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
402 # define SFGEN32(func, NAME) \
403 static GenOpFunc *NAME ## _table [32] = { \
404 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
405 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
406 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
407 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
408 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
409 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
410 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
411 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
413 static inline void func(int n) \
415 NAME ## _table[n](); \
418 # define DFGEN32(func, NAME) \
419 static GenOpFunc *NAME ## _table [32] = { \
420 NAME ## 0, 0, NAME ## 2, 0, \
421 NAME ## 4, 0, NAME ## 6, 0, \
422 NAME ## 8, 0, NAME ## 10, 0, \
423 NAME ## 12, 0, NAME ## 14, 0, \
424 NAME ## 16, 0, NAME ## 18, 0, \
425 NAME ## 20, 0, NAME ## 22, 0, \
426 NAME ## 24, 0, NAME ## 26, 0, \
427 NAME ## 28, 0, NAME ## 30, 0, \
429 static inline void func(int n) \
431 NAME ## _table[n](); \
434 SFGEN32(gen_op_load_fpr_WT0, gen_op_load_fpr_WT0_fpr);
435 SFGEN32(gen_op_store_fpr_WT0, gen_op_store_fpr_WT0_fpr);
437 SFGEN32(gen_op_load_fpr_WT1, gen_op_load_fpr_WT1_fpr);
438 SFGEN32(gen_op_store_fpr_WT1, gen_op_store_fpr_WT1_fpr);
440 SFGEN32(gen_op_load_fpr_WT2, gen_op_load_fpr_WT2_fpr);
441 SFGEN32(gen_op_store_fpr_WT2, gen_op_store_fpr_WT2_fpr);
443 DFGEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fpr);
444 DFGEN32(gen_op_store_fpr_DT0, gen_op_store_fpr_DT0_fpr);
446 DFGEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fpr);
447 DFGEN32(gen_op_store_fpr_DT1, gen_op_store_fpr_DT1_fpr);
449 DFGEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fpr);
450 DFGEN32(gen_op_store_fpr_DT2, gen_op_store_fpr_DT2_fpr);
452 #define FOP_CONDS(fmt) \
453 static GenOpFunc * cond_ ## fmt ## _table[16] = { \
454 gen_op_cmp_ ## fmt ## _f, \
455 gen_op_cmp_ ## fmt ## _un, \
456 gen_op_cmp_ ## fmt ## _eq, \
457 gen_op_cmp_ ## fmt ## _ueq, \
458 gen_op_cmp_ ## fmt ## _olt, \
459 gen_op_cmp_ ## fmt ## _ult, \
460 gen_op_cmp_ ## fmt ## _ole, \
461 gen_op_cmp_ ## fmt ## _ule, \
462 gen_op_cmp_ ## fmt ## _sf, \
463 gen_op_cmp_ ## fmt ## _ngle, \
464 gen_op_cmp_ ## fmt ## _seq, \
465 gen_op_cmp_ ## fmt ## _ngl, \
466 gen_op_cmp_ ## fmt ## _lt, \
467 gen_op_cmp_ ## fmt ## _nge, \
468 gen_op_cmp_ ## fmt ## _le, \
469 gen_op_cmp_ ## fmt ## _ngt, \
471 static inline void gen_cmp_ ## fmt(int n) \
473 cond_ ## fmt ## _table[n](); \
479 #endif /* MIPS_USES_FPU */
481 typedef struct DisasContext {
482 struct TranslationBlock *tb;
483 target_ulong pc, saved_pc;
485 /* Routine used to access memory */
487 uint32_t hflags, saved_hflags;
490 target_ulong btarget;
494 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
495 * exception condition
497 BS_STOP = 1, /* We want to stop translation for any reason */
498 BS_BRANCH = 2, /* We reached a branch condition */
499 BS_EXCP = 3, /* We reached an exception condition */
502 #if defined MIPS_DEBUG_DISAS
503 #define MIPS_DEBUG(fmt, args...) \
505 if (loglevel & CPU_LOG_TB_IN_ASM) { \
506 fprintf(logfile, TLSZ ": %08x " fmt "\n", \
507 ctx->pc, ctx->opcode , ##args); \
511 #define MIPS_DEBUG(fmt, args...) do { } while(0)
514 #define MIPS_INVAL(op) \
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
520 #define GEN_LOAD_REG_TN(Tn, Rn) \
523 glue(gen_op_reset_, Tn)(); \
525 glue(gen_op_load_gpr_, Tn)(Rn); \
529 #define GEN_LOAD_IMM_TN(Tn, Imm) \
532 glue(gen_op_reset_, Tn)(); \
534 glue(gen_op_set_, Tn)(Imm); \
538 #define GEN_STORE_TN_REG(Rn, Tn) \
541 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
545 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
547 glue(gen_op_load_fpr_, FTn)(Fn); \
550 #define GEN_STORE_FTN_FREG(Fn, FTn) \
552 glue(gen_op_store_fpr_, FTn)(Fn); \
555 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
557 #if defined MIPS_DEBUG_DISAS
558 if (loglevel & CPU_LOG_TB_IN_ASM) {
559 fprintf(logfile, "hflags %08x saved %08x\n",
560 ctx->hflags, ctx->saved_hflags);
563 if (do_save_pc && ctx->pc != ctx->saved_pc) {
564 gen_op_save_pc(ctx->pc);
565 ctx->saved_pc = ctx->pc;
567 if (ctx->hflags != ctx->saved_hflags) {
568 gen_op_save_state(ctx->hflags);
569 ctx->saved_hflags = ctx->hflags;
570 if (ctx->hflags & MIPS_HFLAG_BR) {
571 gen_op_save_breg_target();
572 } else if (ctx->hflags & MIPS_HFLAG_B) {
573 gen_op_save_btarget(ctx->btarget);
574 } else if (ctx->hflags & MIPS_HFLAG_BMASK) {
576 gen_op_save_btarget(ctx->btarget);
581 static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
583 #if defined MIPS_DEBUG_DISAS
584 if (loglevel & CPU_LOG_TB_IN_ASM)
585 fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
587 save_cpu_state(ctx, 1);
589 gen_op_raise_exception(excp);
591 gen_op_raise_exception_err(excp, err);
592 ctx->bstate = BS_EXCP;
595 static inline void generate_exception (DisasContext *ctx, int excp)
597 generate_exception_err (ctx, excp, 0);
600 #if defined(CONFIG_USER_ONLY)
601 #define op_ldst(name) gen_op_##name##_raw()
602 #define OP_LD_TABLE(width)
603 #define OP_ST_TABLE(width)
605 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
606 #define OP_LD_TABLE(width) \
607 static GenOpFunc *gen_op_l##width[] = { \
608 &gen_op_l##width##_user, \
609 &gen_op_l##width##_kernel, \
611 #define OP_ST_TABLE(width) \
612 static GenOpFunc *gen_op_s##width[] = { \
613 &gen_op_s##width##_user, \
614 &gen_op_s##width##_kernel, \
618 #ifdef MIPS_HAS_MIPS64
651 static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
652 int base, int16_t offset)
654 const char *opn = "unk";
657 GEN_LOAD_IMM_TN(T0, offset);
658 } else if (offset == 0) {
659 gen_op_load_gpr_T0(base);
661 gen_op_load_gpr_T0(base);
662 gen_op_set_T1(offset);
665 /* Don't do NOP if destination is zero: we must perform the actual
669 #ifdef MIPS_HAS_MIPS64
672 GEN_STORE_TN_REG(rt, T0);
677 GEN_STORE_TN_REG(rt, T0);
681 GEN_LOAD_REG_TN(T1, rt);
686 GEN_LOAD_REG_TN(T1, rt);
692 GEN_STORE_TN_REG(rt, T0);
696 GEN_LOAD_REG_TN(T1, rt);
702 GEN_STORE_TN_REG(rt, T0);
706 GEN_LOAD_REG_TN(T1, rt);
713 GEN_STORE_TN_REG(rt, T0);
718 GEN_STORE_TN_REG(rt, T0);
722 GEN_LOAD_REG_TN(T1, rt);
728 GEN_STORE_TN_REG(rt, T0);
732 GEN_LOAD_REG_TN(T1, rt);
738 GEN_STORE_TN_REG(rt, T0);
743 GEN_STORE_TN_REG(rt, T0);
747 GEN_LOAD_REG_TN(T1, rt);
753 GEN_STORE_TN_REG(rt, T0);
757 GEN_LOAD_REG_TN(T1, rt);
759 GEN_STORE_TN_REG(rt, T0);
763 GEN_LOAD_REG_TN(T1, rt);
768 GEN_LOAD_REG_TN(T1, rt);
770 GEN_STORE_TN_REG(rt, T0);
774 GEN_LOAD_REG_TN(T1, rt);
780 GEN_STORE_TN_REG(rt, T0);
784 GEN_LOAD_REG_TN(T1, rt);
786 GEN_STORE_TN_REG(rt, T0);
790 MIPS_INVAL("load/store");
791 generate_exception(ctx, EXCP_RI);
794 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
800 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
801 int base, int16_t offset)
803 const char *opn = "unk";
806 GEN_LOAD_IMM_TN(T0, offset);
807 } else if (offset == 0) {
808 gen_op_load_gpr_T0(base);
810 gen_op_load_gpr_T0(base);
811 gen_op_set_T1(offset);
814 /* Don't do NOP if destination is zero: we must perform the actual
820 GEN_STORE_FTN_FREG(ft, WT0);
824 GEN_LOAD_FREG_FTN(WT0, ft);
830 GEN_STORE_FTN_FREG(ft, DT0);
834 GEN_LOAD_FREG_FTN(DT0, ft);
839 MIPS_INVAL("float load/store");
840 generate_exception_err(ctx, EXCP_CpU, 1);
843 MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
846 #endif /* MIPS_USES_FPU */
848 /* Arithmetic with immediate operand */
849 static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt,
853 const char *opn = "unk";
855 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
856 /* if no destination, treat it as a NOP
857 * For addi, we must generate the overflow exception when needed.
862 if (opc == OPC_ADDI || opc == OPC_ADDIU ||
863 opc == OPC_DADDI || opc == OPC_DADDIU ||
864 opc == OPC_SLTI || opc == OPC_SLTIU)
865 uimm = (int32_t)imm; /* Sign extend to 32 bits */
867 uimm = (uint16_t)imm;
868 if (opc != OPC_LUI) {
869 GEN_LOAD_REG_TN(T0, rs);
870 GEN_LOAD_IMM_TN(T1, uimm);
873 GEN_LOAD_IMM_TN(T0, uimm);
877 save_cpu_state(ctx, 1);
885 #ifdef MIPS_HAS_MIPS64
887 save_cpu_state(ctx, 1);
928 if ((ctx->opcode >> 21) & 1) {
936 #ifdef MIPS_HAS_MIPS64
946 if ((ctx->opcode >> 21) & 1) {
963 if ((ctx->opcode >> 21) & 1) {
973 MIPS_INVAL("imm arith");
974 generate_exception(ctx, EXCP_RI);
977 GEN_STORE_TN_REG(rt, T0);
978 MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
982 static void gen_arith (DisasContext *ctx, uint32_t opc,
983 int rd, int rs, int rt)
985 const char *opn = "unk";
987 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
988 && opc != OPC_DADD && opc != OPC_DSUB) {
989 /* if no destination, treat it as a NOP
990 * For add & sub, we must generate the overflow exception when needed.
995 GEN_LOAD_REG_TN(T0, rs);
996 GEN_LOAD_REG_TN(T1, rt);
999 save_cpu_state(ctx, 1);
1008 save_cpu_state(ctx, 1);
1016 #ifdef MIPS_HAS_MIPS64
1018 save_cpu_state(ctx, 1);
1027 save_cpu_state(ctx, 1);
1081 if ((ctx->opcode >> 6) & 1) {
1089 #ifdef MIPS_HAS_MIPS64
1099 if ((ctx->opcode >> 6) & 1) {
1109 MIPS_INVAL("arith");
1110 generate_exception(ctx, EXCP_RI);
1113 GEN_STORE_TN_REG(rd, T0);
1115 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1118 /* Arithmetic on HI/LO registers */
1119 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1121 const char *opn = "unk";
1123 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1124 /* Treat as a NOP */
1131 GEN_STORE_TN_REG(reg, T0);
1136 GEN_STORE_TN_REG(reg, T0);
1140 GEN_LOAD_REG_TN(T0, reg);
1145 GEN_LOAD_REG_TN(T0, reg);
1151 generate_exception(ctx, EXCP_RI);
1154 MIPS_DEBUG("%s %s", opn, regnames[reg]);
1157 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1160 const char *opn = "unk";
1162 GEN_LOAD_REG_TN(T0, rs);
1163 GEN_LOAD_REG_TN(T1, rt);
1181 #ifdef MIPS_HAS_MIPS64
1216 MIPS_INVAL("mul/div");
1217 generate_exception(ctx, EXCP_RI);
1220 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
1223 static void gen_cl (DisasContext *ctx, uint32_t opc,
1226 const char *opn = "unk";
1228 /* Treat as a NOP */
1232 GEN_LOAD_REG_TN(T0, rs);
1242 #ifdef MIPS_HAS_MIPS64
1254 generate_exception(ctx, EXCP_RI);
1257 gen_op_store_T0_gpr(rd);
1258 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
1262 static void gen_trap (DisasContext *ctx, uint32_t opc,
1263 int rs, int rt, int16_t imm)
1268 /* Load needed operands */
1276 /* Compare two registers */
1278 GEN_LOAD_REG_TN(T0, rs);
1279 GEN_LOAD_REG_TN(T1, rt);
1289 /* Compare register to immediate */
1290 if (rs != 0 || imm != 0) {
1291 GEN_LOAD_REG_TN(T0, rs);
1292 GEN_LOAD_IMM_TN(T1, (int32_t)imm);
1299 case OPC_TEQ: /* rs == rs */
1300 case OPC_TEQI: /* r0 == 0 */
1301 case OPC_TGE: /* rs >= rs */
1302 case OPC_TGEI: /* r0 >= 0 */
1303 case OPC_TGEU: /* rs >= rs unsigned */
1304 case OPC_TGEIU: /* r0 >= 0 unsigned */
1308 case OPC_TLT: /* rs < rs */
1309 case OPC_TLTI: /* r0 < 0 */
1310 case OPC_TLTU: /* rs < rs unsigned */
1311 case OPC_TLTIU: /* r0 < 0 unsigned */
1312 case OPC_TNE: /* rs != rs */
1313 case OPC_TNEI: /* r0 != 0 */
1314 /* Never trap: treat as NOP */
1318 generate_exception(ctx, EXCP_RI);
1349 generate_exception(ctx, EXCP_RI);
1353 save_cpu_state(ctx, 1);
1355 ctx->bstate = BS_STOP;
1358 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1360 TranslationBlock *tb;
1362 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1364 gen_op_goto_tb0(TBPARAM(tb));
1366 gen_op_goto_tb1(TBPARAM(tb));
1367 gen_op_save_pc(dest);
1368 gen_op_set_T0((long)tb + n);
1371 gen_op_save_pc(dest);
1377 /* Branches (before delay slot) */
1378 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
1379 int rs, int rt, int32_t offset)
1381 target_ulong btarget;
1387 /* Load needed operands */
1393 /* Compare two registers */
1395 GEN_LOAD_REG_TN(T0, rs);
1396 GEN_LOAD_REG_TN(T1, rt);
1399 btarget = ctx->pc + 4 + offset;
1413 /* Compare to zero */
1415 gen_op_load_gpr_T0(rs);
1418 btarget = ctx->pc + 4 + offset;
1422 /* Jump to immediate */
1423 btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | offset;
1427 /* Jump to register */
1428 if (offset != 0 && offset != 16) {
1429 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1430 others are reserved. */
1431 generate_exception(ctx, EXCP_RI);
1434 GEN_LOAD_REG_TN(T2, rs);
1437 MIPS_INVAL("branch/jump");
1438 generate_exception(ctx, EXCP_RI);
1442 /* No condition to be computed */
1444 case OPC_BEQ: /* rx == rx */
1445 case OPC_BEQL: /* rx == rx likely */
1446 case OPC_BGEZ: /* 0 >= 0 */
1447 case OPC_BGEZL: /* 0 >= 0 likely */
1448 case OPC_BLEZ: /* 0 <= 0 */
1449 case OPC_BLEZL: /* 0 <= 0 likely */
1451 ctx->hflags |= MIPS_HFLAG_B;
1452 MIPS_DEBUG("balways");
1454 case OPC_BGEZAL: /* 0 >= 0 */
1455 case OPC_BGEZALL: /* 0 >= 0 likely */
1456 /* Always take and link */
1458 ctx->hflags |= MIPS_HFLAG_B;
1459 MIPS_DEBUG("balways and link");
1461 case OPC_BNE: /* rx != rx */
1462 case OPC_BGTZ: /* 0 > 0 */
1463 case OPC_BLTZ: /* 0 < 0 */
1464 /* Treated as NOP */
1465 MIPS_DEBUG("bnever (NOP)");
1467 case OPC_BLTZAL: /* 0 < 0 */
1468 gen_op_set_T0(ctx->pc + 8);
1469 gen_op_store_T0_gpr(31);
1471 case OPC_BLTZALL: /* 0 < 0 likely */
1472 gen_op_set_T0(ctx->pc + 8);
1473 gen_op_store_T0_gpr(31);
1474 gen_goto_tb(ctx, 0, ctx->pc + 4);
1476 case OPC_BNEL: /* rx != rx likely */
1477 case OPC_BGTZL: /* 0 > 0 likely */
1478 case OPC_BLTZL: /* 0 < 0 likely */
1479 /* Skip the instruction in the delay slot */
1480 MIPS_DEBUG("bnever and skip");
1481 gen_goto_tb(ctx, 0, ctx->pc + 4);
1484 ctx->hflags |= MIPS_HFLAG_B;
1485 MIPS_DEBUG("j %08x", btarget);
1489 ctx->hflags |= MIPS_HFLAG_B;
1490 MIPS_DEBUG("jal %08x", btarget);
1493 ctx->hflags |= MIPS_HFLAG_BR;
1494 MIPS_DEBUG("jr %s", regnames[rs]);
1498 ctx->hflags |= MIPS_HFLAG_BR;
1499 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
1502 MIPS_INVAL("branch/jump");
1503 generate_exception(ctx, EXCP_RI);
1510 MIPS_DEBUG("beq %s, %s, %08x",
1511 regnames[rs], regnames[rt], btarget);
1515 MIPS_DEBUG("beql %s, %s, %08x",
1516 regnames[rs], regnames[rt], btarget);
1520 MIPS_DEBUG("bne %s, %s, %08x",
1521 regnames[rs], regnames[rt], btarget);
1525 MIPS_DEBUG("bnel %s, %s, %08x",
1526 regnames[rs], regnames[rt], btarget);
1530 MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
1534 MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
1538 MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
1544 MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
1548 MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
1552 MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
1556 MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
1560 MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
1564 MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
1568 MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
1573 MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
1575 ctx->hflags |= MIPS_HFLAG_BC;
1580 MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
1582 ctx->hflags |= MIPS_HFLAG_BL;
1587 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1588 blink, ctx->hflags, btarget);
1589 ctx->btarget = btarget;
1591 gen_op_set_T0(ctx->pc + 8);
1592 gen_op_store_T0_gpr(blink);
1597 /* special3 bitfield operations */
1598 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
1599 int rs, int lsb, int msb)
1601 GEN_LOAD_REG_TN(T1, rs);
1606 gen_op_ext(lsb, msb + 1);
1611 gen_op_ext(lsb, msb + 1 + 32);
1616 gen_op_ext(lsb + 32, msb + 1);
1619 gen_op_ext(lsb, msb + 1);
1624 GEN_LOAD_REG_TN(T2, rt);
1625 gen_op_ins(lsb, msb - lsb + 1);
1630 GEN_LOAD_REG_TN(T2, rt);
1631 gen_op_ins(lsb, msb - lsb + 1 + 32);
1636 GEN_LOAD_REG_TN(T2, rt);
1637 gen_op_ins(lsb + 32, msb - lsb + 1);
1642 GEN_LOAD_REG_TN(T2, rt);
1643 gen_op_ins(lsb, msb - lsb + 1);
1647 MIPS_INVAL("bitops");
1648 generate_exception(ctx, EXCP_RI);
1651 GEN_STORE_TN_REG(rt, T0);
1654 /* CP0 (MMU and control) */
1655 static void gen_mfc0 (DisasContext *ctx, int reg, int sel)
1657 const char *rn = "invalid";
1663 gen_op_mfc0_index();
1667 // gen_op_mfc0_mvpcontrol(); /* MT ASE */
1671 // gen_op_mfc0_mvpconf0(); /* MT ASE */
1675 // gen_op_mfc0_mvpconf1(); /* MT ASE */
1685 gen_op_mfc0_random();
1689 // gen_op_mfc0_vpecontrol(); /* MT ASE */
1693 // gen_op_mfc0_vpeconf0(); /* MT ASE */
1697 // gen_op_mfc0_vpeconf1(); /* MT ASE */
1701 // gen_op_mfc0_YQMask(); /* MT ASE */
1705 // gen_op_mfc0_vpeschedule(); /* MT ASE */
1709 // gen_op_mfc0_vpeschefback(); /* MT ASE */
1710 rn = "VPEScheFBack";
1713 // gen_op_mfc0_vpeopt(); /* MT ASE */
1723 gen_op_mfc0_entrylo0();
1727 // gen_op_mfc0_tcstatus(); /* MT ASE */
1731 // gen_op_mfc0_tcbind(); /* MT ASE */
1735 // gen_op_mfc0_tcrestart(); /* MT ASE */
1739 // gen_op_mfc0_tchalt(); /* MT ASE */
1743 // gen_op_mfc0_tccontext(); /* MT ASE */
1747 // gen_op_mfc0_tcschedule(); /* MT ASE */
1751 // gen_op_mfc0_tcschefback(); /* MT ASE */
1761 gen_op_mfc0_entrylo1();
1771 gen_op_mfc0_context();
1775 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1776 rn = "ContextConfig";
1785 gen_op_mfc0_pagemask();
1789 gen_op_mfc0_pagegrain();
1799 gen_op_mfc0_wired();
1803 // gen_op_mfc0_srsconf0(); /* shadow registers */
1807 // gen_op_mfc0_srsconf1(); /* shadow registers */
1811 // gen_op_mfc0_srsconf2(); /* shadow registers */
1815 // gen_op_mfc0_srsconf3(); /* shadow registers */
1819 // gen_op_mfc0_srsconf4(); /* shadow registers */
1829 gen_op_mfc0_hwrena();
1839 gen_op_mfc0_badvaddr();
1849 gen_op_mfc0_count();
1852 /* 6,7 are implementation dependent */
1860 gen_op_mfc0_entryhi();
1870 gen_op_mfc0_compare();
1873 /* 6,7 are implementation dependent */
1881 gen_op_mfc0_status();
1885 gen_op_mfc0_intctl();
1889 gen_op_mfc0_srsctl();
1893 // gen_op_mfc0_srsmap(); /* shadow registers */
1903 gen_op_mfc0_cause();
1927 gen_op_mfc0_ebase();
1937 gen_op_mfc0_config0();
1941 gen_op_mfc0_config1();
1945 gen_op_mfc0_config2();
1949 gen_op_mfc0_config3();
1952 /* 6,7 are implementation dependent */
1960 gen_op_mfc0_lladdr();
1970 gen_op_mfc0_watchlo0();
1974 // gen_op_mfc0_watchlo1();
1978 // gen_op_mfc0_watchlo2();
1982 // gen_op_mfc0_watchlo3();
1986 // gen_op_mfc0_watchlo4();
1990 // gen_op_mfc0_watchlo5();
1994 // gen_op_mfc0_watchlo6();
1998 // gen_op_mfc0_watchlo7();
2008 gen_op_mfc0_watchhi0();
2012 // gen_op_mfc0_watchhi1();
2016 // gen_op_mfc0_watchhi2();
2020 // gen_op_mfc0_watchhi3();
2024 // gen_op_mfc0_watchhi4();
2028 // gen_op_mfc0_watchhi5();
2032 // gen_op_mfc0_watchhi6();
2036 // gen_op_mfc0_watchhi7();
2046 /* 64 bit MMU only */
2047 gen_op_mfc0_xcontext();
2055 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2058 gen_op_mfc0_framemask();
2067 rn = "'Diagnostic"; /* implementation dependent */
2072 gen_op_mfc0_debug(); /* EJTAG support */
2076 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2077 rn = "TraceControl";
2080 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2081 rn = "TraceControl2";
2084 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2085 rn = "UserTraceData";
2088 // gen_op_mfc0_debug(); /* PDtrace support */
2098 gen_op_mfc0_depc(); /* EJTAG support */
2108 gen_op_mfc0_performance0();
2109 rn = "Performance0";
2112 // gen_op_mfc0_performance1();
2113 rn = "Performance1";
2116 // gen_op_mfc0_performance2();
2117 rn = "Performance2";
2120 // gen_op_mfc0_performance3();
2121 rn = "Performance3";
2124 // gen_op_mfc0_performance4();
2125 rn = "Performance4";
2128 // gen_op_mfc0_performance5();
2129 rn = "Performance5";
2132 // gen_op_mfc0_performance6();
2133 rn = "Performance6";
2136 // gen_op_mfc0_performance7();
2137 rn = "Performance7";
2162 gen_op_mfc0_taglo();
2169 gen_op_mfc0_datalo();
2182 gen_op_mfc0_taghi();
2189 gen_op_mfc0_datahi();
2199 gen_op_mfc0_errorepc();
2209 gen_op_mfc0_desave(); /* EJTAG support */
2219 #if defined MIPS_DEBUG_DISAS
2220 if (loglevel & CPU_LOG_TB_IN_ASM) {
2221 fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
2228 #if defined MIPS_DEBUG_DISAS
2229 if (loglevel & CPU_LOG_TB_IN_ASM) {
2230 fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
2234 generate_exception(ctx, EXCP_RI);
2237 static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
2239 const char *rn = "invalid";
2245 gen_op_mtc0_index();
2249 // gen_op_mtc0_mvpcontrol(); /* MT ASE */
2253 // gen_op_mtc0_mvpconf0(); /* MT ASE */
2257 // gen_op_mtc0_mvpconf1(); /* MT ASE */
2271 // gen_op_mtc0_vpecontrol(); /* MT ASE */
2275 // gen_op_mtc0_vpeconf0(); /* MT ASE */
2279 // gen_op_mtc0_vpeconf1(); /* MT ASE */
2283 // gen_op_mtc0_YQMask(); /* MT ASE */
2287 // gen_op_mtc0_vpeschedule(); /* MT ASE */
2291 // gen_op_mtc0_vpeschefback(); /* MT ASE */
2292 rn = "VPEScheFBack";
2295 // gen_op_mtc0_vpeopt(); /* MT ASE */
2305 gen_op_mtc0_entrylo0();
2309 // gen_op_mtc0_tcstatus(); /* MT ASE */
2313 // gen_op_mtc0_tcbind(); /* MT ASE */
2317 // gen_op_mtc0_tcrestart(); /* MT ASE */
2321 // gen_op_mtc0_tchalt(); /* MT ASE */
2325 // gen_op_mtc0_tccontext(); /* MT ASE */
2329 // gen_op_mtc0_tcschedule(); /* MT ASE */
2333 // gen_op_mtc0_tcschefback(); /* MT ASE */
2343 gen_op_mtc0_entrylo1();
2353 gen_op_mtc0_context();
2357 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2358 rn = "ContextConfig";
2367 gen_op_mtc0_pagemask();
2371 gen_op_mtc0_pagegrain();
2381 gen_op_mtc0_wired();
2385 // gen_op_mtc0_srsconf0(); /* shadow registers */
2389 // gen_op_mtc0_srsconf1(); /* shadow registers */
2393 // gen_op_mtc0_srsconf2(); /* shadow registers */
2397 // gen_op_mtc0_srsconf3(); /* shadow registers */
2401 // gen_op_mtc0_srsconf4(); /* shadow registers */
2411 gen_op_mtc0_hwrena();
2425 gen_op_mtc0_count();
2428 /* 6,7 are implementation dependent */
2432 /* Stop translation as we may have switched the execution mode */
2433 ctx->bstate = BS_STOP;
2438 gen_op_mtc0_entryhi();
2448 gen_op_mtc0_compare();
2451 /* 6,7 are implementation dependent */
2455 /* Stop translation as we may have switched the execution mode */
2456 ctx->bstate = BS_STOP;
2461 gen_op_mtc0_status();
2465 gen_op_mtc0_intctl();
2469 gen_op_mtc0_srsctl();
2473 // gen_op_mtc0_srsmap(); /* shadow registers */
2479 /* Stop translation as we may have switched the execution mode */
2480 ctx->bstate = BS_STOP;
2485 gen_op_mtc0_cause();
2491 /* Stop translation as we may have switched the execution mode */
2492 ctx->bstate = BS_STOP;
2511 gen_op_mtc0_ebase();
2521 gen_op_mtc0_config0();
2529 gen_op_mtc0_config2();
2536 /* 6,7 are implementation dependent */
2538 rn = "Invalid config selector";
2541 /* Stop translation as we may have switched the execution mode */
2542 ctx->bstate = BS_STOP;
2557 gen_op_mtc0_watchlo0();
2561 // gen_op_mtc0_watchlo1();
2565 // gen_op_mtc0_watchlo2();
2569 // gen_op_mtc0_watchlo3();
2573 // gen_op_mtc0_watchlo4();
2577 // gen_op_mtc0_watchlo5();
2581 // gen_op_mtc0_watchlo6();
2585 // gen_op_mtc0_watchlo7();
2595 gen_op_mtc0_watchhi0();
2599 // gen_op_mtc0_watchhi1();
2603 // gen_op_mtc0_watchhi2();
2607 // gen_op_mtc0_watchhi3();
2611 // gen_op_mtc0_watchhi4();
2615 // gen_op_mtc0_watchhi5();
2619 // gen_op_mtc0_watchhi6();
2623 // gen_op_mtc0_watchhi7();
2633 /* 64 bit MMU only */
2634 gen_op_mtc0_xcontext();
2642 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2645 gen_op_mtc0_framemask();
2654 rn = "Diagnostic"; /* implementation dependent */
2659 gen_op_mtc0_debug(); /* EJTAG support */
2663 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
2664 rn = "TraceControl";
2667 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2668 rn = "TraceControl2";
2671 // gen_op_mtc0_usertracedata(); /* PDtrace support */
2672 rn = "UserTraceData";
2675 // gen_op_mtc0_debug(); /* PDtrace support */
2681 /* Stop translation as we may have switched the execution mode */
2682 ctx->bstate = BS_STOP;
2687 gen_op_mtc0_depc(); /* EJTAG support */
2697 gen_op_mtc0_performance0();
2698 rn = "Performance0";
2701 // gen_op_mtc0_performance1();
2702 rn = "Performance1";
2705 // gen_op_mtc0_performance2();
2706 rn = "Performance2";
2709 // gen_op_mtc0_performance3();
2710 rn = "Performance3";
2713 // gen_op_mtc0_performance4();
2714 rn = "Performance4";
2717 // gen_op_mtc0_performance5();
2718 rn = "Performance5";
2721 // gen_op_mtc0_performance6();
2722 rn = "Performance6";
2725 // gen_op_mtc0_performance7();
2726 rn = "Performance7";
2752 gen_op_mtc0_taglo();
2759 gen_op_mtc0_datalo();
2772 gen_op_mtc0_taghi();
2779 gen_op_mtc0_datahi();
2790 gen_op_mtc0_errorepc();
2800 gen_op_mtc0_desave(); /* EJTAG support */
2806 /* Stop translation as we may have switched the execution mode */
2807 ctx->bstate = BS_STOP;
2812 #if defined MIPS_DEBUG_DISAS
2813 if (loglevel & CPU_LOG_TB_IN_ASM) {
2814 fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
2821 #if defined MIPS_DEBUG_DISAS
2822 if (loglevel & CPU_LOG_TB_IN_ASM) {
2823 fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
2827 generate_exception(ctx, EXCP_RI);
2830 static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
2832 const char *rn = "invalid";
2838 gen_op_mfc0_index();
2842 // gen_op_dmfc0_mvpcontrol(); /* MT ASE */
2846 // gen_op_dmfc0_mvpconf0(); /* MT ASE */
2850 // gen_op_dmfc0_mvpconf1(); /* MT ASE */
2860 gen_op_mfc0_random();
2864 // gen_op_dmfc0_vpecontrol(); /* MT ASE */
2868 // gen_op_dmfc0_vpeconf0(); /* MT ASE */
2872 // gen_op_dmfc0_vpeconf1(); /* MT ASE */
2876 // gen_op_dmfc0_YQMask(); /* MT ASE */
2880 // gen_op_dmfc0_vpeschedule(); /* MT ASE */
2884 // gen_op_dmfc0_vpeschefback(); /* MT ASE */
2885 rn = "VPEScheFBack";
2888 // gen_op_dmfc0_vpeopt(); /* MT ASE */
2898 gen_op_dmfc0_entrylo0();
2902 // gen_op_dmfc0_tcstatus(); /* MT ASE */
2906 // gen_op_dmfc0_tcbind(); /* MT ASE */
2910 // gen_op_dmfc0_tcrestart(); /* MT ASE */
2914 // gen_op_dmfc0_tchalt(); /* MT ASE */
2918 // gen_op_dmfc0_tccontext(); /* MT ASE */
2922 // gen_op_dmfc0_tcschedule(); /* MT ASE */
2926 // gen_op_dmfc0_tcschefback(); /* MT ASE */
2936 gen_op_dmfc0_entrylo1();
2946 gen_op_dmfc0_context();
2950 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
2951 rn = "ContextConfig";
2960 gen_op_mfc0_pagemask();
2964 gen_op_mfc0_pagegrain();
2974 gen_op_mfc0_wired();
2978 // gen_op_dmfc0_srsconf0(); /* shadow registers */
2982 // gen_op_dmfc0_srsconf1(); /* shadow registers */
2986 // gen_op_dmfc0_srsconf2(); /* shadow registers */
2990 // gen_op_dmfc0_srsconf3(); /* shadow registers */
2994 // gen_op_dmfc0_srsconf4(); /* shadow registers */
3004 gen_op_mfc0_hwrena();
3014 gen_op_dmfc0_badvaddr();
3024 gen_op_mfc0_count();
3027 /* 6,7 are implementation dependent */
3035 gen_op_dmfc0_entryhi();
3045 gen_op_mfc0_compare();
3048 /* 6,7 are implementation dependent */
3056 gen_op_mfc0_status();
3060 gen_op_mfc0_intctl();
3064 gen_op_mfc0_srsctl();
3068 gen_op_mfc0_srsmap(); /* shadow registers */
3078 gen_op_mfc0_cause();
3102 gen_op_mfc0_ebase();
3112 gen_op_mfc0_config0();
3116 gen_op_mfc0_config1();
3120 gen_op_mfc0_config2();
3124 gen_op_mfc0_config3();
3127 /* 6,7 are implementation dependent */
3135 gen_op_dmfc0_lladdr();
3145 gen_op_dmfc0_watchlo0();
3149 // gen_op_dmfc0_watchlo1();
3153 // gen_op_dmfc0_watchlo2();
3157 // gen_op_dmfc0_watchlo3();
3161 // gen_op_dmfc0_watchlo4();
3165 // gen_op_dmfc0_watchlo5();
3169 // gen_op_dmfc0_watchlo6();
3173 // gen_op_dmfc0_watchlo7();
3183 gen_op_mfc0_watchhi0();
3187 // gen_op_mfc0_watchhi1();
3191 // gen_op_mfc0_watchhi2();
3195 // gen_op_mfc0_watchhi3();
3199 // gen_op_mfc0_watchhi4();
3203 // gen_op_mfc0_watchhi5();
3207 // gen_op_mfc0_watchhi6();
3211 // gen_op_mfc0_watchhi7();
3221 /* 64 bit MMU only */
3222 gen_op_dmfc0_xcontext();
3230 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3233 gen_op_mfc0_framemask();
3242 rn = "'Diagnostic"; /* implementation dependent */
3247 gen_op_mfc0_debug(); /* EJTAG support */
3251 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3252 rn = "TraceControl";
3255 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3256 rn = "TraceControl2";
3259 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3260 rn = "UserTraceData";
3263 // gen_op_dmfc0_debug(); /* PDtrace support */
3273 gen_op_dmfc0_depc(); /* EJTAG support */
3283 gen_op_mfc0_performance0();
3284 rn = "Performance0";
3287 // gen_op_dmfc0_performance1();
3288 rn = "Performance1";
3291 // gen_op_dmfc0_performance2();
3292 rn = "Performance2";
3295 // gen_op_dmfc0_performance3();
3296 rn = "Performance3";
3299 // gen_op_dmfc0_performance4();
3300 rn = "Performance4";
3303 // gen_op_dmfc0_performance5();
3304 rn = "Performance5";
3307 // gen_op_dmfc0_performance6();
3308 rn = "Performance6";
3311 // gen_op_dmfc0_performance7();
3312 rn = "Performance7";
3337 gen_op_mfc0_taglo();
3344 gen_op_mfc0_datalo();
3357 gen_op_mfc0_taghi();
3364 gen_op_mfc0_datahi();
3374 gen_op_dmfc0_errorepc();
3384 gen_op_mfc0_desave(); /* EJTAG support */
3394 #if defined MIPS_DEBUG_DISAS
3395 if (loglevel & CPU_LOG_TB_IN_ASM) {
3396 fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
3403 #if defined MIPS_DEBUG_DISAS
3404 if (loglevel & CPU_LOG_TB_IN_ASM) {
3405 fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
3409 generate_exception(ctx, EXCP_RI);
3412 static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
3414 const char *rn = "invalid";
3420 gen_op_mtc0_index();
3424 // gen_op_dmtc0_mvpcontrol(); /* MT ASE */
3428 // gen_op_dmtc0_mvpconf0(); /* MT ASE */
3432 // gen_op_dmtc0_mvpconf1(); /* MT ASE */
3446 // gen_op_dmtc0_vpecontrol(); /* MT ASE */
3450 // gen_op_dmtc0_vpeconf0(); /* MT ASE */
3454 // gen_op_dmtc0_vpeconf1(); /* MT ASE */
3458 // gen_op_dmtc0_YQMask(); /* MT ASE */
3462 // gen_op_dmtc0_vpeschedule(); /* MT ASE */
3466 // gen_op_dmtc0_vpeschefback(); /* MT ASE */
3467 rn = "VPEScheFBack";
3470 // gen_op_dmtc0_vpeopt(); /* MT ASE */
3480 gen_op_dmtc0_entrylo0();
3484 // gen_op_dmtc0_tcstatus(); /* MT ASE */
3488 // gen_op_dmtc0_tcbind(); /* MT ASE */
3492 // gen_op_dmtc0_tcrestart(); /* MT ASE */
3496 // gen_op_dmtc0_tchalt(); /* MT ASE */
3500 // gen_op_dmtc0_tccontext(); /* MT ASE */
3504 // gen_op_dmtc0_tcschedule(); /* MT ASE */
3508 // gen_op_dmtc0_tcschefback(); /* MT ASE */
3518 gen_op_dmtc0_entrylo1();
3528 gen_op_dmtc0_context();
3532 // gen_op_dmtc0_contextconfig(); /* SmartMIPS ASE */
3533 rn = "ContextConfig";
3542 gen_op_mtc0_pagemask();
3546 gen_op_mtc0_pagegrain();
3556 gen_op_mtc0_wired();
3560 // gen_op_dmtc0_srsconf0(); /* shadow registers */
3564 // gen_op_dmtc0_srsconf1(); /* shadow registers */
3568 // gen_op_dmtc0_srsconf2(); /* shadow registers */
3572 // gen_op_dmtc0_srsconf3(); /* shadow registers */
3576 // gen_op_dmtc0_srsconf4(); /* shadow registers */
3586 gen_op_mtc0_hwrena();
3600 gen_op_mtc0_count();
3603 /* 6,7 are implementation dependent */
3607 /* Stop translation as we may have switched the execution mode */
3608 ctx->bstate = BS_STOP;
3613 gen_op_mtc0_entryhi();
3623 gen_op_mtc0_compare();
3626 /* 6,7 are implementation dependent */
3630 /* Stop translation as we may have switched the execution mode */
3631 ctx->bstate = BS_STOP;
3636 gen_op_mtc0_status();
3640 gen_op_mtc0_intctl();
3644 gen_op_mtc0_srsctl();
3648 gen_op_mtc0_srsmap(); /* shadow registers */
3654 /* Stop translation as we may have switched the execution mode */
3655 ctx->bstate = BS_STOP;
3660 gen_op_mtc0_cause();
3666 /* Stop translation as we may have switched the execution mode */
3667 ctx->bstate = BS_STOP;
3686 gen_op_mtc0_ebase();
3696 gen_op_mtc0_config0();
3704 gen_op_mtc0_config2();
3711 /* 6,7 are implementation dependent */
3713 rn = "Invalid config selector";
3716 /* Stop translation as we may have switched the execution mode */
3717 ctx->bstate = BS_STOP;
3732 gen_op_dmtc0_watchlo0();
3736 // gen_op_dmtc0_watchlo1();
3740 // gen_op_dmtc0_watchlo2();
3744 // gen_op_dmtc0_watchlo3();
3748 // gen_op_dmtc0_watchlo4();
3752 // gen_op_dmtc0_watchlo5();
3756 // gen_op_dmtc0_watchlo6();
3760 // gen_op_dmtc0_watchlo7();
3770 gen_op_mtc0_watchhi0();
3774 // gen_op_dmtc0_watchhi1();
3778 // gen_op_dmtc0_watchhi2();
3782 // gen_op_dmtc0_watchhi3();
3786 // gen_op_dmtc0_watchhi4();
3790 // gen_op_dmtc0_watchhi5();
3794 // gen_op_dmtc0_watchhi6();
3798 // gen_op_dmtc0_watchhi7();
3808 /* 64 bit MMU only */
3809 gen_op_dmtc0_xcontext();
3817 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3820 gen_op_mtc0_framemask();
3829 rn = "Diagnostic"; /* implementation dependent */
3834 gen_op_mtc0_debug(); /* EJTAG support */
3838 // gen_op_dmtc0_tracecontrol(); /* PDtrace support */
3839 rn = "TraceControl";
3842 // gen_op_dmtc0_tracecontrol2(); /* PDtrace support */
3843 rn = "TraceControl2";
3846 // gen_op_dmtc0_usertracedata(); /* PDtrace support */
3847 rn = "UserTraceData";
3850 // gen_op_dmtc0_debug(); /* PDtrace support */
3856 /* Stop translation as we may have switched the execution mode */
3857 ctx->bstate = BS_STOP;
3862 gen_op_dmtc0_depc(); /* EJTAG support */
3872 gen_op_mtc0_performance0();
3873 rn = "Performance0";
3876 // gen_op_dmtc0_performance1();
3877 rn = "Performance1";
3880 // gen_op_dmtc0_performance2();
3881 rn = "Performance2";
3884 // gen_op_dmtc0_performance3();
3885 rn = "Performance3";
3888 // gen_op_dmtc0_performance4();
3889 rn = "Performance4";
3892 // gen_op_dmtc0_performance5();
3893 rn = "Performance5";
3896 // gen_op_dmtc0_performance6();
3897 rn = "Performance6";
3900 // gen_op_dmtc0_performance7();
3901 rn = "Performance7";
3927 gen_op_mtc0_taglo();
3934 gen_op_mtc0_datalo();
3947 gen_op_mtc0_taghi();
3954 gen_op_mtc0_datahi();
3965 gen_op_dmtc0_errorepc();
3975 gen_op_mtc0_desave(); /* EJTAG support */
3981 /* Stop translation as we may have switched the execution mode */
3982 ctx->bstate = BS_STOP;
3987 #if defined MIPS_DEBUG_DISAS
3988 if (loglevel & CPU_LOG_TB_IN_ASM) {
3989 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
3996 #if defined MIPS_DEBUG_DISAS
3997 if (loglevel & CPU_LOG_TB_IN_ASM) {
3998 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
4002 generate_exception(ctx, EXCP_RI);
4005 static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
4007 const char *opn = "unk";
4009 if ((!ctx->CP0_Status & (1 << CP0St_CU0) &&
4010 (ctx->hflags & MIPS_HFLAG_UM)) &&
4011 !(ctx->hflags & MIPS_HFLAG_ERL) &&
4012 !(ctx->hflags & MIPS_HFLAG_EXL)) {
4013 if (loglevel & CPU_LOG_TB_IN_ASM) {
4014 fprintf(logfile, "CP0 is not usable\n");
4016 generate_exception (ctx, EXCP_CpU);
4026 gen_mfc0(ctx, rd, ctx->opcode & 0x7);
4027 gen_op_store_T0_gpr(rt);
4031 /* If we get an exception, we want to restart at next instruction */
4032 /* XXX: breaks for mtc in delay slot */
4034 save_cpu_state(ctx, 1);
4036 GEN_LOAD_REG_TN(T0, rt);
4037 gen_mtc0(ctx, rd, ctx->opcode & 0x7);
4045 gen_dmfc0(ctx, rd, ctx->opcode & 0x7);
4046 gen_op_store_T0_gpr(rt);
4050 /* If we get an exception, we want to restart at next instruction */
4051 /* XXX: breaks for dmtc in delay slot */
4053 save_cpu_state(ctx, 1);
4055 GEN_LOAD_REG_TN(T0, rt);
4056 gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
4059 #if defined(MIPS_USES_R4K_TLB)
4079 save_cpu_state(ctx, 0);
4081 ctx->bstate = BS_EXCP;
4085 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
4086 generate_exception(ctx, EXCP_RI);
4088 save_cpu_state(ctx, 0);
4090 ctx->bstate = BS_EXCP;
4095 /* If we get an exception, we want to restart at next instruction */
4097 save_cpu_state(ctx, 1);
4100 ctx->bstate = BS_EXCP;
4103 if (loglevel & CPU_LOG_TB_IN_ASM) {
4104 fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
4105 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4106 ((ctx->opcode >> 16) & 0x1F));
4108 generate_exception(ctx, EXCP_RI);
4111 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
4114 #ifdef MIPS_USES_FPU
4116 /* CP1 Branches (before delay slot) */
4117 static void gen_compute_branch1 (DisasContext *ctx, uint32_t op,
4120 target_ulong btarget;
4122 btarget = ctx->pc + 4 + offset;
4127 MIPS_DEBUG("bc1f " TLSZ, btarget);
4131 MIPS_DEBUG("bc1fl " TLSZ, btarget);
4135 MIPS_DEBUG("bc1t " TLSZ, btarget);
4137 ctx->hflags |= MIPS_HFLAG_BC;
4141 MIPS_DEBUG("bc1tl " TLSZ, btarget);
4143 ctx->hflags |= MIPS_HFLAG_BL;
4146 MIPS_INVAL("cp1 branch/jump");
4147 generate_exception_err (ctx, EXCP_RI, 1);
4152 MIPS_DEBUG("enter ds: cond %02x target " TLSZ,
4153 ctx->hflags, btarget);
4154 ctx->btarget = btarget;
4159 /* Coprocessor 1 (FPU) */
4160 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
4162 const char *opn = "unk";
4166 GEN_LOAD_FREG_FTN(WT0, fs);
4168 GEN_STORE_TN_REG(rt, T0);
4172 GEN_LOAD_REG_TN(T0, rt);
4174 GEN_STORE_FTN_FREG(fs, WT0);
4178 if (fs != 0 && fs != 31) {
4179 MIPS_INVAL("cfc1 freg");
4180 generate_exception_err (ctx, EXCP_RI, 1);
4183 GEN_LOAD_IMM_TN(T1, fs);
4185 GEN_STORE_TN_REG(rt, T0);
4189 if (fs != 0 && fs != 31) {
4190 MIPS_INVAL("ctc1 freg");
4191 generate_exception_err (ctx, EXCP_RI, 1);
4194 GEN_LOAD_IMM_TN(T1, fs);
4195 GEN_LOAD_REG_TN(T0, rt);
4201 /* Not implemented, fallthrough. */
4203 if (loglevel & CPU_LOG_TB_IN_ASM) {
4204 fprintf(logfile, "Invalid CP1 opcode: %08x %03x %03x %03x\n",
4205 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4206 ((ctx->opcode >> 16) & 0x1F));
4208 generate_exception_err (ctx, EXCP_RI, 1);
4211 MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
4214 /* verify if floating point register is valid; an operation is not defined
4215 * if bit 0 of any register specification is set and the FR bit in the
4216 * Status register equals zero, since the register numbers specify an
4217 * even-odd pair of adjacent coprocessor general registers. When the FR bit
4218 * in the Status register equals one, both even and odd register numbers
4221 * Multiple float registers can be checked by calling
4222 * CHECK_FR(ctx, freg1 | freg2 | ... | fregN);
4224 #define CHECK_FR(ctx, freg) do { \
4225 if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
4226 generate_exception_err (ctx, EXCP_RI, 1); \
4231 #define FOP(func, fmt) (((fmt) << 21) | (func))
4233 static void gen_farith (DisasContext *ctx, uint32_t op1, int ft, int fs, int fd)
4235 const char *opn = "unk";
4236 const char *condnames[] = {
4255 uint32_t func = ctx->opcode & 0x3f;
4257 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
4259 CHECK_FR(ctx, fs | ft | fd);
4260 GEN_LOAD_FREG_FTN(DT0, fs);
4261 GEN_LOAD_FREG_FTN(DT1, ft);
4262 gen_op_float_add_d();
4263 GEN_STORE_FTN_FREG(fd, DT2);
4268 CHECK_FR(ctx, fs | ft | fd);
4269 GEN_LOAD_FREG_FTN(DT0, fs);
4270 GEN_LOAD_FREG_FTN(DT1, ft);
4271 gen_op_float_sub_d();
4272 GEN_STORE_FTN_FREG(fd, DT2);
4277 CHECK_FR(ctx, fs | ft | fd);
4278 GEN_LOAD_FREG_FTN(DT0, fs);
4279 GEN_LOAD_FREG_FTN(DT1, ft);
4280 gen_op_float_mul_d();
4281 GEN_STORE_FTN_FREG(fd, DT2);
4286 CHECK_FR(ctx, fs | ft | fd);
4287 GEN_LOAD_FREG_FTN(DT0, fs);
4288 GEN_LOAD_FREG_FTN(DT1, ft);
4289 gen_op_float_div_d();
4290 GEN_STORE_FTN_FREG(fd, DT2);
4295 CHECK_FR(ctx, fs | fd);
4296 GEN_LOAD_FREG_FTN(DT0, fs);
4297 gen_op_float_sqrt_d();
4298 GEN_STORE_FTN_FREG(fd, DT2);
4302 CHECK_FR(ctx, fs | fd);
4303 GEN_LOAD_FREG_FTN(DT0, fs);
4304 gen_op_float_abs_d();
4305 GEN_STORE_FTN_FREG(fd, DT2);
4309 CHECK_FR(ctx, fs | fd);
4310 GEN_LOAD_FREG_FTN(DT0, fs);
4311 gen_op_float_mov_d();
4312 GEN_STORE_FTN_FREG(fd, DT2);
4316 CHECK_FR(ctx, fs | fd);
4317 GEN_LOAD_FREG_FTN(DT0, fs);
4318 gen_op_float_chs_d();
4319 GEN_STORE_FTN_FREG(fd, DT2);
4327 CHECK_FR(ctx, fs | fd);
4328 GEN_LOAD_FREG_FTN(DT0, fs);
4329 gen_op_float_roundw_d();
4330 GEN_STORE_FTN_FREG(fd, WT2);
4334 CHECK_FR(ctx, fs | fd);
4335 GEN_LOAD_FREG_FTN(DT0, fs);
4336 gen_op_float_truncw_d();
4337 GEN_STORE_FTN_FREG(fd, WT2);
4341 CHECK_FR(ctx, fs | fd);
4342 GEN_LOAD_FREG_FTN(DT0, fs);
4343 gen_op_float_ceilw_d();
4344 GEN_STORE_FTN_FREG(fd, WT2);
4348 CHECK_FR(ctx, fs | fd);
4349 GEN_LOAD_FREG_FTN(DT0, fs);
4350 gen_op_float_floorw_d();
4351 GEN_STORE_FTN_FREG(fd, WT2);
4354 case FOP(33, 16): /* cvt.d.s */
4355 CHECK_FR(ctx, fs | fd);
4356 GEN_LOAD_FREG_FTN(WT0, fs);
4357 gen_op_float_cvtd_s();
4358 GEN_STORE_FTN_FREG(fd, DT2);
4361 case FOP(33, 20): /* cvt.d.w */
4362 CHECK_FR(ctx, fs | fd);
4363 GEN_LOAD_FREG_FTN(WT0, fs);
4364 gen_op_float_cvtd_w();
4365 GEN_STORE_FTN_FREG(fd, DT2);
4384 CHECK_FR(ctx, fs | ft);
4385 GEN_LOAD_FREG_FTN(DT0, fs);
4386 GEN_LOAD_FREG_FTN(DT1, ft);
4388 opn = condnames[func-48];
4391 CHECK_FR(ctx, fs | ft | fd);
4392 GEN_LOAD_FREG_FTN(WT0, fs);
4393 GEN_LOAD_FREG_FTN(WT1, ft);
4394 gen_op_float_add_s();
4395 GEN_STORE_FTN_FREG(fd, WT2);
4400 CHECK_FR(ctx, fs | ft | fd);
4401 GEN_LOAD_FREG_FTN(WT0, fs);
4402 GEN_LOAD_FREG_FTN(WT1, ft);
4403 gen_op_float_sub_s();
4404 GEN_STORE_FTN_FREG(fd, WT2);
4409 CHECK_FR(ctx, fs | ft | fd);
4410 GEN_LOAD_FREG_FTN(WT0, fs);
4411 GEN_LOAD_FREG_FTN(WT1, ft);
4412 gen_op_float_mul_s();
4413 GEN_STORE_FTN_FREG(fd, WT2);
4418 CHECK_FR(ctx, fs | ft | fd);
4419 GEN_LOAD_FREG_FTN(WT0, fs);
4420 GEN_LOAD_FREG_FTN(WT1, ft);
4421 gen_op_float_div_s();
4422 GEN_STORE_FTN_FREG(fd, WT2);
4427 CHECK_FR(ctx, fs | fd);
4428 GEN_LOAD_FREG_FTN(WT0, fs);
4429 gen_op_float_sqrt_s();
4430 GEN_STORE_FTN_FREG(fd, WT2);
4434 CHECK_FR(ctx, fs | fd);
4435 GEN_LOAD_FREG_FTN(WT0, fs);
4436 gen_op_float_abs_s();
4437 GEN_STORE_FTN_FREG(fd, WT2);
4441 CHECK_FR(ctx, fs | fd);
4442 GEN_LOAD_FREG_FTN(WT0, fs);
4443 gen_op_float_mov_s();
4444 GEN_STORE_FTN_FREG(fd, WT2);
4448 CHECK_FR(ctx, fs | fd);
4449 GEN_LOAD_FREG_FTN(WT0, fs);
4450 gen_op_float_chs_s();
4451 GEN_STORE_FTN_FREG(fd, WT2);
4455 CHECK_FR(ctx, fs | fd);
4456 GEN_LOAD_FREG_FTN(WT0, fs);
4457 gen_op_float_roundw_s();
4458 GEN_STORE_FTN_FREG(fd, WT2);
4462 CHECK_FR(ctx, fs | fd);
4463 GEN_LOAD_FREG_FTN(WT0, fs);
4464 gen_op_float_truncw_s();
4465 GEN_STORE_FTN_FREG(fd, WT2);
4468 case FOP(32, 17): /* cvt.s.d */
4469 CHECK_FR(ctx, fs | fd);
4470 GEN_LOAD_FREG_FTN(DT0, fs);
4471 gen_op_float_cvts_d();
4472 GEN_STORE_FTN_FREG(fd, WT2);
4475 case FOP(32, 20): /* cvt.s.w */
4476 CHECK_FR(ctx, fs | fd);
4477 GEN_LOAD_FREG_FTN(WT0, fs);
4478 gen_op_float_cvts_w();
4479 GEN_STORE_FTN_FREG(fd, WT2);
4482 case FOP(36, 16): /* cvt.w.s */
4483 CHECK_FR(ctx, fs | fd);
4484 GEN_LOAD_FREG_FTN(WT0, fs);
4485 gen_op_float_cvtw_s();
4486 GEN_STORE_FTN_FREG(fd, WT2);
4489 case FOP(36, 17): /* cvt.w.d */
4490 CHECK_FR(ctx, fs | fd);
4491 GEN_LOAD_FREG_FTN(DT0, fs);
4492 gen_op_float_cvtw_d();
4493 GEN_STORE_FTN_FREG(fd, WT2);
4512 CHECK_FR(ctx, fs | ft);
4513 GEN_LOAD_FREG_FTN(WT0, fs);
4514 GEN_LOAD_FREG_FTN(WT1, ft);
4516 opn = condnames[func-48];
4519 if (loglevel & CPU_LOG_TB_IN_ASM) {
4520 fprintf(logfile, "Invalid FP arith function: %08x %03x %03x %03x\n",
4521 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
4522 ((ctx->opcode >> 16) & 0x1F));
4524 generate_exception_err (ctx, EXCP_RI, 1);
4528 MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
4530 MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
4533 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
4538 ccbit = 1 << (24 + cc);
4542 gen_op_movf(ccbit, rd, rs);
4544 gen_op_movt(ccbit, rd, rs);
4547 #endif /* MIPS_USES_FPU */
4549 /* ISA extensions (ASEs) */
4550 /* MIPS16 extension to MIPS32 */
4551 /* SmartMIPS extension to MIPS32 */
4553 #ifdef MIPS_HAS_MIPS64
4554 /* Coprocessor 3 (FPU) */
4556 /* MDMX extension to MIPS64 */
4557 /* MIPS-3D extension to MIPS64 */
4561 static void gen_blikely(DisasContext *ctx)
4564 l1 = gen_new_label();
4566 gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
4567 gen_goto_tb(ctx, 1, ctx->pc + 4);
4571 static void decode_opc (DisasContext *ctx)
4575 uint32_t op, op1, op2;
4578 /* make sure instructions are on a word boundary */
4579 if (ctx->pc & 0x3) {
4580 generate_exception(ctx, EXCP_AdEL);
4584 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
4585 /* Handle blikely not taken case */
4586 MIPS_DEBUG("blikely condition (" TLSZ ")", ctx->pc + 4);
4589 op = MASK_OP_MAJOR(ctx->opcode);
4590 rs = (ctx->opcode >> 21) & 0x1f;
4591 rt = (ctx->opcode >> 16) & 0x1f;
4592 rd = (ctx->opcode >> 11) & 0x1f;
4593 sa = (ctx->opcode >> 6) & 0x1f;
4594 imm = (int16_t)ctx->opcode;
4597 op1 = MASK_SPECIAL(ctx->opcode);
4599 case OPC_SLL: /* Arithmetic with immediate */
4600 case OPC_SRL ... OPC_SRA:
4601 gen_arith_imm(ctx, op1, rd, rt, sa);
4603 case OPC_SLLV: /* Arithmetic */
4604 case OPC_SRLV ... OPC_SRAV:
4605 case OPC_MOVZ ... OPC_MOVN:
4606 case OPC_ADD ... OPC_NOR:
4607 case OPC_SLT ... OPC_SLTU:
4608 gen_arith(ctx, op1, rd, rs, rt);
4610 case OPC_MULT ... OPC_DIVU:
4611 gen_muldiv(ctx, op1, rs, rt);
4613 case OPC_JR ... OPC_JALR:
4614 gen_compute_branch(ctx, op1, rs, rd, sa);
4616 case OPC_TGE ... OPC_TEQ: /* Traps */
4618 gen_trap(ctx, op1, rs, rt, -1);
4620 case OPC_MFHI: /* Move from HI/LO */
4622 gen_HILO(ctx, op1, rd);
4625 case OPC_MTLO: /* Move to HI/LO */
4626 gen_HILO(ctx, op1, rs);
4628 case OPC_PMON: /* Pmon entry point */
4632 generate_exception(ctx, EXCP_SYSCALL);
4633 ctx->bstate = BS_EXCP;
4636 generate_exception(ctx, EXCP_BREAK);
4638 case OPC_SPIM: /* SPIM ? */
4639 /* Implemented as RI exception for now. */
4640 MIPS_INVAL("spim (unofficial)");
4641 generate_exception(ctx, EXCP_RI);
4644 /* Treat as a noop. */
4647 #ifdef MIPS_USES_FPU
4649 gen_op_cp1_enabled();
4650 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
4651 (ctx->opcode >> 16) & 1);
4655 #ifdef MIPS_HAS_MIPS64
4656 /* MIPS64 specific opcodes */
4658 case OPC_DSRL ... OPC_DSRA:
4660 case OPC_DSRL32 ... OPC_DSRA32:
4661 gen_arith_imm(ctx, op1, rd, rt, sa);
4664 case OPC_DSRLV ... OPC_DSRAV:
4665 case OPC_DADD ... OPC_DSUBU:
4666 gen_arith(ctx, op1, rd, rs, rt);
4668 case OPC_DMULT ... OPC_DDIVU:
4669 gen_muldiv(ctx, op1, rs, rt);
4672 default: /* Invalid */
4673 MIPS_INVAL("special");
4674 generate_exception(ctx, EXCP_RI);
4679 op1 = MASK_SPECIAL2(ctx->opcode);
4681 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
4682 case OPC_MSUB ... OPC_MSUBU:
4683 gen_muldiv(ctx, op1, rs, rt);
4686 gen_arith(ctx, op1, rd, rs, rt);
4688 case OPC_CLZ ... OPC_CLO:
4689 gen_cl(ctx, op1, rd, rs);
4692 /* XXX: not clear which exception should be raised
4693 * when in debug mode...
4695 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
4696 generate_exception(ctx, EXCP_DBp);
4698 generate_exception(ctx, EXCP_DBp);
4700 /* Treat as a noop */
4702 #ifdef MIPS_HAS_MIPS64
4703 case OPC_DCLZ ... OPC_DCLO:
4704 gen_cl(ctx, op1, rd, rs);
4707 default: /* Invalid */
4708 MIPS_INVAL("special2");
4709 generate_exception(ctx, EXCP_RI);
4714 op1 = MASK_SPECIAL3(ctx->opcode);
4718 gen_bitops(ctx, op1, rt, rs, sa, rd);
4721 op2 = MASK_BSHFL(ctx->opcode);
4724 GEN_LOAD_REG_TN(T1, rt);
4728 GEN_LOAD_REG_TN(T1, rt);
4732 GEN_LOAD_REG_TN(T1, rt);
4735 default: /* Invalid */
4736 MIPS_INVAL("bshfl");
4737 generate_exception(ctx, EXCP_RI);
4740 GEN_STORE_TN_REG(rd, T0);
4745 gen_op_rdhwr_cpunum();
4748 gen_op_rdhwr_synci_step();
4754 gen_op_rdhwr_ccres();
4756 default: /* Invalid */
4757 MIPS_INVAL("rdhwr");
4758 generate_exception(ctx, EXCP_RI);
4761 GEN_STORE_TN_REG(rt, T0);
4763 #ifdef MIPS_HAS_MIPS64
4764 case OPC_DEXTM ... OPC_DEXT:
4765 case OPC_DINSM ... OPC_DINS:
4766 gen_bitops(ctx, op1, rt, rs, sa, rd);
4769 op2 = MASK_DBSHFL(ctx->opcode);
4772 GEN_LOAD_REG_TN(T1, rt);
4776 GEN_LOAD_REG_TN(T1, rt);
4779 default: /* Invalid */
4780 MIPS_INVAL("dbshfl");
4781 generate_exception(ctx, EXCP_RI);
4784 GEN_STORE_TN_REG(rd, T0);
4786 default: /* Invalid */
4787 MIPS_INVAL("special3");
4788 generate_exception(ctx, EXCP_RI);
4793 op1 = MASK_REGIMM(ctx->opcode);
4795 case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
4796 case OPC_BLTZAL ... OPC_BGEZALL:
4797 gen_compute_branch(ctx, op1, rs, -1, imm << 2);
4799 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
4801 gen_trap(ctx, op1, rs, -1, imm);
4806 default: /* Invalid */
4807 MIPS_INVAL("REGIMM");
4808 generate_exception(ctx, EXCP_RI);
4813 op1 = MASK_CP0(ctx->opcode);
4817 #ifdef MIPS_HAS_MIPS64
4821 gen_cp0(ctx, op1, rt, rd);
4823 case OPC_C0_FIRST ... OPC_C0_LAST:
4824 gen_cp0(ctx, MASK_C0(ctx->opcode), rt, rd);
4827 op2 = MASK_MFMC0(ctx->opcode);
4831 /* Stop translation as we may have switched the execution mode */
4832 ctx->bstate = BS_STOP;
4836 /* Stop translation as we may have switched the execution mode */
4837 ctx->bstate = BS_STOP;
4839 default: /* Invalid */
4840 MIPS_INVAL("MFMC0");
4841 generate_exception(ctx, EXCP_RI);
4844 GEN_STORE_TN_REG(rt, T0);
4846 /* Shadow registers (not implemented). */
4850 generate_exception(ctx, EXCP_RI);
4854 case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */
4855 gen_arith_imm(ctx, op, rt, rs, imm);
4857 case OPC_J ... OPC_JAL: /* Jump */
4858 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
4859 gen_compute_branch(ctx, op, rs, rt, offset);
4861 case OPC_BEQ ... OPC_BGTZ: /* Branch */
4862 case OPC_BEQL ... OPC_BGTZL:
4863 gen_compute_branch(ctx, op, rs, rt, imm << 2);
4865 case OPC_LB ... OPC_LWR: /* Load and stores */
4866 case OPC_SB ... OPC_SW:
4870 gen_ldst(ctx, op, rt, rs, imm);
4873 /* Treat as a noop */
4876 /* Treat as a noop */
4879 /* Floating point. */
4884 #if defined(MIPS_USES_FPU)
4885 save_cpu_state(ctx, 1);
4886 gen_op_cp1_enabled();
4887 gen_flt_ldst(ctx, op, rt, rs, imm);
4889 generate_exception_err(ctx, EXCP_CpU, 1);
4894 #if defined(MIPS_USES_FPU)
4895 save_cpu_state(ctx, 1);
4896 gen_op_cp1_enabled();
4897 op1 = MASK_CP1(ctx->opcode);
4903 #ifdef MIPS_HAS_MIPS64
4907 gen_cp1(ctx, op1, rt, rd);
4910 gen_compute_branch1(ctx, MASK_CP1_BCOND(ctx->opcode), imm << 2);
4916 gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
4919 generate_exception_err(ctx, EXCP_RI, 1);
4923 generate_exception_err(ctx, EXCP_CpU, 1);
4933 /* COP2: Not implemented. */
4934 generate_exception_err(ctx, EXCP_CpU, 2);
4937 #ifdef MIPS_USES_FPU
4939 gen_op_cp1_enabled();
4940 op1 = MASK_CP3(ctx->opcode);
4942 /* Not implemented */
4944 generate_exception_err(ctx, EXCP_RI, 1);
4950 #ifdef MIPS_HAS_MIPS64
4951 /* MIPS64 opcodes */
4953 case OPC_LDL ... OPC_LDR:
4954 case OPC_SDL ... OPC_SDR:
4959 gen_ldst(ctx, op, rt, rs, imm);
4961 case OPC_DADDI ... OPC_DADDIU:
4962 gen_arith_imm(ctx, op, rt, rs, imm);
4965 #ifdef MIPS_HAS_MIPS16
4967 /* MIPS16: Not implemented. */
4969 #ifdef MIPS_HAS_MDMX
4971 /* MDMX: Not implemented. */
4973 default: /* Invalid */
4975 generate_exception(ctx, EXCP_RI);
4978 if (ctx->hflags & MIPS_HFLAG_BMASK) {
4979 int hflags = ctx->hflags;
4980 /* Branches completion */
4981 ctx->hflags &= ~MIPS_HFLAG_BMASK;
4982 ctx->bstate = BS_BRANCH;
4983 save_cpu_state(ctx, 0);
4984 switch (hflags & MIPS_HFLAG_BMASK) {
4986 /* unconditional branch */
4987 MIPS_DEBUG("unconditional branch");
4988 gen_goto_tb(ctx, 0, ctx->btarget);
4991 /* blikely taken case */
4992 MIPS_DEBUG("blikely branch taken");
4993 gen_goto_tb(ctx, 0, ctx->btarget);
4996 /* Conditional branch */
4997 MIPS_DEBUG("conditional branch");
5000 l1 = gen_new_label();
5002 gen_goto_tb(ctx, 1, ctx->pc + 4);
5004 gen_goto_tb(ctx, 0, ctx->btarget);
5008 /* unconditional branch to register */
5009 MIPS_DEBUG("branch to register");
5013 MIPS_DEBUG("unknown branch");
5019 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
5022 DisasContext ctx, *ctxp = &ctx;
5023 target_ulong pc_start;
5024 uint16_t *gen_opc_end;
5027 if (search_pc && loglevel)
5028 fprintf (logfile, "search pc %d\n", search_pc);
5031 gen_opc_ptr = gen_opc_buf;
5032 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
5033 gen_opparam_ptr = gen_opparam_buf;
5038 ctx.bstate = BS_NONE;
5039 /* Restore delay slot state from the tb context. */
5040 ctx.hflags = tb->flags;
5041 ctx.saved_hflags = ctx.hflags;
5042 if (ctx.hflags & MIPS_HFLAG_BR) {
5043 gen_op_restore_breg_target();
5044 } else if (ctx.hflags & MIPS_HFLAG_B) {
5045 ctx.btarget = env->btarget;
5046 } else if (ctx.hflags & MIPS_HFLAG_BMASK) {
5047 /* If we are in the delay slot of a conditional branch,
5048 * restore the branch condition from env->bcond to T2
5050 ctx.btarget = env->btarget;
5051 gen_op_restore_bcond();
5053 #if defined(CONFIG_USER_ONLY)
5056 ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
5058 ctx.CP0_Status = env->CP0_Status;
5060 if (loglevel & CPU_LOG_TB_CPU) {
5061 fprintf(logfile, "------------------------------------------------\n");
5062 /* FIXME: This may print out stale hflags from env... */
5063 cpu_dump_state(env, logfile, fprintf, 0);
5066 #if defined MIPS_DEBUG_DISAS
5067 if (loglevel & CPU_LOG_TB_IN_ASM)
5068 fprintf(logfile, "\ntb %p super %d cond %04x\n",
5069 tb, ctx.mem_idx, ctx.hflags);
5071 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
5072 if (env->nb_breakpoints > 0) {
5073 for(j = 0; j < env->nb_breakpoints; j++) {
5074 if (env->breakpoints[j] == ctx.pc) {
5075 save_cpu_state(ctxp, 1);
5076 ctx.bstate = BS_BRANCH;
5078 goto done_generating;
5084 j = gen_opc_ptr - gen_opc_buf;
5088 gen_opc_instr_start[lj++] = 0;
5090 gen_opc_pc[lj] = ctx.pc;
5091 gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
5092 gen_opc_instr_start[lj] = 1;
5094 ctx.opcode = ldl_code(ctx.pc);
5098 if (env->singlestep_enabled)
5101 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
5104 #if defined (MIPS_SINGLE_STEP)
5108 if (env->singlestep_enabled) {
5109 save_cpu_state(ctxp, ctx.bstate == BS_NONE);
5111 goto done_generating;
5113 else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
5114 save_cpu_state(ctxp, 0);
5115 gen_goto_tb(&ctx, 0, ctx.pc);
5118 /* Generate the return instruction */
5121 *gen_opc_ptr = INDEX_op_end;
5123 j = gen_opc_ptr - gen_opc_buf;
5126 gen_opc_instr_start[lj++] = 0;
5129 tb->size = ctx.pc - pc_start;
5132 #if defined MIPS_DEBUG_DISAS
5133 if (loglevel & CPU_LOG_TB_IN_ASM)
5134 fprintf(logfile, "\n");
5136 if (loglevel & CPU_LOG_TB_IN_ASM) {
5137 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
5138 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
5139 fprintf(logfile, "\n");
5141 if (loglevel & CPU_LOG_TB_OP) {
5142 fprintf(logfile, "OP:\n");
5143 dump_ops(gen_opc_buf, gen_opparam_buf);
5144 fprintf(logfile, "\n");
5146 if (loglevel & CPU_LOG_TB_CPU) {
5147 fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
5154 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
5156 return gen_intermediate_code_internal(env, tb, 0);
5159 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
5161 return gen_intermediate_code_internal(env, tb, 1);
5164 #ifdef MIPS_USES_FPU
5166 void fpu_dump_state(CPUState *env, FILE *f,
5167 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
5172 # define printfpr(fp) do { \
5173 fpu_fprintf(f, "w:%08x d:%08lx%08lx fd:%g fs:%g\n", \
5174 (fp)->w[FP_ENDIAN_IDX], (fp)->w[0], (fp)->w[1], (fp)->fd, (fp)->fs[FP_ENDIAN_IDX]); \
5177 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d\n",
5178 env->fcr0, env->fcr31,
5179 (env->CP0_Status & (1 << CP0St_FR)) != 0);
5180 fpu_fprintf(f, "FT0: "); printfpr(&env->ft0);
5181 fpu_fprintf(f, "FT1: "); printfpr(&env->ft1);
5182 fpu_fprintf(f, "FT2: "); printfpr(&env->ft2);
5183 for(i = 0; i < 32; i += 2) {
5184 fpu_fprintf(f, "%s: ", fregnames[i]);
5185 printfpr(FPR(env, i));
5191 void dump_fpu (CPUState *env)
5194 fprintf(logfile, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
5195 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
5196 fpu_dump_state(env, logfile, fprintf, 0);
5200 #endif /* MIPS_USES_FPU */
5202 #if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
5203 /* Debug help: The architecture requires 32bit code to maintain proper
5204 sign-extened values on 64bit machines. */
5206 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
5208 void cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
5209 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5214 if (!SIGN_EXT_P(env->PC))
5215 cpu_fprintf(f, "BROKEN: pc=0x" TLSZ "\n", env->PC);
5216 if (!SIGN_EXT_P(env->HI))
5217 cpu_fprintf(f, "BROKEN: HI=0x" TLSZ "\n", env->HI);
5218 if (!SIGN_EXT_P(env->LO))
5219 cpu_fprintf(f, "BROKEN: LO=0x" TLSZ "\n", env->LO);
5220 if (!SIGN_EXT_P(env->btarget))
5221 cpu_fprintf(f, "BROKEN: btarget=0x" TLSZ "\n", env->btarget);
5223 for (i = 0; i < 32; i++) {
5224 if (!SIGN_EXT_P(env->gpr[i]))
5225 cpu_fprintf(f, "BROKEN: %s=0x" TLSZ "\n", regnames[i], env->gpr[i]);
5228 if (!SIGN_EXT_P(env->CP0_EPC))
5229 cpu_fprintf(f, "BROKEN: EPC=0x" TLSZ "\n", env->CP0_EPC);
5230 if (!SIGN_EXT_P(env->CP0_LLAddr))
5231 cpu_fprintf(f, "BROKEN: LLAddr=0x" TLSZ "\n", env->CP0_LLAddr);
5235 void cpu_dump_state (CPUState *env, FILE *f,
5236 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
5242 cpu_fprintf(f, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
5243 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
5244 for (i = 0; i < 32; i++) {
5246 cpu_fprintf(f, "GPR%02d:", i);
5247 cpu_fprintf(f, " %s " TLSZ, regnames[i], env->gpr[i]);
5249 cpu_fprintf(f, "\n");
5252 c0_status = env->CP0_Status;
5253 if (env->hflags & MIPS_HFLAG_UM)
5254 c0_status |= (1 << CP0St_UM);
5255 if (env->hflags & MIPS_HFLAG_ERL)
5256 c0_status |= (1 << CP0St_ERL);
5257 if (env->hflags & MIPS_HFLAG_EXL)
5258 c0_status |= (1 << CP0St_EXL);
5260 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TLSZ "\n",
5261 c0_status, env->CP0_Cause, env->CP0_EPC);
5262 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TLSZ "\n",
5263 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
5264 #ifdef MIPS_USES_FPU
5265 if (c0_status & (1 << CP0St_CU1))
5266 fpu_dump_state(env, f, cpu_fprintf, flags);
5268 #if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
5269 cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
5273 CPUMIPSState *cpu_mips_init (void)
5277 env = qemu_mallocz(sizeof(CPUMIPSState));
5285 void cpu_reset (CPUMIPSState *env)
5287 memset(env, 0, offsetof(CPUMIPSState, breakpoints));
5292 #if !defined(CONFIG_USER_ONLY)
5293 if (env->hflags & MIPS_HFLAG_BMASK) {
5294 /* If the exception was raised from a delay slot,
5295 * come back to the jump. */
5296 env->CP0_ErrorEPC = env->PC - 4;
5297 env->hflags &= ~MIPS_HFLAG_BMASK;
5299 env->CP0_ErrorEPC = env->PC;
5301 env->PC = (int32_t)0xBFC00000;
5302 #if defined (MIPS_USES_R4K_TLB)
5303 env->CP0_Random = MIPS_TLB_NB - 1;
5304 env->tlb_in_use = MIPS_TLB_NB;
5307 /* SMP not implemented */
5308 env->CP0_EBase = 0x80000000;
5309 env->CP0_Config0 = MIPS_CONFIG0;
5310 env->CP0_Config1 = MIPS_CONFIG1;
5311 env->CP0_Config2 = MIPS_CONFIG2;
5312 env->CP0_Config3 = MIPS_CONFIG3;
5313 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
5314 env->CP0_WatchLo = 0;
5315 env->hflags = MIPS_HFLAG_ERL;
5316 /* Count register increments in debug mode, EJTAG version 1 */
5317 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
5318 env->CP0_PRid = MIPS_CPU;
5320 env->exception_index = EXCP_NONE;
5321 #if defined(CONFIG_USER_ONLY)
5322 env->hflags |= MIPS_HFLAG_UM;
5323 env->user_mode_only = 1;
5325 #ifdef MIPS_USES_FPU
5326 env->fcr0 = MIPS_FCR0;
5328 /* XXX some guesswork here, values are CPU specific */
5329 env->SYNCI_Step = 16;