2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #define MIPS_DEBUG_DISAS
32 //#define MIPS_SINGLE_STEP
34 #ifdef USE_DIRECT_JUMP
37 #define TBPARAM(x) (long)(x)
41 #define DEF(s, n, copy_size) INDEX_op_ ## s,
47 static uint16_t *gen_opc_ptr;
48 static uint32_t *gen_opparam_ptr;
53 #define EXT_SPECIAL 0x100
54 #define EXT_SPECIAL2 0x200
55 #define EXT_REGIMM 0x300
62 /* indirect opcode tables */
70 /* arithmetic with immediate */
79 /* Jump and branches */
82 OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
90 OPC_JALX = 0x1D, /* MIPS 16 only */
106 /* Floating point load/store */
115 /* Cache and prefetch */
120 /* MIPS special opcodes */
123 OPC_SLL = 0x00 | EXT_SPECIAL,
124 /* NOP is SLL r0, r0, 0 */
125 /* SSNOP is SLL r0, r0, 1 */
126 OPC_SRL = 0x02 | EXT_SPECIAL,
127 OPC_SRA = 0x03 | EXT_SPECIAL,
128 OPC_SLLV = 0x04 | EXT_SPECIAL,
129 OPC_SRLV = 0x06 | EXT_SPECIAL,
130 OPC_SRAV = 0x07 | EXT_SPECIAL,
131 /* Multiplication / division */
132 OPC_MULT = 0x18 | EXT_SPECIAL,
133 OPC_MULTU = 0x19 | EXT_SPECIAL,
134 OPC_DIV = 0x1A | EXT_SPECIAL,
135 OPC_DIVU = 0x1B | EXT_SPECIAL,
136 /* 2 registers arithmetic / logic */
137 OPC_ADD = 0x20 | EXT_SPECIAL,
138 OPC_ADDU = 0x21 | EXT_SPECIAL,
139 OPC_SUB = 0x22 | EXT_SPECIAL,
140 OPC_SUBU = 0x23 | EXT_SPECIAL,
141 OPC_AND = 0x24 | EXT_SPECIAL,
142 OPC_OR = 0x25 | EXT_SPECIAL,
143 OPC_XOR = 0x26 | EXT_SPECIAL,
144 OPC_NOR = 0x27 | EXT_SPECIAL,
145 OPC_SLT = 0x2A | EXT_SPECIAL,
146 OPC_SLTU = 0x2B | EXT_SPECIAL,
148 OPC_JR = 0x08 | EXT_SPECIAL,
149 OPC_JALR = 0x09 | EXT_SPECIAL,
151 OPC_TGE = 0x30 | EXT_SPECIAL,
152 OPC_TGEU = 0x31 | EXT_SPECIAL,
153 OPC_TLT = 0x32 | EXT_SPECIAL,
154 OPC_TLTU = 0x33 | EXT_SPECIAL,
155 OPC_TEQ = 0x34 | EXT_SPECIAL,
156 OPC_TNE = 0x36 | EXT_SPECIAL,
157 /* HI / LO registers load & stores */
158 OPC_MFHI = 0x10 | EXT_SPECIAL,
159 OPC_MTHI = 0x11 | EXT_SPECIAL,
160 OPC_MFLO = 0x12 | EXT_SPECIAL,
161 OPC_MTLO = 0x13 | EXT_SPECIAL,
162 /* Conditional moves */
163 OPC_MOVZ = 0x0A | EXT_SPECIAL,
164 OPC_MOVN = 0x0B | EXT_SPECIAL,
166 OPC_MOVCI = 0x01 | EXT_SPECIAL,
169 OPC_PMON = 0x05 | EXT_SPECIAL,
170 OPC_SYSCALL = 0x0C | EXT_SPECIAL,
171 OPC_BREAK = 0x0D | EXT_SPECIAL,
172 OPC_SYNC = 0x0F | EXT_SPECIAL,
176 /* Mutiply & xxx operations */
177 OPC_MADD = 0x00 | EXT_SPECIAL2,
178 OPC_MADDU = 0x01 | EXT_SPECIAL2,
179 OPC_MUL = 0x02 | EXT_SPECIAL2,
180 OPC_MSUB = 0x04 | EXT_SPECIAL2,
181 OPC_MSUBU = 0x05 | EXT_SPECIAL2,
183 OPC_CLZ = 0x20 | EXT_SPECIAL2,
184 OPC_CLO = 0x21 | EXT_SPECIAL2,
186 OPC_SDBBP = 0x3F | EXT_SPECIAL2,
191 OPC_BLTZ = 0x00 | EXT_REGIMM,
192 OPC_BLTZL = 0x02 | EXT_REGIMM,
193 OPC_BGEZ = 0x01 | EXT_REGIMM,
194 OPC_BGEZL = 0x03 | EXT_REGIMM,
195 OPC_BLTZAL = 0x10 | EXT_REGIMM,
196 OPC_BLTZALL = 0x12 | EXT_REGIMM,
197 OPC_BGEZAL = 0x11 | EXT_REGIMM,
198 OPC_BGEZALL = 0x13 | EXT_REGIMM,
199 OPC_TGEI = 0x08 | EXT_REGIMM,
200 OPC_TGEIU = 0x09 | EXT_REGIMM,
201 OPC_TLTI = 0x0A | EXT_REGIMM,
202 OPC_TLTIU = 0x0B | EXT_REGIMM,
203 OPC_TEQI = 0x0C | EXT_REGIMM,
204 OPC_TNEI = 0x0E | EXT_REGIMM,
208 /* Coprocessor 0 (MMU) */
209 OPC_MFC0 = 0x00 | EXT_CP0,
210 OPC_MTC0 = 0x04 | EXT_CP0,
211 OPC_TLBR = 0x01 | EXT_CP0,
212 OPC_TLBWI = 0x02 | EXT_CP0,
213 OPC_TLBWR = 0x06 | EXT_CP0,
214 OPC_TLBP = 0x08 | EXT_CP0,
215 OPC_ERET = 0x18 | EXT_CP0,
216 OPC_DERET = 0x1F | EXT_CP0,
217 OPC_WAIT = 0x20 | EXT_CP0,
220 const unsigned char *regnames[] =
221 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
222 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
223 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
224 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
226 /* Warning: no function for r0 register (hard wired to zero) */
227 #define GEN32(func, NAME) \
228 static GenOpFunc *NAME ## _table [32] = { \
229 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
230 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
231 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
232 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
233 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
234 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
235 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
236 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
238 static inline void func(int n) \
240 NAME ## _table[n](); \
243 /* General purpose registers moves */
244 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
245 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
246 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
248 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
249 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
251 typedef struct DisasContext {
252 struct TranslationBlock *tb;
253 target_ulong pc, saved_pc;
255 /* Routine used to access memory */
257 uint32_t hflags, saved_hflags;
260 target_ulong btarget;
264 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
265 * exception condition
267 BS_STOP = 1, /* We want to stop translation for any reason */
268 BS_BRANCH = 2, /* We reached a branch condition */
269 BS_EXCP = 3, /* We reached an exception condition */
272 #if defined MIPS_DEBUG_DISAS
273 #define MIPS_DEBUG(fmt, args...) \
275 if (loglevel & CPU_LOG_TB_IN_ASM) { \
276 fprintf(logfile, "%08x: %08x " fmt "\n", \
277 ctx->pc, ctx->opcode , ##args); \
281 #define MIPS_DEBUG(fmt, args...) do { } while(0)
284 #define MIPS_INVAL(op) \
286 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
287 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
290 #define GEN_LOAD_REG_TN(Tn, Rn) \
293 glue(gen_op_reset_, Tn)(); \
295 glue(gen_op_load_gpr_, Tn)(Rn); \
299 #define GEN_LOAD_IMM_TN(Tn, Imm) \
302 glue(gen_op_reset_, Tn)(); \
304 glue(gen_op_set_, Tn)(Imm); \
308 #define GEN_STORE_TN_REG(Rn, Tn) \
311 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
315 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
317 #if defined MIPS_DEBUG_DISAS
318 if (loglevel & CPU_LOG_TB_IN_ASM) {
319 fprintf(logfile, "hflags %08x saved %08x\n",
320 ctx->hflags, ctx->saved_hflags);
323 if (do_save_pc && ctx->pc != ctx->saved_pc) {
324 gen_op_save_pc(ctx->pc);
325 ctx->saved_pc = ctx->pc;
327 if (ctx->hflags != ctx->saved_hflags) {
328 gen_op_save_state(ctx->hflags);
329 ctx->saved_hflags = ctx->hflags;
330 if (ctx->hflags & MIPS_HFLAG_BR) {
331 gen_op_save_breg_target();
332 } else if (ctx->hflags & MIPS_HFLAG_B) {
333 gen_op_save_btarget(ctx->btarget);
334 } else if (ctx->hflags & MIPS_HFLAG_BMASK) {
336 gen_op_save_btarget(ctx->btarget);
341 static inline void generate_exception (DisasContext *ctx, int excp)
343 #if defined MIPS_DEBUG_DISAS
344 if (loglevel & CPU_LOG_TB_IN_ASM)
345 fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
347 save_cpu_state(ctx, 1);
348 gen_op_raise_exception(excp);
349 ctx->bstate = BS_EXCP;
352 #if defined(CONFIG_USER_ONLY)
353 #define op_ldst(name) gen_op_##name##_raw()
354 #define OP_LD_TABLE(width)
355 #define OP_ST_TABLE(width)
357 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
358 #define OP_LD_TABLE(width) \
359 static GenOpFunc *gen_op_l##width[] = { \
360 &gen_op_l##width##_user, \
361 &gen_op_l##width##_kernel, \
363 #define OP_ST_TABLE(width) \
364 static GenOpFunc *gen_op_s##width[] = { \
365 &gen_op_s##width##_user, \
366 &gen_op_s##width##_kernel, \
394 static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt,
395 int base, int16_t offset)
397 const unsigned char *opn = "unk";
400 GEN_LOAD_IMM_TN(T0, offset);
401 } else if (offset == 0) {
402 gen_op_load_gpr_T0(base);
404 gen_op_load_gpr_T0(base);
405 gen_op_set_T1(offset);
408 /* Don't do NOP if destination is zero: we must perform the actual
412 #if defined(TARGET_MIPS64)
414 #if defined (MIPS_HAS_UNALIGNED_LS)
418 GEN_STORE_TN_REG(rt, T0);
422 #if defined (MIPS_HAS_UNALIGNED_LS)
425 GEN_LOAD_REG_TN(T1, rt);
431 GEN_STORE_TN_REG(rt, T0);
435 GEN_LOAD_REG_TN(T1, rt);
441 GEN_STORE_TN_REG(rt, T0);
445 GEN_LOAD_REG_TN(T1, rt);
451 #if defined (MIPS_HAS_UNALIGNED_LS)
455 GEN_STORE_TN_REG(rt, T0);
459 #if defined (MIPS_HAS_UNALIGNED_LS)
462 GEN_LOAD_REG_TN(T1, rt);
467 #if defined (MIPS_HAS_UNALIGNED_LS)
471 GEN_STORE_TN_REG(rt, T0);
475 #if defined (MIPS_HAS_UNALIGNED_LS)
478 GEN_LOAD_REG_TN(T1, rt);
483 #if defined (MIPS_HAS_UNALIGNED_LS)
487 GEN_STORE_TN_REG(rt, T0);
492 GEN_STORE_TN_REG(rt, T0);
496 GEN_LOAD_REG_TN(T1, rt);
502 GEN_STORE_TN_REG(rt, T0);
506 GEN_LOAD_REG_TN(T1, rt);
508 GEN_STORE_TN_REG(rt, T0);
512 GEN_LOAD_REG_TN(T1, rt);
517 GEN_LOAD_REG_TN(T1, rt);
519 GEN_STORE_TN_REG(rt, T0);
523 GEN_LOAD_REG_TN(T1, rt);
529 GEN_STORE_TN_REG(rt, T0);
533 GEN_LOAD_REG_TN(T1, rt);
535 GEN_STORE_TN_REG(rt, T0);
539 MIPS_INVAL("load/store");
540 generate_exception(ctx, EXCP_RI);
543 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
546 /* Arithmetic with immediate operand */
547 static void gen_arith_imm (DisasContext *ctx, uint16_t opc, int rt,
551 const unsigned char *opn = "unk";
553 if (rt == 0 && opc != OPC_ADDI) {
554 /* if no destination, treat it as a NOP
555 * For addi, we must generate the overflow exception when needed.
560 if (opc == OPC_ADDI || opc == OPC_ADDIU ||
561 opc == OPC_SLTI || opc == OPC_SLTIU)
562 uimm = (int32_t)imm; /* Sign extent to 32 bits */
564 uimm = (uint16_t)imm;
565 if (opc != OPC_LUI) {
566 GEN_LOAD_REG_TN(T0, rs);
567 GEN_LOAD_IMM_TN(T1, uimm);
570 GEN_LOAD_IMM_TN(T0, uimm);
574 save_cpu_state(ctx, 1);
618 MIPS_INVAL("imm arith");
619 generate_exception(ctx, EXCP_RI);
622 GEN_STORE_TN_REG(rt, T0);
623 MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
627 static void gen_arith (DisasContext *ctx, uint16_t opc,
628 int rd, int rs, int rt)
630 const unsigned char *opn = "unk";
632 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB) {
633 /* if no destination, treat it as a NOP
634 * For add & sub, we must generate the overflow exception when needed.
639 GEN_LOAD_REG_TN(T0, rs);
640 GEN_LOAD_REG_TN(T1, rt);
643 save_cpu_state(ctx, 1);
652 save_cpu_state(ctx, 1);
710 generate_exception(ctx, EXCP_RI);
713 GEN_STORE_TN_REG(rd, T0);
715 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
718 /* Arithmetic on HI/LO registers */
719 static void gen_HILO (DisasContext *ctx, uint16_t opc, int reg)
721 const unsigned char *opn = "unk";
723 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
731 GEN_STORE_TN_REG(reg, T0);
736 GEN_STORE_TN_REG(reg, T0);
740 GEN_LOAD_REG_TN(T0, reg);
745 GEN_LOAD_REG_TN(T0, reg);
751 generate_exception(ctx, EXCP_RI);
754 MIPS_DEBUG("%s %s", opn, regnames[reg]);
757 static void gen_muldiv (DisasContext *ctx, uint16_t opc,
760 const unsigned char *opn = "unk";
762 GEN_LOAD_REG_TN(T0, rs);
763 GEN_LOAD_REG_TN(T1, rt);
798 MIPS_INVAL("mul/div");
799 generate_exception(ctx, EXCP_RI);
802 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
805 static void gen_cl (DisasContext *ctx, uint16_t opc,
808 const unsigned char *opn = "unk";
814 GEN_LOAD_REG_TN(T0, rs);
828 generate_exception(ctx, EXCP_RI);
831 gen_op_store_T0_gpr(rd);
832 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
836 static void gen_trap (DisasContext *ctx, uint16_t opc,
837 int rs, int rt, int16_t imm)
842 /* Load needed operands */
850 /* Compare two registers */
852 GEN_LOAD_REG_TN(T0, rs);
853 GEN_LOAD_REG_TN(T1, rt);
862 /* Compare register to immediate */
863 if (rs != 0 || imm != 0) {
864 GEN_LOAD_REG_TN(T0, rs);
865 GEN_LOAD_IMM_TN(T1, (int32_t)imm);
872 case OPC_TEQ: /* rs == rs */
873 case OPC_TEQI: /* r0 == 0 */
874 case OPC_TGE: /* rs >= rs */
875 case OPC_TGEI: /* r0 >= 0 */
876 case OPC_TGEU: /* rs >= rs unsigned */
877 case OPC_TGEIU: /* r0 >= 0 unsigned */
881 case OPC_TLT: /* rs < rs */
882 case OPC_TLTI: /* r0 < 0 */
883 case OPC_TLTU: /* rs < rs unsigned */
884 case OPC_TLTIU: /* r0 < 0 unsigned */
885 case OPC_TNE: /* rs != rs */
886 case OPC_TNEI: /* r0 != 0 */
887 /* Never trap: treat as NOP */
891 generate_exception(ctx, EXCP_RI);
922 generate_exception(ctx, EXCP_RI);
926 save_cpu_state(ctx, 1);
928 ctx->bstate = BS_STOP;
931 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
933 TranslationBlock *tb;
935 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
937 gen_op_goto_tb0(TBPARAM(tb));
939 gen_op_goto_tb1(TBPARAM(tb));
940 gen_op_save_pc(dest);
941 gen_op_set_T0((long)tb + n);
944 gen_op_save_pc(dest);
950 /* Branches (before delay slot) */
951 static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
952 int rs, int rt, int32_t offset)
954 target_ulong btarget;
960 /* Load needed operands */
966 /* Compare two registers */
968 GEN_LOAD_REG_TN(T0, rs);
969 GEN_LOAD_REG_TN(T1, rt);
972 btarget = ctx->pc + 4 + offset;
986 /* Compare to zero */
988 gen_op_load_gpr_T0(rs);
991 btarget = ctx->pc + 4 + offset;
995 /* Jump to immediate */
996 btarget = ((ctx->pc + 4) & 0xF0000000) | offset;
1000 /* Jump to register */
1002 /* Only hint = 0 is valid */
1003 generate_exception(ctx, EXCP_RI);
1006 GEN_LOAD_REG_TN(T2, rs);
1009 MIPS_INVAL("branch/jump");
1010 generate_exception(ctx, EXCP_RI);
1014 /* No condition to be computed */
1016 case OPC_BEQ: /* rx == rx */
1017 case OPC_BEQL: /* rx == rx likely */
1018 case OPC_BGEZ: /* 0 >= 0 */
1019 case OPC_BGEZL: /* 0 >= 0 likely */
1020 case OPC_BLEZ: /* 0 <= 0 */
1021 case OPC_BLEZL: /* 0 <= 0 likely */
1023 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
1024 MIPS_DEBUG("balways");
1026 case OPC_BGEZAL: /* 0 >= 0 */
1027 case OPC_BGEZALL: /* 0 >= 0 likely */
1028 /* Always take and link */
1030 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
1031 MIPS_DEBUG("balways and link");
1033 case OPC_BNE: /* rx != rx */
1034 case OPC_BGTZ: /* 0 > 0 */
1035 case OPC_BLTZ: /* 0 < 0 */
1036 case OPC_BLTZAL: /* 0 < 0 */
1037 /* Treated as NOP */
1038 MIPS_DEBUG("bnever (NOP)");
1040 case OPC_BNEL: /* rx != rx likely */
1041 case OPC_BGTZL: /* 0 > 0 likely */
1042 case OPC_BLTZALL: /* 0 < 0 likely */
1043 case OPC_BLTZL: /* 0 < 0 likely */
1044 /* Skip the instruction in the delay slot */
1045 MIPS_DEBUG("bnever and skip");
1046 gen_goto_tb(ctx, 0, ctx->pc + 4);
1049 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
1050 MIPS_DEBUG("j %08x", btarget);
1054 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
1055 MIPS_DEBUG("jal %08x", btarget);
1058 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
1059 MIPS_DEBUG("jr %s", regnames[rs]);
1063 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
1064 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
1067 MIPS_INVAL("branch/jump");
1068 generate_exception(ctx, EXCP_RI);
1075 MIPS_DEBUG("beq %s, %s, %08x",
1076 regnames[rs], regnames[rt], btarget);
1080 MIPS_DEBUG("beql %s, %s, %08x",
1081 regnames[rs], regnames[rt], btarget);
1085 MIPS_DEBUG("bne %s, %s, %08x",
1086 regnames[rs], regnames[rt], btarget);
1090 MIPS_DEBUG("bnel %s, %s, %08x",
1091 regnames[rs], regnames[rt], btarget);
1095 MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
1099 MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
1103 MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
1109 MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
1113 MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
1117 MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
1121 MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
1125 MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
1129 MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
1133 MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
1138 MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
1140 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC;
1145 MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
1147 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL;
1152 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
1153 blink, ctx->hflags, btarget);
1154 ctx->btarget = btarget;
1156 gen_op_set_T0(ctx->pc + 8);
1157 gen_op_store_T0_gpr(blink);
1162 /* CP0 (MMU and control) */
1163 static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd)
1165 const unsigned char *opn = "unk";
1167 if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
1168 !(ctx->hflags & MIPS_HFLAG_UM) &&
1169 !(ctx->hflags & MIPS_HFLAG_ERL) &&
1170 !(ctx->hflags & MIPS_HFLAG_EXL)) {
1171 if (loglevel & CPU_LOG_TB_IN_ASM) {
1172 fprintf(logfile, "CP0 is not usable\n");
1174 gen_op_raise_exception_err(EXCP_CpU, 0);
1183 gen_op_mfc0(rd, ctx->opcode & 0x7);
1184 gen_op_store_T0_gpr(rt);
1188 /* If we get an exception, we want to restart at next instruction */
1190 save_cpu_state(ctx, 1);
1192 GEN_LOAD_REG_TN(T0, rt);
1193 gen_op_mtc0(rd, ctx->opcode & 0x7);
1194 /* Stop translation as we may have switched the execution mode */
1195 ctx->bstate = BS_STOP;
1198 #if defined(MIPS_USES_R4K_TLB)
1218 save_cpu_state(ctx, 0);
1220 ctx->bstate = BS_EXCP;
1224 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
1225 generate_exception(ctx, EXCP_RI);
1227 save_cpu_state(ctx, 0);
1229 ctx->bstate = BS_EXCP;
1232 /* XXX: TODO: WAIT */
1234 if (loglevel & CPU_LOG_TB_IN_ASM) {
1235 fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
1236 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
1237 ((ctx->opcode >> 16) & 0x1F));
1239 generate_exception(ctx, EXCP_RI);
1242 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
1245 /* Coprocessor 1 (FPU) */
1247 /* ISA extensions */
1248 /* MIPS16 extension to MIPS32 */
1249 /* SmartMIPS extension to MIPS32 */
1251 #ifdef TARGET_MIPS64
1252 static void gen_arith64 (DisasContext *ctx, uint16_t opc)
1254 if (func == 0x02 && rd == 0) {
1258 if (rs == 0 || rt == 0) {
1262 gen_op_load_gpr_T0(rs);
1263 gen_op_load_gpr_T1(rt);
1276 /* Coprocessor 3 (FPU) */
1278 /* MDMX extension to MIPS64 */
1279 /* MIPS-3D extension to MIPS64 */
1283 static void gen_blikely(DisasContext *ctx)
1286 l1 = gen_new_label();
1288 gen_op_save_state(ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS));
1289 gen_goto_tb(ctx, 1, ctx->pc + 4);
1292 static void decode_opc (DisasContext *ctx)
1299 if ((ctx->hflags & MIPS_HFLAG_DS) &&
1300 (ctx->hflags & MIPS_HFLAG_BL)) {
1301 /* Handle blikely not taken case */
1302 MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
1305 op = ctx->opcode >> 26;
1306 rs = ((ctx->opcode >> 21) & 0x1F);
1307 rt = ((ctx->opcode >> 16) & 0x1F);
1308 rd = ((ctx->opcode >> 11) & 0x1F);
1309 sa = ((ctx->opcode >> 6) & 0x1F);
1310 imm = (int16_t)ctx->opcode;
1312 case 0x00: /* Special opcode */
1313 op1 = ctx->opcode & 0x3F;
1315 case 0x00: /* Arithmetic with immediate */
1317 gen_arith_imm(ctx, op1 | EXT_SPECIAL, rd, rt, sa);
1319 case 0x04: /* Arithmetic */
1324 gen_arith(ctx, op1 | EXT_SPECIAL, rd, rs, rt);
1326 case 0x18 ... 0x1B: /* MULT / DIV */
1327 gen_muldiv(ctx, op1 | EXT_SPECIAL, rs, rt);
1329 case 0x08 ... 0x09: /* Jumps */
1330 gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);
1332 case 0x30 ... 0x34: /* Traps */
1334 gen_trap(ctx, op1 | EXT_SPECIAL, rs, rt, -1);
1336 case 0x10: /* Move from HI/LO */
1338 gen_HILO(ctx, op1 | EXT_SPECIAL, rd);
1341 case 0x13: /* Move to HI/LO */
1342 gen_HILO(ctx, op1 | EXT_SPECIAL, rs);
1344 case 0x0C: /* SYSCALL */
1345 generate_exception(ctx, EXCP_SYSCALL);
1347 case 0x0D: /* BREAK */
1348 generate_exception(ctx, EXCP_BREAK);
1350 case 0x0F: /* SYNC */
1351 /* Treat as a noop */
1353 case 0x05: /* Pmon entry point */
1354 gen_op_pmon((ctx->opcode >> 6) & 0x1F);
1356 #if defined (MIPS_HAS_MOVCI)
1357 case 0x01: /* MOVCI */
1359 #if defined (TARGET_MIPS64)
1360 case 0x14: /* MIPS64 specific opcodes */
1369 default: /* Invalid */
1370 MIPS_INVAL("special");
1371 generate_exception(ctx, EXCP_RI);
1375 case 0x1C: /* Special2 opcode */
1376 op1 = ctx->opcode & 0x3F;
1378 #if defined (MIPS_USES_R4K_EXT)
1379 /* Those instructions are not part of MIPS32 core */
1380 case 0x00 ... 0x01: /* Multiply and add/sub */
1382 gen_muldiv(ctx, op1 | EXT_SPECIAL2, rs, rt);
1384 case 0x02: /* MUL */
1385 gen_arith(ctx, op1 | EXT_SPECIAL2, rd, rs, rt);
1387 case 0x20 ... 0x21: /* CLO / CLZ */
1388 gen_cl(ctx, op1 | EXT_SPECIAL2, rd, rs);
1391 case 0x3F: /* SDBBP */
1392 /* XXX: not clear which exception should be raised
1393 * when in debug mode...
1395 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
1396 generate_exception(ctx, EXCP_DBp);
1398 generate_exception(ctx, EXCP_DBp);
1400 /* Treat as a noop */
1402 default: /* Invalid */
1403 MIPS_INVAL("special2");
1404 generate_exception(ctx, EXCP_RI);
1408 case 0x01: /* B REGIMM opcode */
1409 op1 = ((ctx->opcode >> 16) & 0x1F);
1411 case 0x00 ... 0x03: /* REGIMM branches */
1413 gen_compute_branch(ctx, op1 | EXT_REGIMM, rs, -1, imm << 2);
1415 case 0x08 ... 0x0C: /* Traps */
1417 gen_trap(ctx, op1 | EXT_REGIMM, rs, -1, imm);
1419 default: /* Invalid */
1420 MIPS_INVAL("REGIMM");
1421 generate_exception(ctx, EXCP_RI);
1425 case 0x10: /* CP0 opcode */
1426 op1 = ((ctx->opcode >> 21) & 0x1F);
1430 gen_cp0(ctx, op1 | EXT_CP0, rt, rd);
1433 gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd);
1437 case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */
1438 gen_arith_imm(ctx, op, rt, rs, imm);
1440 case 0x02 ... 0x03: /* Jump */
1441 offset = (int32_t)(ctx->opcode & 0x03FFFFFF) << 2;
1442 gen_compute_branch(ctx, op, rs, rt, offset);
1444 case 0x04 ... 0x07: /* Branch */
1446 gen_compute_branch(ctx, op, rs, rt, imm << 2);
1448 case 0x20 ... 0x26: /* Load and stores */
1452 gen_ldst(ctx, op, rt, rs, imm);
1454 case 0x2F: /* Cache operation */
1455 /* Treat as a noop */
1457 case 0x33: /* Prefetch */
1458 /* Treat as a noop */
1460 case 0x3F: /* HACK */
1462 #if defined(MIPS_USES_FPU)
1463 case 0x31 ... 0x32: /* Floating point load/store */
1467 /* Not implemented */
1468 /* XXX: not correct */
1470 case 0x11: /* CP1 opcode */
1471 /* Not implemented */
1472 /* XXX: not correct */
1473 case 0x12: /* CP2 opcode */
1474 /* Not implemented */
1475 /* XXX: not correct */
1476 case 0x13: /* CP3 opcode */
1477 /* Not implemented */
1478 /* XXX: not correct */
1479 #if defined (TARGET_MIPS64)
1484 /* MIPS64 opcodes */
1486 #if defined (MIPS_HAS_JALX)
1488 /* JALX: not implemented */
1492 #if defined (MIPS_HAS_LSC)
1493 case 0x31: /* LWC1 */
1494 case 0x32: /* LWC2 */
1495 case 0x35: /* SDC1 */
1496 case 0x36: /* SDC2 */
1498 default: /* Invalid */
1500 generate_exception(ctx, EXCP_RI);
1503 if (ctx->hflags & MIPS_HFLAG_DS) {
1504 int hflags = ctx->hflags;
1505 /* Branches completion */
1506 ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS);
1507 ctx->bstate = BS_BRANCH;
1508 save_cpu_state(ctx, 0);
1509 switch (hflags & MIPS_HFLAG_BMASK) {
1511 /* unconditional branch */
1512 MIPS_DEBUG("unconditional branch");
1513 gen_goto_tb(ctx, 0, ctx->btarget);
1516 /* blikely taken case */
1517 MIPS_DEBUG("blikely branch taken");
1518 gen_goto_tb(ctx, 0, ctx->btarget);
1521 /* Conditional branch */
1522 MIPS_DEBUG("conditional branch");
1525 l1 = gen_new_label();
1527 gen_goto_tb(ctx, 0, ctx->btarget);
1529 gen_goto_tb(ctx, 1, ctx->pc + 4);
1533 /* unconditional branch to register */
1534 MIPS_DEBUG("branch to register");
1538 MIPS_DEBUG("unknown branch");
1544 int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
1547 DisasContext ctx, *ctxp = &ctx;
1548 target_ulong pc_start;
1549 uint16_t *gen_opc_end;
1553 gen_opc_ptr = gen_opc_buf;
1554 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1555 gen_opparam_ptr = gen_opparam_buf;
1559 ctx.bstate = BS_NONE;
1560 /* Restore delay slot state */
1561 ctx.hflags = env->hflags;
1562 ctx.saved_hflags = ctx.hflags;
1563 if (ctx.hflags & MIPS_HFLAG_BR) {
1564 gen_op_restore_breg_target();
1565 } else if (ctx.hflags & MIPS_HFLAG_B) {
1566 ctx.btarget = env->btarget;
1567 } else if (ctx.hflags & MIPS_HFLAG_BMASK) {
1568 /* If we are in the delay slot of a conditional branch,
1569 * restore the branch condition from env->bcond to T2
1571 ctx.btarget = env->btarget;
1572 gen_op_restore_bcond();
1574 #if defined(CONFIG_USER_ONLY)
1577 ctx.mem_idx = (ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 0 : 1;
1579 ctx.CP0_Status = env->CP0_Status;
1581 if (loglevel & CPU_LOG_TB_CPU) {
1582 fprintf(logfile, "------------------------------------------------\n");
1583 cpu_dump_state(env, logfile, fprintf, 0);
1586 #if defined MIPS_DEBUG_DISAS
1587 if (loglevel & CPU_LOG_TB_IN_ASM)
1588 fprintf(logfile, "\ntb %p super %d cond %04x %04x\n",
1589 tb, ctx.mem_idx, ctx.hflags, env->hflags);
1591 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1593 j = gen_opc_ptr - gen_opc_buf;
1594 save_cpu_state(ctxp, 1);
1598 gen_opc_instr_start[lj++] = 0;
1599 gen_opc_pc[lj] = ctx.pc;
1600 gen_opc_instr_start[lj] = 1;
1603 ctx.opcode = ldl_code(ctx.pc);
1606 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1608 #if defined (MIPS_SINGLE_STEP)
1612 if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
1613 save_cpu_state(ctxp, 0);
1614 gen_goto_tb(&ctx, 0, ctx.pc);
1617 /* Generate the return instruction */
1619 *gen_opc_ptr = INDEX_op_end;
1621 j = gen_opc_ptr - gen_opc_buf;
1624 gen_opc_instr_start[lj++] = 0;
1627 tb->size = ctx.pc - pc_start;
1630 #if defined MIPS_DEBUG_DISAS
1631 if (loglevel & CPU_LOG_TB_IN_ASM)
1632 fprintf(logfile, "\n");
1634 if (loglevel & CPU_LOG_TB_IN_ASM) {
1635 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1636 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1637 fprintf(logfile, "\n");
1639 if (loglevel & CPU_LOG_TB_OP) {
1640 fprintf(logfile, "OP:\n");
1641 dump_ops(gen_opc_buf, gen_opparam_buf);
1642 fprintf(logfile, "\n");
1644 if (loglevel & CPU_LOG_TB_CPU) {
1645 fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
1652 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1654 return gen_intermediate_code_internal(env, tb, 0);
1657 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1659 return gen_intermediate_code_internal(env, tb, 1);
1662 void cpu_dump_state (CPUState *env, FILE *f,
1663 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1669 cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
1670 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
1671 for (i = 0; i < 32; i++) {
1673 cpu_fprintf(f, "GPR%02d:", i);
1674 cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]);
1676 cpu_fprintf(f, "\n");
1679 c0_status = env->CP0_Status;
1680 if (env->hflags & MIPS_HFLAG_UM)
1681 c0_status |= (1 << CP0St_UM);
1682 if (env->hflags & MIPS_HFLAG_ERL)
1683 c0_status |= (1 << CP0St_ERL);
1684 if (env->hflags & MIPS_HFLAG_EXL)
1685 c0_status |= (1 << CP0St_EXL);
1687 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
1688 c0_status, env->CP0_Cause, env->CP0_EPC);
1689 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
1690 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
1693 CPUMIPSState *cpu_mips_init (void)
1697 env = qemu_mallocz(sizeof(CPUMIPSState));
1703 env->PC = 0xBFC00000;
1704 #if defined (MIPS_USES_R4K_TLB)
1705 env->CP0_random = MIPS_TLB_NB - 1;
1708 env->CP0_Config0 = MIPS_CONFIG0;
1709 #if defined (MIPS_CONFIG1)
1710 env->CP0_Config1 = MIPS_CONFIG1;
1712 #if defined (MIPS_CONFIG2)
1713 env->CP0_Config2 = MIPS_CONFIG2;
1715 #if defined (MIPS_CONFIG3)
1716 env->CP0_Config3 = MIPS_CONFIG3;
1718 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
1719 env->CP0_WatchLo = 0;
1720 env->hflags = MIPS_HFLAG_ERL;
1721 /* Count register increments in debug mode, EJTAG version 1 */
1722 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
1723 env->CP0_PRid = MIPS_CPU;
1724 env->exception_index = EXCP_NONE;