2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 /* MIPS32 4K MMU emulation */
32 #ifdef MIPS_USES_R4K_TLB
33 static int map_address (CPUState *env, target_ulong *physical, int *prot,
34 target_ulong address, int rw, int access_type)
43 tag = (address & 0xFFFFE000);
44 ASID = env->CP0_EntryHi & 0x000000FF;
45 for (i = 0; i < MIPS_TLB_NB; i++) {
47 /* Check ASID, virtual page number & size */
48 if ((tlb->G == 1 || tlb->ASID == ASID) &&
49 tlb->VPN == tag && address < tlb->end2) {
51 n = (address >> 12) & 1;
52 /* Check access rights */
53 if ((tlb->V[n] & 2) && (rw == 0 || (tlb->D[n] & 4))) {
54 *physical = tlb->PFN[n] | (address & 0xFFF);
59 } else if (!(tlb->V[n] & 2)) {
71 int get_physical_address (CPUState *env, target_ulong *physical, int *prot,
72 target_ulong address, int rw, int access_type)
77 /* User mode can only access useg */
78 user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;
81 fprintf(logfile, "user mode %d h %08x\n",
82 user_mode, env->hflags);
85 if (user_mode && address > 0x7FFFFFFFUL)
88 if (address < 0x80000000UL) {
89 if (!(env->hflags & MIPS_HFLAG_ERL)) {
90 #ifdef MIPS_USES_R4K_TLB
91 ret = map_address(env, physical, prot, address, rw, access_type);
93 *physical = address + 0x40000000UL;
94 *prot = PAGE_READ | PAGE_WRITE;
98 *prot = PAGE_READ | PAGE_WRITE;
100 } else if (address < 0xA0000000UL) {
102 /* XXX: check supervisor mode */
103 *physical = address - 0x80000000UL;
104 *prot = PAGE_READ | PAGE_WRITE;
105 } else if (address < 0xC0000000UL) {
107 /* XXX: check supervisor mode */
108 *physical = address - 0xA0000000UL;
109 *prot = PAGE_READ | PAGE_WRITE;
110 } else if (address < 0xE0000000UL) {
112 #ifdef MIPS_USES_R4K_TLB
113 ret = map_address(env, physical, prot, address, rw, access_type);
116 *prot = PAGE_READ | PAGE_WRITE;
120 /* XXX: check supervisor mode */
121 /* XXX: debug segment is not emulated */
122 #ifdef MIPS_USES_R4K_TLB
123 ret = map_address(env, physical, prot, address, rw, access_type);
126 *prot = PAGE_READ | PAGE_WRITE;
131 fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
132 access_type, *physical, *prot, ret);
139 #if defined(CONFIG_USER_ONLY)
140 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
145 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
147 target_ulong phys_addr;
150 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
155 void cpu_mips_init_mmu (CPUState *env)
158 #endif /* !defined(CONFIG_USER_ONLY) */
160 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
161 int is_user, int is_softmmu)
163 target_ulong physical;
165 int exception = 0, error_code = 0;
171 cpu_dump_state(env, logfile, fprintf, 0);
173 fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
174 __func__, env->PC, address, rw, is_user, is_softmmu);
180 /* XXX: put correct access by using cpu_restore_state()
182 access_type = ACCESS_INT;
183 if (env->user_mode_only) {
184 /* user mode only emulation */
188 ret = get_physical_address(env, &physical, &prot,
189 address, rw, access_type);
191 fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
192 __func__, address, ret, physical, prot);
195 ret = tlb_set_page(env, address & ~0xFFF, physical & ~0xFFF, prot,
196 is_user, is_softmmu);
197 } else if (ret < 0) {
202 /* Reference to kernel address from user mode or supervisor mode */
203 /* Reference to supervisor address from user mode */
205 exception = EXCP_AdES;
207 exception = EXCP_AdEL;
210 /* No TLB match for a mapped address */
212 exception = EXCP_TLBS;
214 exception = EXCP_TLBL;
218 /* TLB match with no valid bit */
220 exception = EXCP_TLBS;
222 exception = EXCP_TLBL;
226 /* TLB match but 'D' bit is cleared */
227 exception = EXCP_LTLBL;
231 /* Raise exception */
232 env->CP0_BadVAddr = address;
233 env->CP0_Context = (env->CP0_Context & 0xff800000) |
234 ((address >> 9) & 0x007ffff0);
236 (env->CP0_EntryHi & 0x000000FF) | (address & 0xFFFFF000);
237 env->exception_index = exception;
238 env->error_code = error_code;
245 void do_interrupt (CPUState *env)
247 target_ulong pc, offset;
250 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
251 fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
252 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
254 if (env->exception_index == EXCP_EXT_INTERRUPT &&
255 (env->hflags & MIPS_HFLAG_DM))
256 env->exception_index = EXCP_DINT;
258 switch (env->exception_index) {
260 env->CP0_Debug |= 1 << CP0DB_DSS;
261 /* Debug single step cannot be raised inside a delay slot and
262 * resume will always occur on the next instruction
263 * (but we assume the pc has always been updated during
266 env->CP0_DEPC = env->PC;
267 goto enter_debug_mode;
269 env->CP0_Debug |= 1 << CP0DB_DINT;
272 env->CP0_Debug |= 1 << CP0DB_DIB;
275 env->CP0_Debug |= 1 << CP0DB_DBp;
278 env->CP0_Debug |= 1 << CP0DB_DDBS;
281 env->CP0_Debug |= 1 << CP0DB_DDBL;
284 if (env->hflags & MIPS_HFLAG_BMASK) {
285 /* If the exception was raised from a delay slot,
286 * come back to the jump
288 env->CP0_DEPC = env->PC - 4;
289 env->hflags &= ~MIPS_HFLAG_BMASK;
291 env->CP0_DEPC = env->PC;
294 env->hflags |= MIPS_HFLAG_DM;
295 /* EJTAG probe trap enable is not implemented... */
299 #ifdef MIPS_USES_R4K_TLB
300 env->CP0_random = MIPS_TLB_NB - 1;
303 env->CP0_Config0 = MIPS_CONFIG0;
304 #if defined (MIPS_CONFIG1)
305 env->CP0_Config1 = MIPS_CONFIG1;
307 #if defined (MIPS_CONFIG2)
308 env->CP0_Config2 = MIPS_CONFIG2;
310 #if defined (MIPS_CONFIG3)
311 env->CP0_Config3 = MIPS_CONFIG3;
313 env->CP0_WatchLo = 0;
314 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
317 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
319 env->CP0_WatchLo = 0;
322 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) |
325 if (env->hflags & MIPS_HFLAG_BMASK) {
326 /* If the exception was raised from a delay slot,
327 * come back to the jump
329 env->CP0_ErrorEPC = env->PC - 4;
331 env->CP0_ErrorEPC = env->PC;
333 env->hflags = MIPS_HFLAG_ERL;
339 case EXCP_EXT_INTERRUPT:
341 if (env->CP0_Cause & (1 << CP0Ca_IV))
346 /* XXX: TODO: manage defered watch exceptions */
355 if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
375 env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
388 if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
392 if (env->CP0_Status & (1 << CP0St_BEV)) {
397 env->hflags |= MIPS_HFLAG_EXL;
399 env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
400 if (env->hflags & MIPS_HFLAG_BMASK) {
401 /* If the exception was raised from a delay slot,
402 * come back to the jump
404 env->CP0_EPC = env->PC - 4;
405 env->CP0_Cause |= 0x80000000;
406 env->hflags &= ~MIPS_HFLAG_BMASK;
408 env->CP0_EPC = env->PC;
409 env->CP0_Cause &= ~0x80000000;
414 fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
415 env->exception_index);
417 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
421 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
422 fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
423 " S %08x C %08x A %08x D %08x\n",
424 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
425 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
428 env->exception_index = EXCP_NONE;