1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
20 typedef union fpr_t fpr_t;
22 float64 fd; /* ieee double precision */
23 float32 fs[2];/* ieee single precision */
24 uint64_t d; /* binary double fixed-point */
25 uint32_t w[2]; /* binary single fixed-point */
27 /* define FP_ENDIAN_IDX to access the same location
28 * in the fpr_t union regardless of the host endianess
30 #if defined(WORDS_BIGENDIAN)
31 # define FP_ENDIAN_IDX 1
33 # define FP_ENDIAN_IDX 0
36 typedef struct r4k_tlb_t r4k_tlb_t;
51 typedef struct mips_def_t mips_def_t;
53 typedef struct CPUMIPSState CPUMIPSState;
55 /* General integer registers */
57 /* Special registers */
59 #if TARGET_LONG_BITS > HOST_LONG_BITS
65 /* Floating point registers */
67 #ifndef USE_HOST_FLOAT_REGS
72 float_status fp_status;
73 /* fpu implementation/revision register (fir) */
86 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
87 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
89 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
90 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
91 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
92 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
93 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
94 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
95 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
97 #define FP_UNDERFLOW 2
100 #define FP_INVALID 16
101 #define FP_UNIMPLEMENTED 32
105 int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
106 void (*do_tlbwi) (void);
107 void (*do_tlbwr) (void);
108 void (*do_tlbp) (void);
109 void (*do_tlbr) (void);
112 r4k_tlb_t tlb[MIPS_TLB_MAX];
118 target_ulong CP0_EntryLo0;
119 target_ulong CP0_EntryLo1;
120 target_ulong CP0_Context;
121 int32_t CP0_PageMask;
122 int32_t CP0_PageGrain;
125 target_ulong CP0_BadVAddr;
127 target_ulong CP0_EntryHi;
164 #define CP0Ca_IP_mask 0x0000FF00
166 target_ulong CP0_EPC;
210 #define CP0C3_DSPP 10
220 target_ulong CP0_LLAddr;
221 target_ulong CP0_WatchLo[8];
222 int32_t CP0_WatchHi[8];
223 target_ulong CP0_XContext;
224 int32_t CP0_Framemask;
228 #define CP0DB_LSNM 28
229 #define CP0DB_Doze 27
230 #define CP0DB_Halt 26
232 #define CP0DB_IBEP 24
233 #define CP0DB_DBEP 21
234 #define CP0DB_IEXI 20
244 target_ulong CP0_DEPC;
245 int32_t CP0_Performance0;
250 target_ulong CP0_ErrorEPC;
253 int interrupt_request;
257 int user_mode_only; /* user mode only simulation */
258 uint32_t hflags; /* CPU State */
259 /* TMASK defines different execution modes */
260 #define MIPS_HFLAG_TMASK 0x007F
261 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
262 #define MIPS_HFLAG_UM 0x0001 /* user mode */
263 #define MIPS_HFLAG_DM 0x0002 /* Debug mode */
264 #define MIPS_HFLAG_SM 0x0004 /* Supervisor mode */
265 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
266 #define MIPS_HFLAG_FPU 0x0010 /* FPU enabled */
267 #define MIPS_HFLAG_F64 0x0020 /* 64-bit FPU enabled */
268 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
269 /* If translation is interrupted between the branch instruction and
270 * the delay slot, record what type of branch it is so that we can
271 * resume translation properly. It might be possible to reduce
272 * this from three bits to two. */
273 #define MIPS_HFLAG_BMASK 0x0380
274 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
275 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
276 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
277 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
278 target_ulong btarget; /* Jump / branch target */
279 int bcond; /* Branch condition (if needed) */
281 int halted; /* TRUE if the CPU is in suspend state */
283 int SYNCI_Step; /* Address step size for SYNCI */
284 int CCRes; /* Cycle count resolution/divisor */
285 int Status_rw_bitmask; /* Read/write bits in CP0_Status */
287 #if defined(CONFIG_USER_ONLY)
288 target_ulong tls_value;
296 const char *kernel_filename;
297 const char *kernel_cmdline;
298 const char *initrd_filename;
300 mips_def_t *cpu_model;
302 struct QEMUTimer *timer; /* Internal timer */
305 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
306 target_ulong address, int rw, int access_type);
307 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
308 target_ulong address, int rw, int access_type);
309 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
310 target_ulong address, int rw, int access_type);
311 void r4k_do_tlbwi (void);
312 void r4k_do_tlbwr (void);
313 void r4k_do_tlbp (void);
314 void r4k_do_tlbr (void);
315 int mips_find_by_name (const unsigned char *name, mips_def_t **def);
316 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
317 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
321 /* Memory access type :
322 * may be needed for precise access rights control and precise exceptions.
325 /* 1 bit to define user level / supervisor access */
328 /* 1 bit to indicate direction */
330 /* Type of instruction that generated the access */
331 ACCESS_CODE = 0x10, /* Code fetch access */
332 ACCESS_INT = 0x20, /* Integer load/store access */
333 ACCESS_FLOAT = 0x30, /* floating point load/store access */
370 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
371 /* may change privilege level */
372 EXCP_BRANCH = 0x108, /* branch instruction */
373 EXCP_ERET = 0x10C, /* return from interrupt */
374 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
378 int cpu_mips_exec(CPUMIPSState *s);
379 CPUMIPSState *cpu_mips_init(void);
380 uint32_t cpu_mips_get_clock (void);
381 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
383 #endif /* !defined (__MIPS_CPU_H__) */