1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && SOLARISREV < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
20 typedef union fpr_t fpr_t;
22 float64 fd; /* ieee double precision */
23 float32 fs[2];/* ieee single precision */
24 uint64_t d; /* binary single fixed-point */
25 uint32_t w[2]; /* binary single fixed-point */
27 /* define FP_ENDIAN_IDX to access the same location
28 * in the fpr_t union regardless of the host endianess
30 #if defined(WORDS_BIGENDIAN)
31 # define FP_ENDIAN_IDX 1
33 # define FP_ENDIAN_IDX 0
36 #if defined(MIPS_USES_R4K_TLB)
37 typedef struct tlb_t tlb_t;
53 typedef struct CPUMIPSState CPUMIPSState;
55 /* General integer registers */
57 /* Special registers */
59 #if TARGET_LONG_BITS > HOST_LONG_BITS
66 #if defined(MIPS_USES_FPU)
67 /* Floating point registers */
69 #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
70 #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
71 #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
72 #define FPR_D(cpu, n) (FPR(cpu, n)->d)
73 #define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
75 #ifndef USE_HOST_FLOAT_REGS
80 float_status fp_status;
81 /* fpu implementation/revision register */
85 #define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0)
86 #define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0)
87 #define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0)
88 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
89 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
90 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
91 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
92 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0)
93 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0)
95 #define FP_UNDERFLOW 2
99 #define FP_UNIMPLEMENTED 32
102 #if defined(MIPS_USES_R4K_TLB)
103 tlb_t tlb[MIPS_TLB_MAX];
108 target_ulong CP0_EntryLo0;
109 target_ulong CP0_EntryLo1;
110 target_ulong CP0_Context;
111 int32_t CP0_PageMask;
112 int32_t CP0_PageGrain;
115 target_ulong CP0_BadVAddr;
117 target_ulong CP0_EntryHi;
154 #define CP0Ca_IP_mask 0x0000FF00
156 target_ulong CP0_EPC;
200 #define CP0C3_DSPP 10
208 target_ulong CP0_LLAddr;
209 target_ulong CP0_WatchLo;
211 target_ulong CP0_XContext;
212 int32_t CP0_Framemask;
216 #define CP0DB_LSNM 28
217 #define CP0DB_Doze 27
218 #define CP0DB_Halt 26
220 #define CP0DB_IBEP 24
221 #define CP0DB_DBEP 21
222 #define CP0DB_IEXI 20
232 target_ulong CP0_DEPC;
233 int32_t CP0_Performance0;
238 target_ulong CP0_ErrorEPC;
241 int interrupt_request;
245 int user_mode_only; /* user mode only simulation */
246 uint32_t hflags; /* CPU State */
247 /* TMASK defines different execution modes */
248 #define MIPS_HFLAG_TMASK 0x007F
249 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
250 #define MIPS_HFLAG_UM 0x0001 /* user mode */
251 #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
252 #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
253 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
254 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
255 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
256 /* If translation is interrupted between the branch instruction and
257 * the delay slot, record what type of branch it is so that we can
258 * resume translation properly. It might be possible to reduce
259 * this from three bits to two. */
260 #define MIPS_HFLAG_BMASK 0x0380
261 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
262 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
263 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
264 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
265 target_ulong btarget; /* Jump / branch target */
266 int bcond; /* Branch condition (if needed) */
268 int halted; /* TRUE if the CPU is in suspend state */
270 int SYNCI_Step; /* Address step size for SYNCI */
271 int CCRes; /* Cycle count resolution/divisor */
276 const char *kernel_filename;
277 const char *kernel_cmdline;
278 const char *initrd_filename;
280 struct QEMUTimer *timer; /* Internal timer */
285 /* Memory access type :
286 * may be needed for precise access rights control and precise exceptions.
289 /* 1 bit to define user level / supervisor access */
292 /* 1 bit to indicate direction */
294 /* Type of instruction that generated the access */
295 ACCESS_CODE = 0x10, /* Code fetch access */
296 ACCESS_INT = 0x20, /* Integer load/store access */
297 ACCESS_FLOAT = 0x30, /* floating point load/store access */
333 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
334 /* may change privilege level */
335 EXCP_BRANCH = 0x108, /* branch instruction */
336 EXCP_ERET = 0x10C, /* return from interrupt */
337 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
341 int cpu_mips_exec(CPUMIPSState *s);
342 CPUMIPSState *cpu_mips_init(void);
343 uint32_t cpu_mips_get_clock (void);
345 #endif /* !defined (__MIPS_CPU_H__) */