1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
20 typedef union fpr_t fpr_t;
22 float64 fd; /* ieee double precision */
23 float32 fs[2];/* ieee single precision */
24 uint64_t d; /* binary double fixed-point */
25 uint32_t w[2]; /* binary single fixed-point */
27 /* define FP_ENDIAN_IDX to access the same location
28 * in the fpr_t union regardless of the host endianess
30 #if defined(WORDS_BIGENDIAN)
31 # define FP_ENDIAN_IDX 1
33 # define FP_ENDIAN_IDX 0
36 typedef struct r4k_tlb_t r4k_tlb_t;
51 typedef struct CPUMIPSState CPUMIPSState;
53 /* General integer registers */
55 /* Special registers */
57 #if TARGET_LONG_BITS > HOST_LONG_BITS
63 /* Floating point registers */
65 #ifndef USE_HOST_FLOAT_REGS
70 float_status fp_status;
71 /* fpu implementation/revision register (fir) */
84 #define SET_FP_COND(num,env) do { (env->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0)
85 #define CLEAR_FP_COND(num,env) do { (env->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0)
86 #define IS_FP_COND_SET(num,env) (((env->fcr31) & ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23)))) != 0)
87 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
88 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
89 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
90 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
91 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
92 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
93 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
95 #define FP_UNDERFLOW 2
99 #define FP_UNIMPLEMENTED 32
103 int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
104 void (*do_tlbwi) (void);
105 void (*do_tlbwr) (void);
106 void (*do_tlbp) (void);
107 void (*do_tlbr) (void);
110 r4k_tlb_t tlb[MIPS_TLB_MAX];
116 target_ulong CP0_EntryLo0;
117 target_ulong CP0_EntryLo1;
118 target_ulong CP0_Context;
119 int32_t CP0_PageMask;
120 int32_t CP0_PageGrain;
123 target_ulong CP0_BadVAddr;
125 target_ulong CP0_EntryHi;
162 #define CP0Ca_IP_mask 0x0000FF00
164 target_ulong CP0_EPC;
208 #define CP0C3_DSPP 10
218 target_ulong CP0_LLAddr;
219 target_ulong CP0_WatchLo;
221 target_ulong CP0_XContext;
222 int32_t CP0_Framemask;
226 #define CP0DB_LSNM 28
227 #define CP0DB_Doze 27
228 #define CP0DB_Halt 26
230 #define CP0DB_IBEP 24
231 #define CP0DB_DBEP 21
232 #define CP0DB_IEXI 20
242 target_ulong CP0_DEPC;
243 int32_t CP0_Performance0;
248 target_ulong CP0_ErrorEPC;
251 int interrupt_request;
255 int user_mode_only; /* user mode only simulation */
256 uint32_t hflags; /* CPU State */
257 /* TMASK defines different execution modes */
258 #define MIPS_HFLAG_TMASK 0x007F
259 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
260 #define MIPS_HFLAG_UM 0x0001 /* user mode */
261 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
262 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
263 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
264 /* If translation is interrupted between the branch instruction and
265 * the delay slot, record what type of branch it is so that we can
266 * resume translation properly. It might be possible to reduce
267 * this from three bits to two. */
268 #define MIPS_HFLAG_BMASK 0x0380
269 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
270 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
271 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
272 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
273 target_ulong btarget; /* Jump / branch target */
274 int bcond; /* Branch condition (if needed) */
276 int halted; /* TRUE if the CPU is in suspend state */
278 int SYNCI_Step; /* Address step size for SYNCI */
279 int CCRes; /* Cycle count resolution/divisor */
280 int Status_rw_bitmask; /* Read/write bits in CP0_Status */
282 #if defined(CONFIG_USER_ONLY)
283 target_ulong tls_value;
291 const char *kernel_filename;
292 const char *kernel_cmdline;
293 const char *initrd_filename;
295 struct QEMUTimer *timer; /* Internal timer */
298 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
299 target_ulong address, int rw, int access_type);
300 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
301 target_ulong address, int rw, int access_type);
302 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
303 target_ulong address, int rw, int access_type);
304 void r4k_do_tlbwi (void);
305 void r4k_do_tlbwr (void);
306 void r4k_do_tlbp (void);
307 void r4k_do_tlbr (void);
308 typedef struct mips_def_t mips_def_t;
309 int mips_find_by_name (const unsigned char *name, mips_def_t **def);
310 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
311 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
315 /* Memory access type :
316 * may be needed for precise access rights control and precise exceptions.
319 /* 1 bit to define user level / supervisor access */
322 /* 1 bit to indicate direction */
324 /* Type of instruction that generated the access */
325 ACCESS_CODE = 0x10, /* Code fetch access */
326 ACCESS_INT = 0x20, /* Integer load/store access */
327 ACCESS_FLOAT = 0x30, /* floating point load/store access */
364 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
365 /* may change privilege level */
366 EXCP_BRANCH = 0x108, /* branch instruction */
367 EXCP_ERET = 0x10C, /* return from interrupt */
368 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
372 int cpu_mips_exec(CPUMIPSState *s);
373 CPUMIPSState *cpu_mips_init(void);
374 uint32_t cpu_mips_get_clock (void);
376 #endif /* !defined (__MIPS_CPU_H__) */