1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
22 typedef struct r4k_tlb_t r4k_tlb_t;
37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
38 struct CPUMIPSTLBContext {
41 int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
42 void (*do_tlbwi) (void);
43 void (*do_tlbwr) (void);
44 void (*do_tlbp) (void);
45 void (*do_tlbr) (void);
48 r4k_tlb_t tlb[MIPS_TLB_MAX];
53 typedef union fpr_t fpr_t;
55 float64 fd; /* ieee double precision */
56 float32 fs[2];/* ieee single precision */
57 uint64_t d; /* binary double fixed-point */
58 uint32_t w[2]; /* binary single fixed-point */
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianess
63 #if defined(WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
66 # define FP_ENDIAN_IDX 0
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70 struct CPUMIPSFPUContext {
71 /* Floating point registers */
73 #ifndef USE_HOST_FLOAT_REGS
78 float_status fp_status;
79 /* fpu implementation/revision register (fir) */
92 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
93 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
94 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
95 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
96 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
97 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
98 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
99 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
100 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
101 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
103 #define FP_UNDERFLOW 2
104 #define FP_OVERFLOW 4
106 #define FP_INVALID 16
107 #define FP_UNIMPLEMENTED 32
110 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
111 struct CPUMIPSMVPContext {
112 int32_t CP0_MVPControl;
113 #define CP0MVPCo_CPA 3
114 #define CP0MVPCo_STLB 2
115 #define CP0MVPCo_VPC 1
116 #define CP0MVPCo_EVP 0
117 int32_t CP0_MVPConf0;
118 #define CP0MVPC0_M 31
119 #define CP0MVPC0_TLBS 29
120 #define CP0MVPC0_GS 28
121 #define CP0MVPC0_PCP 27
122 #define CP0MVPC0_PTLBE 16
123 #define CP0MVPC0_TCA 15
124 #define CP0MVPC0_PVPE 10
125 #define CP0MVPC0_PTC 0
126 int32_t CP0_MVPConf1;
127 #define CP0MVPC1_CIM 31
128 #define CP0MVPC1_CIF 30
129 #define CP0MVPC1_PCX 20
130 #define CP0MVPC1_PCP2 10
131 #define CP0MVPC1_PCP1 0
134 typedef struct mips_def_t mips_def_t;
136 #define MIPS_SHADOW_SET_MAX 16
137 #define MIPS_TC_MAX 5
138 #define MIPS_DSP_ACC 4
140 typedef struct CPUMIPSState CPUMIPSState;
141 struct CPUMIPSState {
142 /* General integer registers */
143 target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
144 /* Special registers */
145 target_ulong PC[MIPS_TC_MAX];
146 #if TARGET_LONG_BITS > HOST_LONG_BITS
151 target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
152 target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
153 target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
154 target_ulong DSPControl[MIPS_TC_MAX];
156 CPUMIPSMVPContext *mvp;
157 CPUMIPSTLBContext *tlb;
158 CPUMIPSFPUContext *fpu;
162 target_ulong SEGMask;
165 /* CP0_MVP* are per MVP registers. */
167 int32_t CP0_VPEControl;
168 #define CP0VPECo_YSI 21
169 #define CP0VPECo_GSI 20
170 #define CP0VPECo_EXCPT 16
171 #define CP0VPECo_TE 15
172 #define CP0VPECo_TargTC 0
173 int32_t CP0_VPEConf0;
174 #define CP0VPEC0_M 31
175 #define CP0VPEC0_XTC 21
176 #define CP0VPEC0_TCS 19
177 #define CP0VPEC0_SCS 18
178 #define CP0VPEC0_DSC 17
179 #define CP0VPEC0_ICS 16
180 #define CP0VPEC0_MVP 1
181 #define CP0VPEC0_VPA 0
182 int32_t CP0_VPEConf1;
183 #define CP0VPEC1_NCX 20
184 #define CP0VPEC1_NCP2 10
185 #define CP0VPEC1_NCP1 0
186 target_ulong CP0_YQMask;
187 target_ulong CP0_VPESchedule;
188 target_ulong CP0_VPEScheFBack;
190 #define CP0VPEOpt_IWX7 15
191 #define CP0VPEOpt_IWX6 14
192 #define CP0VPEOpt_IWX5 13
193 #define CP0VPEOpt_IWX4 12
194 #define CP0VPEOpt_IWX3 11
195 #define CP0VPEOpt_IWX2 10
196 #define CP0VPEOpt_IWX1 9
197 #define CP0VPEOpt_IWX0 8
198 #define CP0VPEOpt_DWX7 7
199 #define CP0VPEOpt_DWX6 6
200 #define CP0VPEOpt_DWX5 5
201 #define CP0VPEOpt_DWX4 4
202 #define CP0VPEOpt_DWX3 3
203 #define CP0VPEOpt_DWX2 2
204 #define CP0VPEOpt_DWX1 1
205 #define CP0VPEOpt_DWX0 0
206 target_ulong CP0_EntryLo0;
207 int32_t CP0_TCStatus[MIPS_TC_MAX];
208 #define CP0TCSt_TCU3 31
209 #define CP0TCSt_TCU2 30
210 #define CP0TCSt_TCU1 29
211 #define CP0TCSt_TCU0 28
212 #define CP0TCSt_TMX 27
213 #define CP0TCSt_RNST 23
214 #define CP0TCSt_TDS 21
215 #define CP0TCSt_DT 20
216 #define CP0TCSt_DA 15
218 #define CP0TCSt_TKSU 11
219 #define CP0TCSt_IXMT 10
220 #define CP0TCSt_TASID 0
221 int32_t CP0_TCBind[MIPS_TC_MAX];
222 #define CP0TCBd_CurTC 21
223 #define CP0TCBd_TBE 17
224 #define CP0TCBd_CurVPE 0
225 target_ulong CP0_TCHalt[MIPS_TC_MAX];
226 target_ulong CP0_TCContext[MIPS_TC_MAX];
227 target_ulong CP0_TCSchedule[MIPS_TC_MAX];
228 target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
229 target_ulong CP0_EntryLo1;
230 target_ulong CP0_Context;
231 int32_t CP0_PageMask;
232 int32_t CP0_PageGrain;
234 int32_t CP0_SRSConf0_rw_bitmask;
235 int32_t CP0_SRSConf0;
236 #define CP0SRSC0_M 31
237 #define CP0SRSC0_SRS3 20
238 #define CP0SRSC0_SRS2 10
239 #define CP0SRSC0_SRS1 0
240 int32_t CP0_SRSConf1_rw_bitmask;
241 int32_t CP0_SRSConf1;
242 #define CP0SRSC1_M 31
243 #define CP0SRSC1_SRS6 20
244 #define CP0SRSC1_SRS5 10
245 #define CP0SRSC1_SRS4 0
246 int32_t CP0_SRSConf2_rw_bitmask;
247 int32_t CP0_SRSConf2;
248 #define CP0SRSC2_M 31
249 #define CP0SRSC2_SRS9 20
250 #define CP0SRSC2_SRS8 10
251 #define CP0SRSC2_SRS7 0
252 int32_t CP0_SRSConf3_rw_bitmask;
253 int32_t CP0_SRSConf3;
254 #define CP0SRSC3_M 31
255 #define CP0SRSC3_SRS12 20
256 #define CP0SRSC3_SRS11 10
257 #define CP0SRSC3_SRS10 0
258 int32_t CP0_SRSConf4_rw_bitmask;
259 int32_t CP0_SRSConf4;
260 #define CP0SRSC4_SRS15 20
261 #define CP0SRSC4_SRS14 10
262 #define CP0SRSC4_SRS13 0
264 target_ulong CP0_BadVAddr;
266 target_ulong CP0_EntryHi;
292 #define CP0IntCtl_IPTI 29
293 #define CP0IntCtl_IPPC1 26
294 #define CP0IntCtl_VS 5
296 #define CP0SRSCtl_HSS 26
297 #define CP0SRSCtl_EICSS 18
298 #define CP0SRSCtl_ESS 12
299 #define CP0SRSCtl_PSS 6
300 #define CP0SRSCtl_CSS 0
302 #define CP0SRSMap_SSV7 28
303 #define CP0SRSMap_SSV6 24
304 #define CP0SRSMap_SSV5 20
305 #define CP0SRSMap_SSV4 16
306 #define CP0SRSMap_SSV3 12
307 #define CP0SRSMap_SSV2 8
308 #define CP0SRSMap_SSV1 4
309 #define CP0SRSMap_SSV0 0
319 #define CP0Ca_IP_mask 0x0000FF00
321 target_ulong CP0_EPC;
365 #define CP0C3_DSPP 10
375 /* XXX: Maybe make LLAddr per-TC? */
376 target_ulong CP0_LLAddr;
377 target_ulong CP0_WatchLo[8];
378 int32_t CP0_WatchHi[8];
379 target_ulong CP0_XContext;
380 int32_t CP0_Framemask;
384 #define CP0DB_LSNM 28
385 #define CP0DB_Doze 27
386 #define CP0DB_Halt 26
388 #define CP0DB_IBEP 24
389 #define CP0DB_DBEP 21
390 #define CP0DB_IEXI 20
400 int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
401 target_ulong CP0_DEPC;
402 int32_t CP0_Performance0;
407 target_ulong CP0_ErrorEPC;
410 int interrupt_request;
414 int user_mode_only; /* user mode only simulation */
415 uint32_t hflags; /* CPU State */
416 /* TMASK defines different execution modes */
417 #define MIPS_HFLAG_TMASK 0x00FF
418 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
419 #define MIPS_HFLAG_UM 0x0001 /* user mode */
420 #define MIPS_HFLAG_DM 0x0002 /* Debug mode */
421 #define MIPS_HFLAG_SM 0x0004 /* Supervisor mode */
422 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
423 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
424 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
425 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
426 #define MIPS_HFLAG_RE 0x0080 /* Reversed endianness */
427 /* If translation is interrupted between the branch instruction and
428 * the delay slot, record what type of branch it is so that we can
429 * resume translation properly. It might be possible to reduce
430 * this from three bits to two. */
431 #define MIPS_HFLAG_BMASK 0x0700
432 #define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
433 #define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
434 #define MIPS_HFLAG_BL 0x0300 /* Likely branch */
435 #define MIPS_HFLAG_BR 0x0400 /* branch to register (can't link TB) */
436 target_ulong btarget; /* Jump / branch target */
437 int bcond; /* Branch condition (if needed) */
439 int halted; /* TRUE if the CPU is in suspend state */
441 int SYNCI_Step; /* Address step size for SYNCI */
442 int CCRes; /* Cycle count resolution/divisor */
443 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
444 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
445 int insn_flags; /* Supported instruction set */
447 #ifdef CONFIG_USER_ONLY
448 target_ulong tls_value;
454 const char *kernel_filename;
455 const char *kernel_cmdline;
456 const char *initrd_filename;
458 mips_def_t *cpu_model;
459 #ifndef CONFIG_USER_ONLY
463 struct QEMUTimer *timer; /* Internal timer */
466 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
467 target_ulong address, int rw, int access_type);
468 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
469 target_ulong address, int rw, int access_type);
470 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
471 target_ulong address, int rw, int access_type);
472 void r4k_do_tlbwi (void);
473 void r4k_do_tlbwr (void);
474 void r4k_do_tlbp (void);
475 void r4k_do_tlbr (void);
476 int mips_find_by_name (const unsigned char *name, mips_def_t **def);
477 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
478 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
480 #define CPUState CPUMIPSState
481 #define cpu_init cpu_mips_init
482 #define cpu_exec cpu_mips_exec
483 #define cpu_gen_code cpu_mips_gen_code
484 #define cpu_signal_handler cpu_mips_signal_handler
488 /* Memory access type :
489 * may be needed for precise access rights control and precise exceptions.
492 /* 1 bit to define user level / supervisor access */
495 /* 1 bit to indicate direction */
497 /* Type of instruction that generated the access */
498 ACCESS_CODE = 0x10, /* Code fetch access */
499 ACCESS_INT = 0x20, /* Integer load/store access */
500 ACCESS_FLOAT = 0x30, /* floating point load/store access */
538 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
539 /* may change privilege level */
540 EXCP_BRANCH = 0x108, /* branch instruction */
541 EXCP_ERET = 0x10C, /* return from interrupt */
542 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
546 int cpu_mips_exec(CPUMIPSState *s);
547 CPUMIPSState *cpu_mips_init(void);
548 uint32_t cpu_mips_get_clock (void);
549 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
551 #endif /* !defined (__MIPS_CPU_H__) */