4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 /* XXX: move that elsewhere */
33 static uint16_t *gen_opc_ptr;
34 static uint32_t *gen_opparam_ptr;
36 #define PREFIX_REPZ 0x01
37 #define PREFIX_REPNZ 0x02
38 #define PREFIX_LOCK 0x04
39 #define PREFIX_DATA 0x08
40 #define PREFIX_ADR 0x10
42 typedef struct DisasContext {
43 /* current insn context */
44 int override; /* -1 if no override */
47 uint8_t *pc; /* pc = eip + cs_base */
48 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
49 static state change (stop translation) */
50 /* current block context */
51 uint8_t *cs_base; /* base of CS segment */
52 int pe; /* protected mode */
53 int code32; /* 32 bit code segment */
54 int ss32; /* 32 bit stack segment */
55 int cc_op; /* current CC operation */
56 int addseg; /* non zero if either DS/ES/SS have a non zero base */
57 int f_st; /* currently unused */
58 int vm86; /* vm86 mode */
61 int tf; /* TF cpu flag */
62 int singlestep_enabled; /* "hardware" single step enabled */
63 int jmp_opt; /* use direct block chaining for direct jumps */
64 int mem_index; /* select memory access functions */
65 int flags; /* all execution flags */
66 struct TranslationBlock *tb;
67 int popl_esp_hack; /* for correct popl with esp base handling */
70 static void gen_eob(DisasContext *s);
71 static void gen_jmp(DisasContext *s, unsigned int eip);
73 /* i386 arith/logic operations */
93 OP_SHL1, /* undocumented */
98 #define DEF(s, n, copy_size) INDEX_op_ ## s,
115 /* I386 int registers */
116 OR_EAX, /* MUST be even numbered */
124 OR_TMP0, /* temporary operand register */
126 OR_A0, /* temporary register used when doing address evaluation */
127 OR_ZERO, /* fixed zero register */
131 static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
164 static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
197 static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
220 static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
290 static GenOpFunc *gen_op_movl_A0_reg[8] = {
301 static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
313 gen_op_addl_A0_EAX_s1,
314 gen_op_addl_A0_ECX_s1,
315 gen_op_addl_A0_EDX_s1,
316 gen_op_addl_A0_EBX_s1,
317 gen_op_addl_A0_ESP_s1,
318 gen_op_addl_A0_EBP_s1,
319 gen_op_addl_A0_ESI_s1,
320 gen_op_addl_A0_EDI_s1,
323 gen_op_addl_A0_EAX_s2,
324 gen_op_addl_A0_ECX_s2,
325 gen_op_addl_A0_EDX_s2,
326 gen_op_addl_A0_EBX_s2,
327 gen_op_addl_A0_ESP_s2,
328 gen_op_addl_A0_EBP_s2,
329 gen_op_addl_A0_ESI_s2,
330 gen_op_addl_A0_EDI_s2,
333 gen_op_addl_A0_EAX_s3,
334 gen_op_addl_A0_ECX_s3,
335 gen_op_addl_A0_EDX_s3,
336 gen_op_addl_A0_EBX_s3,
337 gen_op_addl_A0_ESP_s3,
338 gen_op_addl_A0_EBP_s3,
339 gen_op_addl_A0_ESI_s3,
340 gen_op_addl_A0_EDI_s3,
344 static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
346 gen_op_cmovw_EAX_T1_T0,
347 gen_op_cmovw_ECX_T1_T0,
348 gen_op_cmovw_EDX_T1_T0,
349 gen_op_cmovw_EBX_T1_T0,
350 gen_op_cmovw_ESP_T1_T0,
351 gen_op_cmovw_EBP_T1_T0,
352 gen_op_cmovw_ESI_T1_T0,
353 gen_op_cmovw_EDI_T1_T0,
356 gen_op_cmovl_EAX_T1_T0,
357 gen_op_cmovl_ECX_T1_T0,
358 gen_op_cmovl_EDX_T1_T0,
359 gen_op_cmovl_EBX_T1_T0,
360 gen_op_cmovl_ESP_T1_T0,
361 gen_op_cmovl_EBP_T1_T0,
362 gen_op_cmovl_ESI_T1_T0,
363 gen_op_cmovl_EDI_T1_T0,
367 static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
378 #define DEF_ARITHC(SUFFIX)\
380 gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
381 gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
384 gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
385 gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
388 gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
389 gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
392 static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
396 static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[9][2] = {
398 #ifndef CONFIG_USER_ONLY
404 static const int cc_op_arithb[8] = {
415 #define DEF_CMPXCHG(SUFFIX)\
416 gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
417 gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
418 gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,
421 static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
425 static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[9] = {
427 #ifndef CONFIG_USER_ONLY
433 #define DEF_SHIFT(SUFFIX)\
435 gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
436 gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
437 gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
438 gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
439 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
440 gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
441 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
442 gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
445 gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
446 gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
447 gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
448 gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
449 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
450 gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
451 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
452 gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
455 gen_op_roll ## SUFFIX ## _T0_T1_cc,\
456 gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
457 gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
458 gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
459 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
460 gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
461 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
462 gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
465 static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
469 static GenOpFunc *gen_op_shift_mem_T0_T1_cc[9][8] = {
471 #ifndef CONFIG_USER_ONLY
477 #define DEF_SHIFTD(SUFFIX, op)\
483 gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
484 gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
487 gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
488 gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
492 static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[3][2] = {
496 static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[3][2] = {
500 static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[9][2] = {
502 #ifndef CONFIG_USER_ONLY
503 DEF_SHIFTD(_kernel, im)
504 DEF_SHIFTD(_user, im)
508 static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[9][2] = {
509 DEF_SHIFTD(_raw, ECX)
510 #ifndef CONFIG_USER_ONLY
511 DEF_SHIFTD(_kernel, ECX)
512 DEF_SHIFTD(_user, ECX)
516 static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
519 gen_op_btsw_T0_T1_cc,
520 gen_op_btrw_T0_T1_cc,
521 gen_op_btcw_T0_T1_cc,
525 gen_op_btsl_T0_T1_cc,
526 gen_op_btrl_T0_T1_cc,
527 gen_op_btcl_T0_T1_cc,
531 static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
542 static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
543 gen_op_ldsb_raw_T0_A0,
544 gen_op_ldsw_raw_T0_A0,
546 #ifndef CONFIG_USER_ONLY
547 gen_op_ldsb_kernel_T0_A0,
548 gen_op_ldsw_kernel_T0_A0,
551 gen_op_ldsb_user_T0_A0,
552 gen_op_ldsw_user_T0_A0,
557 static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
558 gen_op_ldub_raw_T0_A0,
559 gen_op_lduw_raw_T0_A0,
562 #ifndef CONFIG_USER_ONLY
563 gen_op_ldub_kernel_T0_A0,
564 gen_op_lduw_kernel_T0_A0,
567 gen_op_ldub_user_T0_A0,
568 gen_op_lduw_user_T0_A0,
573 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
574 static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
575 gen_op_ldub_raw_T0_A0,
576 gen_op_lduw_raw_T0_A0,
577 gen_op_ldl_raw_T0_A0,
579 #ifndef CONFIG_USER_ONLY
580 gen_op_ldub_kernel_T0_A0,
581 gen_op_lduw_kernel_T0_A0,
582 gen_op_ldl_kernel_T0_A0,
584 gen_op_ldub_user_T0_A0,
585 gen_op_lduw_user_T0_A0,
586 gen_op_ldl_user_T0_A0,
590 static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
591 gen_op_ldub_raw_T1_A0,
592 gen_op_lduw_raw_T1_A0,
593 gen_op_ldl_raw_T1_A0,
595 #ifndef CONFIG_USER_ONLY
596 gen_op_ldub_kernel_T1_A0,
597 gen_op_lduw_kernel_T1_A0,
598 gen_op_ldl_kernel_T1_A0,
600 gen_op_ldub_user_T1_A0,
601 gen_op_lduw_user_T1_A0,
602 gen_op_ldl_user_T1_A0,
606 static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
607 gen_op_stb_raw_T0_A0,
608 gen_op_stw_raw_T0_A0,
609 gen_op_stl_raw_T0_A0,
611 #ifndef CONFIG_USER_ONLY
612 gen_op_stb_kernel_T0_A0,
613 gen_op_stw_kernel_T0_A0,
614 gen_op_stl_kernel_T0_A0,
616 gen_op_stb_user_T0_A0,
617 gen_op_stw_user_T0_A0,
618 gen_op_stl_user_T0_A0,
622 static GenOpFunc *gen_op_st_T1_A0[3 * 3] = {
624 gen_op_stw_raw_T1_A0,
625 gen_op_stl_raw_T1_A0,
627 #ifndef CONFIG_USER_ONLY
629 gen_op_stw_kernel_T1_A0,
630 gen_op_stl_kernel_T1_A0,
633 gen_op_stw_user_T1_A0,
634 gen_op_stl_user_T1_A0,
638 static inline void gen_string_movl_A0_ESI(DisasContext *s)
642 override = s->override;
645 if (s->addseg && override < 0)
648 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
649 gen_op_addl_A0_reg_sN[0][R_ESI]();
651 gen_op_movl_A0_reg[R_ESI]();
654 /* 16 address, always override */
657 gen_op_movl_A0_reg[R_ESI]();
658 gen_op_andl_A0_ffff();
659 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
663 static inline void gen_string_movl_A0_EDI(DisasContext *s)
667 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
668 gen_op_addl_A0_reg_sN[0][R_EDI]();
670 gen_op_movl_A0_reg[R_EDI]();
673 gen_op_movl_A0_reg[R_EDI]();
674 gen_op_andl_A0_ffff();
675 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
679 static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
680 gen_op_movl_T0_Dshiftb,
681 gen_op_movl_T0_Dshiftw,
682 gen_op_movl_T0_Dshiftl,
685 static GenOpFunc2 *gen_op_jz_ecx[2] = {
690 static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
695 static GenOpFunc *gen_op_dec_ECX[2] = {
700 #ifdef USE_DIRECT_JUMP
701 typedef GenOpFunc GenOpFuncTB2;
702 #define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot]()
704 typedef GenOpFunc1 GenOpFuncTB2;
705 #define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot](tb)
708 static GenOpFuncTB2 *gen_op_string_jnz_sub2[2][3] = {
710 gen_op_string_jnz_subb,
711 gen_op_string_jnz_subw,
712 gen_op_string_jnz_subl,
715 gen_op_string_jz_subb,
716 gen_op_string_jz_subw,
717 gen_op_string_jz_subl,
721 static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
723 gen_op_string_jnz_subb_im,
724 gen_op_string_jnz_subw_im,
725 gen_op_string_jnz_subl_im,
728 gen_op_string_jz_subb_im,
729 gen_op_string_jz_subw_im,
730 gen_op_string_jz_subl_im,
734 static GenOpFunc *gen_op_in_DX_T0[3] = {
740 static GenOpFunc *gen_op_out_DX_T0[3] = {
746 static GenOpFunc *gen_op_in[3] = {
752 static GenOpFunc *gen_op_out[3] = {
758 static GenOpFunc *gen_check_io_T0[3] = {
764 static GenOpFunc *gen_check_io_DX[3] = {
770 static void gen_check_io(DisasContext *s, int ot, int use_dx, int cur_eip)
772 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
773 if (s->cc_op != CC_OP_DYNAMIC)
774 gen_op_set_cc_op(s->cc_op);
775 gen_op_jmp_im(cur_eip);
777 gen_check_io_DX[ot]();
779 gen_check_io_T0[ot]();
783 static inline void gen_movs(DisasContext *s, int ot)
785 gen_string_movl_A0_ESI(s);
786 gen_op_ld_T0_A0[ot + s->mem_index]();
787 gen_string_movl_A0_EDI(s);
788 gen_op_st_T0_A0[ot + s->mem_index]();
789 gen_op_movl_T0_Dshift[ot]();
791 gen_op_addl_ESI_T0();
792 gen_op_addl_EDI_T0();
794 gen_op_addw_ESI_T0();
795 gen_op_addw_EDI_T0();
799 static inline void gen_update_cc_op(DisasContext *s)
801 if (s->cc_op != CC_OP_DYNAMIC) {
802 gen_op_set_cc_op(s->cc_op);
803 s->cc_op = CC_OP_DYNAMIC;
807 static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
810 gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
812 /* XXX: does not work with gdbstub "ice" single step - not a
814 gen_op_jz_ecx_im[s->aflag](next_eip);
818 static inline void gen_stos(DisasContext *s, int ot)
820 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
821 gen_string_movl_A0_EDI(s);
822 gen_op_st_T0_A0[ot + s->mem_index]();
823 gen_op_movl_T0_Dshift[ot]();
825 gen_op_addl_EDI_T0();
827 gen_op_addw_EDI_T0();
831 static inline void gen_lods(DisasContext *s, int ot)
833 gen_string_movl_A0_ESI(s);
834 gen_op_ld_T0_A0[ot + s->mem_index]();
835 gen_op_mov_reg_T0[ot][R_EAX]();
836 gen_op_movl_T0_Dshift[ot]();
838 gen_op_addl_ESI_T0();
840 gen_op_addw_ESI_T0();
844 static inline void gen_scas(DisasContext *s, int ot)
846 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
847 gen_string_movl_A0_EDI(s);
848 gen_op_ld_T1_A0[ot + s->mem_index]();
849 gen_op_cmpl_T0_T1_cc();
850 gen_op_movl_T0_Dshift[ot]();
852 gen_op_addl_EDI_T0();
854 gen_op_addw_EDI_T0();
858 static inline void gen_cmps(DisasContext *s, int ot)
860 gen_string_movl_A0_ESI(s);
861 gen_op_ld_T0_A0[ot + s->mem_index]();
862 gen_string_movl_A0_EDI(s);
863 gen_op_ld_T1_A0[ot + s->mem_index]();
864 gen_op_cmpl_T0_T1_cc();
865 gen_op_movl_T0_Dshift[ot]();
867 gen_op_addl_ESI_T0();
868 gen_op_addl_EDI_T0();
870 gen_op_addw_ESI_T0();
871 gen_op_addw_EDI_T0();
875 static inline void gen_ins(DisasContext *s, int ot)
877 gen_op_in_DX_T0[ot]();
878 gen_string_movl_A0_EDI(s);
879 gen_op_st_T0_A0[ot + s->mem_index]();
880 gen_op_movl_T0_Dshift[ot]();
882 gen_op_addl_EDI_T0();
884 gen_op_addw_EDI_T0();
888 static inline void gen_outs(DisasContext *s, int ot)
890 gen_string_movl_A0_ESI(s);
891 gen_op_ld_T0_A0[ot + s->mem_index]();
892 gen_op_out_DX_T0[ot]();
893 gen_op_movl_T0_Dshift[ot]();
895 gen_op_addl_ESI_T0();
897 gen_op_addw_ESI_T0();
901 /* same method as Valgrind : we generate jumps to current or next
903 #define GEN_REPZ(op) \
904 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
905 unsigned int cur_eip, unsigned int next_eip) \
907 gen_update_cc_op(s); \
908 gen_jz_ecx_string(s, next_eip); \
910 gen_op_dec_ECX[s->aflag](); \
911 /* a loop would cause two single step exceptions if ECX = 1 \
912 before rep string_insn */ \
914 gen_op_jz_ecx_im[s->aflag](next_eip); \
915 gen_jmp(s, cur_eip); \
918 #define GEN_REPZ2(op) \
919 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
920 unsigned int cur_eip, \
921 unsigned int next_eip, \
924 gen_update_cc_op(s); \
925 gen_jz_ecx_string(s, next_eip); \
927 gen_op_dec_ECX[s->aflag](); \
928 gen_op_set_cc_op(CC_OP_SUBB + ot); \
930 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
932 gen_op_string_jnz_sub(nz, ot, (long)s->tb); \
934 gen_op_jz_ecx_im[s->aflag](next_eip); \
935 gen_jmp(s, cur_eip); \
957 static GenOpFunc3 *gen_jcc_sub[3][8] = {
989 static GenOpFunc2 *gen_op_loop[2][4] = {
1004 static GenOpFunc *gen_setcc_slow[8] = {
1015 static GenOpFunc *gen_setcc_sub[3][8] = {
1018 gen_op_setb_T0_subb,
1019 gen_op_setz_T0_subb,
1020 gen_op_setbe_T0_subb,
1021 gen_op_sets_T0_subb,
1023 gen_op_setl_T0_subb,
1024 gen_op_setle_T0_subb,
1028 gen_op_setb_T0_subw,
1029 gen_op_setz_T0_subw,
1030 gen_op_setbe_T0_subw,
1031 gen_op_sets_T0_subw,
1033 gen_op_setl_T0_subw,
1034 gen_op_setle_T0_subw,
1038 gen_op_setb_T0_subl,
1039 gen_op_setz_T0_subl,
1040 gen_op_setbe_T0_subl,
1041 gen_op_sets_T0_subl,
1043 gen_op_setl_T0_subl,
1044 gen_op_setle_T0_subl,
1048 static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1049 gen_op_fadd_ST0_FT0,
1050 gen_op_fmul_ST0_FT0,
1051 gen_op_fcom_ST0_FT0,
1052 gen_op_fcom_ST0_FT0,
1053 gen_op_fsub_ST0_FT0,
1054 gen_op_fsubr_ST0_FT0,
1055 gen_op_fdiv_ST0_FT0,
1056 gen_op_fdivr_ST0_FT0,
1059 /* NOTE the exception in "r" op ordering */
1060 static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1061 gen_op_fadd_STN_ST0,
1062 gen_op_fmul_STN_ST0,
1065 gen_op_fsubr_STN_ST0,
1066 gen_op_fsub_STN_ST0,
1067 gen_op_fdivr_STN_ST0,
1068 gen_op_fdiv_STN_ST0,
1071 /* if d == OR_TMP0, it means memory operand (address in A0) */
1072 static void gen_op(DisasContext *s1, int op, int ot, int d)
1074 GenOpFunc *gen_update_cc;
1077 gen_op_mov_TN_reg[ot][0][d]();
1079 gen_op_ld_T0_A0[ot + s1->mem_index]();
1084 if (s1->cc_op != CC_OP_DYNAMIC)
1085 gen_op_set_cc_op(s1->cc_op);
1087 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1088 gen_op_mov_reg_T0[ot][d]();
1090 gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1092 s1->cc_op = CC_OP_DYNAMIC;
1095 gen_op_addl_T0_T1();
1096 s1->cc_op = CC_OP_ADDB + ot;
1097 gen_update_cc = gen_op_update2_cc;
1100 gen_op_subl_T0_T1();
1101 s1->cc_op = CC_OP_SUBB + ot;
1102 gen_update_cc = gen_op_update2_cc;
1108 gen_op_arith_T0_T1_cc[op]();
1109 s1->cc_op = CC_OP_LOGICB + ot;
1110 gen_update_cc = gen_op_update1_cc;
1113 gen_op_cmpl_T0_T1_cc();
1114 s1->cc_op = CC_OP_SUBB + ot;
1115 gen_update_cc = NULL;
1118 if (op != OP_CMPL) {
1120 gen_op_mov_reg_T0[ot][d]();
1122 gen_op_st_T0_A0[ot + s1->mem_index]();
1124 /* the flags update must happen after the memory write (precise
1125 exception support) */
1131 /* if d == OR_TMP0, it means memory operand (address in A0) */
1132 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1135 gen_op_mov_TN_reg[ot][0][d]();
1137 gen_op_ld_T0_A0[ot + s1->mem_index]();
1138 if (s1->cc_op != CC_OP_DYNAMIC)
1139 gen_op_set_cc_op(s1->cc_op);
1142 s1->cc_op = CC_OP_INCB + ot;
1145 s1->cc_op = CC_OP_DECB + ot;
1148 gen_op_mov_reg_T0[ot][d]();
1150 gen_op_st_T0_A0[ot + s1->mem_index]();
1151 gen_op_update_inc_cc();
1154 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1157 gen_op_mov_TN_reg[ot][0][d]();
1159 gen_op_ld_T0_A0[ot + s1->mem_index]();
1161 gen_op_mov_TN_reg[ot][1][s]();
1162 /* for zero counts, flags are not updated, so must do it dynamically */
1163 if (s1->cc_op != CC_OP_DYNAMIC)
1164 gen_op_set_cc_op(s1->cc_op);
1167 gen_op_shift_T0_T1_cc[ot][op]();
1169 gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1171 gen_op_mov_reg_T0[ot][d]();
1172 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1175 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1177 /* currently not optimized */
1178 gen_op_movl_T1_im(c);
1179 gen_shift(s1, op, ot, d, OR_TMP1);
1182 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1189 int mod, rm, code, override, must_add_seg;
1191 override = s->override;
1192 must_add_seg = s->addseg;
1195 mod = (modrm >> 6) & 3;
1207 code = ldub_code(s->pc++);
1208 scale = (code >> 6) & 3;
1209 index = (code >> 3) & 7;
1217 disp = ldl_code(s->pc);
1224 disp = (int8_t)ldub_code(s->pc++);
1228 disp = ldl_code(s->pc);
1234 /* for correct popl handling with esp */
1235 if (base == 4 && s->popl_esp_hack)
1236 disp += s->popl_esp_hack;
1237 gen_op_movl_A0_reg[base]();
1239 gen_op_addl_A0_im(disp);
1241 gen_op_movl_A0_im(disp);
1243 /* XXX: index == 4 is always invalid */
1244 if (havesib && (index != 4 || scale != 0)) {
1245 gen_op_addl_A0_reg_sN[scale][index]();
1249 if (base == R_EBP || base == R_ESP)
1254 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1260 disp = lduw_code(s->pc);
1262 gen_op_movl_A0_im(disp);
1263 rm = 0; /* avoid SS override */
1270 disp = (int8_t)ldub_code(s->pc++);
1274 disp = lduw_code(s->pc);
1280 gen_op_movl_A0_reg[R_EBX]();
1281 gen_op_addl_A0_reg_sN[0][R_ESI]();
1284 gen_op_movl_A0_reg[R_EBX]();
1285 gen_op_addl_A0_reg_sN[0][R_EDI]();
1288 gen_op_movl_A0_reg[R_EBP]();
1289 gen_op_addl_A0_reg_sN[0][R_ESI]();
1292 gen_op_movl_A0_reg[R_EBP]();
1293 gen_op_addl_A0_reg_sN[0][R_EDI]();
1296 gen_op_movl_A0_reg[R_ESI]();
1299 gen_op_movl_A0_reg[R_EDI]();
1302 gen_op_movl_A0_reg[R_EBP]();
1306 gen_op_movl_A0_reg[R_EBX]();
1310 gen_op_addl_A0_im(disp);
1311 gen_op_andl_A0_ffff();
1315 if (rm == 2 || rm == 3 || rm == 6)
1320 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1330 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1332 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1334 int mod, rm, opreg, disp;
1336 mod = (modrm >> 6) & 3;
1341 gen_op_mov_TN_reg[ot][0][reg]();
1342 gen_op_mov_reg_T0[ot][rm]();
1344 gen_op_mov_TN_reg[ot][0][rm]();
1346 gen_op_mov_reg_T0[ot][reg]();
1349 gen_lea_modrm(s, modrm, &opreg, &disp);
1352 gen_op_mov_TN_reg[ot][0][reg]();
1353 gen_op_st_T0_A0[ot + s->mem_index]();
1355 gen_op_ld_T0_A0[ot + s->mem_index]();
1357 gen_op_mov_reg_T0[ot][reg]();
1362 static inline uint32_t insn_get(DisasContext *s, int ot)
1368 ret = ldub_code(s->pc);
1372 ret = lduw_code(s->pc);
1377 ret = ldl_code(s->pc);
1384 static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1386 TranslationBlock *tb;
1391 jcc_op = (b >> 1) & 7;
1395 /* we optimize the cmp/jcc case */
1399 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1402 /* some jumps are easy to compute */
1429 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1432 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1444 if (s->cc_op != CC_OP_DYNAMIC)
1445 gen_op_set_cc_op(s->cc_op);
1448 gen_setcc_slow[jcc_op]();
1454 func((long)tb, val, next_eip);
1456 func((long)tb, next_eip, val);
1460 if (s->cc_op != CC_OP_DYNAMIC) {
1461 gen_op_set_cc_op(s->cc_op);
1462 s->cc_op = CC_OP_DYNAMIC;
1464 gen_setcc_slow[jcc_op]();
1466 gen_op_jcc_im(val, next_eip);
1468 gen_op_jcc_im(next_eip, val);
1474 static void gen_setcc(DisasContext *s, int b)
1480 jcc_op = (b >> 1) & 7;
1482 /* we optimize the cmp/jcc case */
1486 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1491 /* some jumps are easy to compute */
1509 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1512 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1520 if (s->cc_op != CC_OP_DYNAMIC)
1521 gen_op_set_cc_op(s->cc_op);
1522 func = gen_setcc_slow[jcc_op];
1531 /* move T0 to seg_reg and compute if the CPU state may change. Never
1532 call this function with seg_reg == R_CS */
1533 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1535 if (s->pe && !s->vm86) {
1536 /* XXX: optimize by finding processor state dynamically */
1537 if (s->cc_op != CC_OP_DYNAMIC)
1538 gen_op_set_cc_op(s->cc_op);
1539 gen_op_jmp_im(cur_eip);
1540 gen_op_movl_seg_T0(seg_reg);
1541 /* abort translation because the addseg value may change or
1542 because ss32 may change. For R_SS, translation must always
1543 stop as a special handling must be done to disable hardware
1544 interrupts for the next instruction */
1545 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
1548 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1549 if (seg_reg == R_SS)
1554 static inline void gen_stack_update(DisasContext *s, int addend)
1558 gen_op_addl_ESP_2();
1559 else if (addend == 4)
1560 gen_op_addl_ESP_4();
1562 gen_op_addl_ESP_im(addend);
1565 gen_op_addw_ESP_2();
1566 else if (addend == 4)
1567 gen_op_addw_ESP_4();
1569 gen_op_addw_ESP_im(addend);
1573 /* generate a push. It depends on ss32, addseg and dflag */
1574 static void gen_push_T0(DisasContext *s)
1576 gen_op_movl_A0_reg[R_ESP]();
1583 gen_op_movl_T1_A0();
1584 gen_op_addl_A0_SS();
1587 gen_op_andl_A0_ffff();
1588 gen_op_movl_T1_A0();
1589 gen_op_addl_A0_SS();
1591 gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
1592 if (s->ss32 && !s->addseg)
1593 gen_op_movl_ESP_A0();
1595 gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
1598 /* generate a push. It depends on ss32, addseg and dflag */
1599 /* slower version for T1, only used for call Ev */
1600 static void gen_push_T1(DisasContext *s)
1602 gen_op_movl_A0_reg[R_ESP]();
1609 gen_op_addl_A0_SS();
1612 gen_op_andl_A0_ffff();
1613 gen_op_addl_A0_SS();
1615 gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
1617 if (s->ss32 && !s->addseg)
1618 gen_op_movl_ESP_A0();
1620 gen_stack_update(s, (-2) << s->dflag);
1623 /* two step pop is necessary for precise exceptions */
1624 static void gen_pop_T0(DisasContext *s)
1626 gen_op_movl_A0_reg[R_ESP]();
1629 gen_op_addl_A0_SS();
1631 gen_op_andl_A0_ffff();
1632 gen_op_addl_A0_SS();
1634 gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
1637 static void gen_pop_update(DisasContext *s)
1639 gen_stack_update(s, 2 << s->dflag);
1642 static void gen_stack_A0(DisasContext *s)
1644 gen_op_movl_A0_ESP();
1646 gen_op_andl_A0_ffff();
1647 gen_op_movl_T1_A0();
1649 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1652 /* NOTE: wrap around in 16 bit not fully handled */
1653 static void gen_pusha(DisasContext *s)
1656 gen_op_movl_A0_ESP();
1657 gen_op_addl_A0_im(-16 << s->dflag);
1659 gen_op_andl_A0_ffff();
1660 gen_op_movl_T1_A0();
1662 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1663 for(i = 0;i < 8; i++) {
1664 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1665 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1666 gen_op_addl_A0_im(2 << s->dflag);
1668 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1671 /* NOTE: wrap around in 16 bit not fully handled */
1672 static void gen_popa(DisasContext *s)
1675 gen_op_movl_A0_ESP();
1677 gen_op_andl_A0_ffff();
1678 gen_op_movl_T1_A0();
1679 gen_op_addl_T1_im(16 << s->dflag);
1681 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1682 for(i = 0;i < 8; i++) {
1683 /* ESP is not reloaded */
1685 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1686 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1688 gen_op_addl_A0_im(2 << s->dflag);
1690 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1693 /* NOTE: wrap around in 16 bit not fully handled */
1694 /* XXX: check this */
1695 static void gen_enter(DisasContext *s, int esp_addend, int level)
1697 int ot, level1, addend, opsize;
1699 ot = s->dflag + OT_WORD;
1702 opsize = 2 << s->dflag;
1704 gen_op_movl_A0_ESP();
1705 gen_op_addl_A0_im(-opsize);
1707 gen_op_andl_A0_ffff();
1708 gen_op_movl_T1_A0();
1710 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1712 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1713 gen_op_st_T0_A0[ot + s->mem_index]();
1716 gen_op_addl_A0_im(-opsize);
1717 gen_op_addl_T0_im(-opsize);
1718 gen_op_st_T0_A0[ot + s->mem_index]();
1720 gen_op_addl_A0_im(-opsize);
1721 gen_op_st_T1_A0[ot + s->mem_index]();
1723 gen_op_mov_reg_T1[ot][R_EBP]();
1724 addend = -esp_addend;
1726 addend -= opsize * (level1 + 1);
1727 gen_op_addl_T1_im(addend);
1728 gen_op_mov_reg_T1[ot][R_ESP]();
1731 static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1733 if (s->cc_op != CC_OP_DYNAMIC)
1734 gen_op_set_cc_op(s->cc_op);
1735 gen_op_jmp_im(cur_eip);
1736 gen_op_raise_exception(trapno);
1740 /* an interrupt is different from an exception because of the
1741 priviledge checks */
1742 static void gen_interrupt(DisasContext *s, int intno,
1743 unsigned int cur_eip, unsigned int next_eip)
1745 if (s->cc_op != CC_OP_DYNAMIC)
1746 gen_op_set_cc_op(s->cc_op);
1747 gen_op_jmp_im(cur_eip);
1748 gen_op_raise_interrupt(intno, next_eip);
1752 static void gen_debug(DisasContext *s, unsigned int cur_eip)
1754 if (s->cc_op != CC_OP_DYNAMIC)
1755 gen_op_set_cc_op(s->cc_op);
1756 gen_op_jmp_im(cur_eip);
1761 /* generate a generic end of block. Trace exception is also generated
1763 static void gen_eob(DisasContext *s)
1765 if (s->cc_op != CC_OP_DYNAMIC)
1766 gen_op_set_cc_op(s->cc_op);
1767 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
1768 gen_op_reset_inhibit_irq();
1770 if (s->singlestep_enabled) {
1773 gen_op_raise_exception(EXCP01_SSTP);
1781 /* generate a jump to eip. No segment change must happen before as a
1782 direct call to the next block may occur */
1783 static void gen_jmp(DisasContext *s, unsigned int eip)
1785 TranslationBlock *tb = s->tb;
1788 if (s->cc_op != CC_OP_DYNAMIC)
1789 gen_op_set_cc_op(s->cc_op);
1790 gen_op_jmp((long)tb, eip);
1798 /* convert one instruction. s->is_jmp is set if the translation must
1799 be stopped. Return the next pc value */
1800 static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1802 int b, prefixes, aflag, dflag;
1804 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1805 unsigned int next_eip;
1813 b = ldub_code(s->pc);
1815 /* check prefixes */
1818 prefixes |= PREFIX_REPZ;
1821 prefixes |= PREFIX_REPNZ;
1824 prefixes |= PREFIX_LOCK;
1845 prefixes |= PREFIX_DATA;
1848 prefixes |= PREFIX_ADR;
1852 if (prefixes & PREFIX_DATA)
1854 if (prefixes & PREFIX_ADR)
1857 s->prefix = prefixes;
1861 /* lock generation */
1862 if (prefixes & PREFIX_LOCK)
1865 /* now check op code */
1869 /**************************/
1870 /* extended op code */
1871 b = ldub_code(s->pc++) | 0x100;
1874 /**************************/
1892 ot = dflag ? OT_LONG : OT_WORD;
1895 case 0: /* OP Ev, Gv */
1896 modrm = ldub_code(s->pc++);
1897 reg = ((modrm >> 3) & 7);
1898 mod = (modrm >> 6) & 3;
1901 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1903 } else if (op == OP_XORL && rm == reg) {
1905 /* xor reg, reg optimisation */
1907 s->cc_op = CC_OP_LOGICB + ot;
1908 gen_op_mov_reg_T0[ot][reg]();
1909 gen_op_update1_cc();
1914 gen_op_mov_TN_reg[ot][1][reg]();
1915 gen_op(s, op, ot, opreg);
1917 case 1: /* OP Gv, Ev */
1918 modrm = ldub_code(s->pc++);
1919 mod = (modrm >> 6) & 3;
1920 reg = ((modrm >> 3) & 7);
1923 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1924 gen_op_ld_T1_A0[ot + s->mem_index]();
1925 } else if (op == OP_XORL && rm == reg) {
1928 gen_op_mov_TN_reg[ot][1][rm]();
1930 gen_op(s, op, ot, reg);
1932 case 2: /* OP A, Iv */
1933 val = insn_get(s, ot);
1934 gen_op_movl_T1_im(val);
1935 gen_op(s, op, ot, OR_EAX);
1941 case 0x80: /* GRP1 */
1951 ot = dflag ? OT_LONG : OT_WORD;
1953 modrm = ldub_code(s->pc++);
1954 mod = (modrm >> 6) & 3;
1956 op = (modrm >> 3) & 7;
1959 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
1962 opreg = rm + OR_EAX;
1970 val = insn_get(s, ot);
1973 val = (int8_t)insn_get(s, OT_BYTE);
1976 gen_op_movl_T1_im(val);
1977 gen_op(s, op, ot, opreg);
1981 /**************************/
1982 /* inc, dec, and other misc arith */
1983 case 0x40 ... 0x47: /* inc Gv */
1984 ot = dflag ? OT_LONG : OT_WORD;
1985 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1987 case 0x48 ... 0x4f: /* dec Gv */
1988 ot = dflag ? OT_LONG : OT_WORD;
1989 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1991 case 0xf6: /* GRP3 */
1996 ot = dflag ? OT_LONG : OT_WORD;
1998 modrm = ldub_code(s->pc++);
1999 mod = (modrm >> 6) & 3;
2001 op = (modrm >> 3) & 7;
2003 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2004 gen_op_ld_T0_A0[ot + s->mem_index]();
2006 gen_op_mov_TN_reg[ot][0][rm]();
2011 val = insn_get(s, ot);
2012 gen_op_movl_T1_im(val);
2013 gen_op_testl_T0_T1_cc();
2014 s->cc_op = CC_OP_LOGICB + ot;
2019 gen_op_st_T0_A0[ot + s->mem_index]();
2021 gen_op_mov_reg_T0[ot][rm]();
2027 gen_op_st_T0_A0[ot + s->mem_index]();
2029 gen_op_mov_reg_T0[ot][rm]();
2031 gen_op_update_neg_cc();
2032 s->cc_op = CC_OP_SUBB + ot;
2037 gen_op_mulb_AL_T0();
2038 s->cc_op = CC_OP_MULB;
2041 gen_op_mulw_AX_T0();
2042 s->cc_op = CC_OP_MULW;
2046 gen_op_mull_EAX_T0();
2047 s->cc_op = CC_OP_MULL;
2054 gen_op_imulb_AL_T0();
2055 s->cc_op = CC_OP_MULB;
2058 gen_op_imulw_AX_T0();
2059 s->cc_op = CC_OP_MULW;
2063 gen_op_imull_EAX_T0();
2064 s->cc_op = CC_OP_MULL;
2071 gen_op_divb_AL_T0(pc_start - s->cs_base);
2074 gen_op_divw_AX_T0(pc_start - s->cs_base);
2078 gen_op_divl_EAX_T0(pc_start - s->cs_base);
2085 gen_op_idivb_AL_T0(pc_start - s->cs_base);
2088 gen_op_idivw_AX_T0(pc_start - s->cs_base);
2092 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2101 case 0xfe: /* GRP4 */
2102 case 0xff: /* GRP5 */
2106 ot = dflag ? OT_LONG : OT_WORD;
2108 modrm = ldub_code(s->pc++);
2109 mod = (modrm >> 6) & 3;
2111 op = (modrm >> 3) & 7;
2112 if (op >= 2 && b == 0xfe) {
2116 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2117 if (op >= 2 && op != 3 && op != 5)
2118 gen_op_ld_T0_A0[ot + s->mem_index]();
2120 gen_op_mov_TN_reg[ot][0][rm]();
2124 case 0: /* inc Ev */
2129 gen_inc(s, ot, opreg, 1);
2131 case 1: /* dec Ev */
2136 gen_inc(s, ot, opreg, -1);
2138 case 2: /* call Ev */
2139 /* XXX: optimize if memory (no 'and' is necessary) */
2141 gen_op_andl_T0_ffff();
2142 next_eip = s->pc - s->cs_base;
2143 gen_op_movl_T1_im(next_eip);
2148 case 3: /* lcall Ev */
2149 gen_op_ld_T1_A0[ot + s->mem_index]();
2150 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2151 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2153 if (s->pe && !s->vm86) {
2154 if (s->cc_op != CC_OP_DYNAMIC)
2155 gen_op_set_cc_op(s->cc_op);
2156 gen_op_jmp_im(pc_start - s->cs_base);
2157 gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2159 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2163 case 4: /* jmp Ev */
2165 gen_op_andl_T0_ffff();
2169 case 5: /* ljmp Ev */
2170 gen_op_ld_T1_A0[ot + s->mem_index]();
2171 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2172 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2174 if (s->pe && !s->vm86) {
2175 if (s->cc_op != CC_OP_DYNAMIC)
2176 gen_op_set_cc_op(s->cc_op);
2177 gen_op_jmp_im(pc_start - s->cs_base);
2178 gen_op_ljmp_protected_T0_T1(s->pc - s->cs_base);
2180 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2181 gen_op_movl_T0_T1();
2186 case 6: /* push Ev */
2194 case 0x84: /* test Ev, Gv */
2199 ot = dflag ? OT_LONG : OT_WORD;
2201 modrm = ldub_code(s->pc++);
2202 mod = (modrm >> 6) & 3;
2204 reg = (modrm >> 3) & 7;
2206 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2207 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2208 gen_op_testl_T0_T1_cc();
2209 s->cc_op = CC_OP_LOGICB + ot;
2212 case 0xa8: /* test eAX, Iv */
2217 ot = dflag ? OT_LONG : OT_WORD;
2218 val = insn_get(s, ot);
2220 gen_op_mov_TN_reg[ot][0][OR_EAX]();
2221 gen_op_movl_T1_im(val);
2222 gen_op_testl_T0_T1_cc();
2223 s->cc_op = CC_OP_LOGICB + ot;
2226 case 0x98: /* CWDE/CBW */
2228 gen_op_movswl_EAX_AX();
2230 gen_op_movsbw_AX_AL();
2232 case 0x99: /* CDQ/CWD */
2234 gen_op_movslq_EDX_EAX();
2236 gen_op_movswl_DX_AX();
2238 case 0x1af: /* imul Gv, Ev */
2239 case 0x69: /* imul Gv, Ev, I */
2241 ot = dflag ? OT_LONG : OT_WORD;
2242 modrm = ldub_code(s->pc++);
2243 reg = ((modrm >> 3) & 7) + OR_EAX;
2244 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2246 val = insn_get(s, ot);
2247 gen_op_movl_T1_im(val);
2248 } else if (b == 0x6b) {
2249 val = (int8_t)insn_get(s, OT_BYTE);
2250 gen_op_movl_T1_im(val);
2252 gen_op_mov_TN_reg[ot][1][reg]();
2255 if (ot == OT_LONG) {
2256 gen_op_imull_T0_T1();
2258 gen_op_imulw_T0_T1();
2260 gen_op_mov_reg_T0[ot][reg]();
2261 s->cc_op = CC_OP_MULB + ot;
2264 case 0x1c1: /* xadd Ev, Gv */
2268 ot = dflag ? OT_LONG : OT_WORD;
2269 modrm = ldub_code(s->pc++);
2270 reg = (modrm >> 3) & 7;
2271 mod = (modrm >> 6) & 3;
2274 gen_op_mov_TN_reg[ot][0][reg]();
2275 gen_op_mov_TN_reg[ot][1][rm]();
2276 gen_op_addl_T0_T1();
2277 gen_op_mov_reg_T1[ot][reg]();
2278 gen_op_mov_reg_T0[ot][rm]();
2280 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2281 gen_op_mov_TN_reg[ot][0][reg]();
2282 gen_op_ld_T1_A0[ot + s->mem_index]();
2283 gen_op_addl_T0_T1();
2284 gen_op_st_T0_A0[ot + s->mem_index]();
2285 gen_op_mov_reg_T1[ot][reg]();
2287 gen_op_update2_cc();
2288 s->cc_op = CC_OP_ADDB + ot;
2291 case 0x1b1: /* cmpxchg Ev, Gv */
2295 ot = dflag ? OT_LONG : OT_WORD;
2296 modrm = ldub_code(s->pc++);
2297 reg = (modrm >> 3) & 7;
2298 mod = (modrm >> 6) & 3;
2299 gen_op_mov_TN_reg[ot][1][reg]();
2302 gen_op_mov_TN_reg[ot][0][rm]();
2303 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2304 gen_op_mov_reg_T0[ot][rm]();
2306 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2307 gen_op_ld_T0_A0[ot + s->mem_index]();
2308 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
2310 s->cc_op = CC_OP_SUBB + ot;
2312 case 0x1c7: /* cmpxchg8b */
2313 modrm = ldub_code(s->pc++);
2314 mod = (modrm >> 6) & 3;
2317 if (s->cc_op != CC_OP_DYNAMIC)
2318 gen_op_set_cc_op(s->cc_op);
2319 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2321 s->cc_op = CC_OP_EFLAGS;
2324 /**************************/
2326 case 0x50 ... 0x57: /* push */
2327 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2330 case 0x58 ... 0x5f: /* pop */
2331 ot = dflag ? OT_LONG : OT_WORD;
2333 /* NOTE: order is important for pop %sp */
2335 gen_op_mov_reg_T0[ot][b & 7]();
2337 case 0x60: /* pusha */
2340 case 0x61: /* popa */
2343 case 0x68: /* push Iv */
2345 ot = dflag ? OT_LONG : OT_WORD;
2347 val = insn_get(s, ot);
2349 val = (int8_t)insn_get(s, OT_BYTE);
2350 gen_op_movl_T0_im(val);
2353 case 0x8f: /* pop Ev */
2354 ot = dflag ? OT_LONG : OT_WORD;
2355 modrm = ldub_code(s->pc++);
2356 mod = (modrm >> 6) & 3;
2359 /* NOTE: order is important for pop %sp */
2362 gen_op_mov_reg_T0[ot][rm]();
2364 /* NOTE: order is important too for MMU exceptions */
2365 s->popl_esp_hack = 2 << dflag;
2366 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2367 s->popl_esp_hack = 0;
2371 case 0xc8: /* enter */
2374 val = lduw_code(s->pc);
2376 level = ldub_code(s->pc++);
2377 gen_enter(s, val, level);
2380 case 0xc9: /* leave */
2381 /* XXX: exception not precise (ESP is updated before potential exception) */
2383 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2384 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2386 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2387 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2390 ot = dflag ? OT_LONG : OT_WORD;
2391 gen_op_mov_reg_T0[ot][R_EBP]();
2394 case 0x06: /* push es */
2395 case 0x0e: /* push cs */
2396 case 0x16: /* push ss */
2397 case 0x1e: /* push ds */
2398 gen_op_movl_T0_seg(b >> 3);
2401 case 0x1a0: /* push fs */
2402 case 0x1a8: /* push gs */
2403 gen_op_movl_T0_seg((b >> 3) & 7);
2406 case 0x07: /* pop es */
2407 case 0x17: /* pop ss */
2408 case 0x1f: /* pop ds */
2411 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2414 /* if reg == SS, inhibit interrupts/trace. */
2415 /* If several instructions disable interrupts, only the
2417 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2418 gen_op_set_inhibit_irq();
2422 gen_op_jmp_im(s->pc - s->cs_base);
2426 case 0x1a1: /* pop fs */
2427 case 0x1a9: /* pop gs */
2429 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2432 gen_op_jmp_im(s->pc - s->cs_base);
2437 /**************************/
2440 case 0x89: /* mov Gv, Ev */
2444 ot = dflag ? OT_LONG : OT_WORD;
2445 modrm = ldub_code(s->pc++);
2446 reg = (modrm >> 3) & 7;
2448 /* generate a generic store */
2449 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2452 case 0xc7: /* mov Ev, Iv */
2456 ot = dflag ? OT_LONG : OT_WORD;
2457 modrm = ldub_code(s->pc++);
2458 mod = (modrm >> 6) & 3;
2460 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2461 val = insn_get(s, ot);
2462 gen_op_movl_T0_im(val);
2464 gen_op_st_T0_A0[ot + s->mem_index]();
2466 gen_op_mov_reg_T0[ot][modrm & 7]();
2469 case 0x8b: /* mov Ev, Gv */
2473 ot = dflag ? OT_LONG : OT_WORD;
2474 modrm = ldub_code(s->pc++);
2475 reg = (modrm >> 3) & 7;
2477 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2478 gen_op_mov_reg_T0[ot][reg]();
2480 case 0x8e: /* mov seg, Gv */
2481 modrm = ldub_code(s->pc++);
2482 reg = (modrm >> 3) & 7;
2483 if (reg >= 6 || reg == R_CS)
2485 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2486 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2488 /* if reg == SS, inhibit interrupts/trace */
2489 /* If several instructions disable interrupts, only the
2491 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2492 gen_op_set_inhibit_irq();
2496 gen_op_jmp_im(s->pc - s->cs_base);
2500 case 0x8c: /* mov Gv, seg */
2501 modrm = ldub_code(s->pc++);
2502 reg = (modrm >> 3) & 7;
2503 mod = (modrm >> 6) & 3;
2506 gen_op_movl_T0_seg(reg);
2508 if (mod == 3 && dflag)
2510 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2513 case 0x1b6: /* movzbS Gv, Eb */
2514 case 0x1b7: /* movzwS Gv, Eb */
2515 case 0x1be: /* movsbS Gv, Eb */
2516 case 0x1bf: /* movswS Gv, Eb */
2519 /* d_ot is the size of destination */
2520 d_ot = dflag + OT_WORD;
2521 /* ot is the size of source */
2522 ot = (b & 1) + OT_BYTE;
2523 modrm = ldub_code(s->pc++);
2524 reg = ((modrm >> 3) & 7) + OR_EAX;
2525 mod = (modrm >> 6) & 3;
2529 gen_op_mov_TN_reg[ot][0][rm]();
2530 switch(ot | (b & 8)) {
2532 gen_op_movzbl_T0_T0();
2535 gen_op_movsbl_T0_T0();
2538 gen_op_movzwl_T0_T0();
2542 gen_op_movswl_T0_T0();
2545 gen_op_mov_reg_T0[d_ot][reg]();
2547 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2549 gen_op_lds_T0_A0[ot + s->mem_index]();
2551 gen_op_ldu_T0_A0[ot + s->mem_index]();
2553 gen_op_mov_reg_T0[d_ot][reg]();
2558 case 0x8d: /* lea */
2559 ot = dflag ? OT_LONG : OT_WORD;
2560 modrm = ldub_code(s->pc++);
2561 mod = (modrm >> 6) & 3;
2564 reg = (modrm >> 3) & 7;
2565 /* we must ensure that no segment is added */
2569 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2571 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2574 case 0xa0: /* mov EAX, Ov */
2576 case 0xa2: /* mov Ov, EAX */
2581 ot = dflag ? OT_LONG : OT_WORD;
2583 offset_addr = insn_get(s, OT_LONG);
2585 offset_addr = insn_get(s, OT_WORD);
2586 gen_op_movl_A0_im(offset_addr);
2587 /* handle override */
2589 int override, must_add_seg;
2590 must_add_seg = s->addseg;
2591 if (s->override >= 0) {
2592 override = s->override;
2598 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2602 gen_op_ld_T0_A0[ot + s->mem_index]();
2603 gen_op_mov_reg_T0[ot][R_EAX]();
2605 gen_op_mov_TN_reg[ot][0][R_EAX]();
2606 gen_op_st_T0_A0[ot + s->mem_index]();
2609 case 0xd7: /* xlat */
2610 gen_op_movl_A0_reg[R_EBX]();
2611 gen_op_addl_A0_AL();
2613 gen_op_andl_A0_ffff();
2614 /* handle override */
2616 int override, must_add_seg;
2617 must_add_seg = s->addseg;
2619 if (s->override >= 0) {
2620 override = s->override;
2626 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2629 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2630 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2632 case 0xb0 ... 0xb7: /* mov R, Ib */
2633 val = insn_get(s, OT_BYTE);
2634 gen_op_movl_T0_im(val);
2635 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2637 case 0xb8 ... 0xbf: /* mov R, Iv */
2638 ot = dflag ? OT_LONG : OT_WORD;
2639 val = insn_get(s, ot);
2640 reg = OR_EAX + (b & 7);
2641 gen_op_movl_T0_im(val);
2642 gen_op_mov_reg_T0[ot][reg]();
2645 case 0x91 ... 0x97: /* xchg R, EAX */
2646 ot = dflag ? OT_LONG : OT_WORD;
2651 case 0x87: /* xchg Ev, Gv */
2655 ot = dflag ? OT_LONG : OT_WORD;
2656 modrm = ldub_code(s->pc++);
2657 reg = (modrm >> 3) & 7;
2658 mod = (modrm >> 6) & 3;
2662 gen_op_mov_TN_reg[ot][0][reg]();
2663 gen_op_mov_TN_reg[ot][1][rm]();
2664 gen_op_mov_reg_T0[ot][rm]();
2665 gen_op_mov_reg_T1[ot][reg]();
2667 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2668 gen_op_mov_TN_reg[ot][0][reg]();
2669 /* for xchg, lock is implicit */
2670 if (!(prefixes & PREFIX_LOCK))
2672 gen_op_ld_T1_A0[ot + s->mem_index]();
2673 gen_op_st_T0_A0[ot + s->mem_index]();
2674 if (!(prefixes & PREFIX_LOCK))
2676 gen_op_mov_reg_T1[ot][reg]();
2679 case 0xc4: /* les Gv */
2682 case 0xc5: /* lds Gv */
2685 case 0x1b2: /* lss Gv */
2688 case 0x1b4: /* lfs Gv */
2691 case 0x1b5: /* lgs Gv */
2694 ot = dflag ? OT_LONG : OT_WORD;
2695 modrm = ldub_code(s->pc++);
2696 reg = (modrm >> 3) & 7;
2697 mod = (modrm >> 6) & 3;
2700 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2701 gen_op_ld_T1_A0[ot + s->mem_index]();
2702 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2703 /* load the segment first to handle exceptions properly */
2704 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2705 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2706 /* then put the data */
2707 gen_op_mov_reg_T1[ot][reg]();
2709 gen_op_jmp_im(s->pc - s->cs_base);
2714 /************************/
2725 ot = dflag ? OT_LONG : OT_WORD;
2727 modrm = ldub_code(s->pc++);
2728 mod = (modrm >> 6) & 3;
2730 op = (modrm >> 3) & 7;
2733 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2736 opreg = rm + OR_EAX;
2741 gen_shift(s, op, ot, opreg, OR_ECX);
2744 shift = ldub_code(s->pc++);
2746 gen_shifti(s, op, ot, opreg, shift);
2761 case 0x1a4: /* shld imm */
2765 case 0x1a5: /* shld cl */
2769 case 0x1ac: /* shrd imm */
2773 case 0x1ad: /* shrd cl */
2777 ot = dflag ? OT_LONG : OT_WORD;
2778 modrm = ldub_code(s->pc++);
2779 mod = (modrm >> 6) & 3;
2781 reg = (modrm >> 3) & 7;
2784 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2785 gen_op_ld_T0_A0[ot + s->mem_index]();
2787 gen_op_mov_TN_reg[ot][0][rm]();
2789 gen_op_mov_TN_reg[ot][1][reg]();
2792 val = ldub_code(s->pc++);
2796 gen_op_shiftd_T0_T1_im_cc[ot][op](val);
2798 gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
2799 if (op == 0 && ot != OT_WORD)
2800 s->cc_op = CC_OP_SHLB + ot;
2802 s->cc_op = CC_OP_SARB + ot;
2805 if (s->cc_op != CC_OP_DYNAMIC)
2806 gen_op_set_cc_op(s->cc_op);
2808 gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
2810 gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
2811 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2814 gen_op_mov_reg_T0[ot][rm]();
2818 /************************/
2821 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
2822 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
2823 /* XXX: what to do if illegal op ? */
2824 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2827 modrm = ldub_code(s->pc++);
2828 mod = (modrm >> 6) & 3;
2830 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2833 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2835 case 0x00 ... 0x07: /* fxxxs */
2836 case 0x10 ... 0x17: /* fixxxl */
2837 case 0x20 ... 0x27: /* fxxxl */
2838 case 0x30 ... 0x37: /* fixxx */
2845 gen_op_flds_FT0_A0();
2848 gen_op_fildl_FT0_A0();
2851 gen_op_fldl_FT0_A0();
2855 gen_op_fild_FT0_A0();
2859 gen_op_fp_arith_ST0_FT0[op1]();
2861 /* fcomp needs pop */
2866 case 0x08: /* flds */
2867 case 0x0a: /* fsts */
2868 case 0x0b: /* fstps */
2869 case 0x18: /* fildl */
2870 case 0x1a: /* fistl */
2871 case 0x1b: /* fistpl */
2872 case 0x28: /* fldl */
2873 case 0x2a: /* fstl */
2874 case 0x2b: /* fstpl */
2875 case 0x38: /* filds */
2876 case 0x3a: /* fists */
2877 case 0x3b: /* fistps */
2883 gen_op_flds_ST0_A0();
2886 gen_op_fildl_ST0_A0();
2889 gen_op_fldl_ST0_A0();
2893 gen_op_fild_ST0_A0();
2900 gen_op_fsts_ST0_A0();
2903 gen_op_fistl_ST0_A0();
2906 gen_op_fstl_ST0_A0();
2910 gen_op_fist_ST0_A0();
2918 case 0x0c: /* fldenv mem */
2919 gen_op_fldenv_A0(s->dflag);
2921 case 0x0d: /* fldcw mem */
2924 case 0x0e: /* fnstenv mem */
2925 gen_op_fnstenv_A0(s->dflag);
2927 case 0x0f: /* fnstcw mem */
2930 case 0x1d: /* fldt mem */
2931 gen_op_fldt_ST0_A0();
2933 case 0x1f: /* fstpt mem */
2934 gen_op_fstt_ST0_A0();
2937 case 0x2c: /* frstor mem */
2938 gen_op_frstor_A0(s->dflag);
2940 case 0x2e: /* fnsave mem */
2941 gen_op_fnsave_A0(s->dflag);
2943 case 0x2f: /* fnstsw mem */
2946 case 0x3c: /* fbld */
2947 gen_op_fbld_ST0_A0();
2949 case 0x3e: /* fbstp */
2950 gen_op_fbst_ST0_A0();
2953 case 0x3d: /* fildll */
2954 gen_op_fildll_ST0_A0();
2956 case 0x3f: /* fistpll */
2957 gen_op_fistll_ST0_A0();
2964 /* register float ops */
2968 case 0x08: /* fld sti */
2970 gen_op_fmov_ST0_STN((opreg + 1) & 7);
2972 case 0x09: /* fxchg sti */
2973 gen_op_fxchg_ST0_STN(opreg);
2975 case 0x0a: /* grp d9/2 */
2978 /* check exceptions (FreeBSD FPU probe) */
2979 if (s->cc_op != CC_OP_DYNAMIC)
2980 gen_op_set_cc_op(s->cc_op);
2981 gen_op_jmp_im(pc_start - s->cs_base);
2988 case 0x0c: /* grp d9/4 */
2998 gen_op_fcom_ST0_FT0();
3007 case 0x0d: /* grp d9/5 */
3016 gen_op_fldl2t_ST0();
3020 gen_op_fldl2e_ST0();
3028 gen_op_fldlg2_ST0();
3032 gen_op_fldln2_ST0();
3043 case 0x0e: /* grp d9/6 */
3054 case 3: /* fpatan */
3057 case 4: /* fxtract */
3060 case 5: /* fprem1 */
3063 case 6: /* fdecstp */
3067 case 7: /* fincstp */
3072 case 0x0f: /* grp d9/7 */
3077 case 1: /* fyl2xp1 */
3083 case 3: /* fsincos */
3086 case 5: /* fscale */
3089 case 4: /* frndint */
3101 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3102 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3103 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3109 gen_op_fp_arith_STN_ST0[op1](opreg);
3113 gen_op_fmov_FT0_STN(opreg);
3114 gen_op_fp_arith_ST0_FT0[op1]();
3118 case 0x02: /* fcom */
3119 gen_op_fmov_FT0_STN(opreg);
3120 gen_op_fcom_ST0_FT0();
3122 case 0x03: /* fcomp */
3123 gen_op_fmov_FT0_STN(opreg);
3124 gen_op_fcom_ST0_FT0();
3127 case 0x15: /* da/5 */
3129 case 1: /* fucompp */
3130 gen_op_fmov_FT0_STN(1);
3131 gen_op_fucom_ST0_FT0();
3141 case 0: /* feni (287 only, just do nop here) */
3143 case 1: /* fdisi (287 only, just do nop here) */
3148 case 3: /* fninit */
3151 case 4: /* fsetpm (287 only, just do nop here) */
3157 case 0x1d: /* fucomi */
3158 if (s->cc_op != CC_OP_DYNAMIC)
3159 gen_op_set_cc_op(s->cc_op);
3160 gen_op_fmov_FT0_STN(opreg);
3161 gen_op_fucomi_ST0_FT0();
3162 s->cc_op = CC_OP_EFLAGS;
3164 case 0x1e: /* fcomi */
3165 if (s->cc_op != CC_OP_DYNAMIC)
3166 gen_op_set_cc_op(s->cc_op);
3167 gen_op_fmov_FT0_STN(opreg);
3168 gen_op_fcomi_ST0_FT0();
3169 s->cc_op = CC_OP_EFLAGS;
3171 case 0x28: /* ffree sti */
3172 gen_op_ffree_STN(opreg);
3174 case 0x2a: /* fst sti */
3175 gen_op_fmov_STN_ST0(opreg);
3177 case 0x2b: /* fstp sti */
3178 gen_op_fmov_STN_ST0(opreg);
3181 case 0x2c: /* fucom st(i) */
3182 gen_op_fmov_FT0_STN(opreg);
3183 gen_op_fucom_ST0_FT0();
3185 case 0x2d: /* fucomp st(i) */
3186 gen_op_fmov_FT0_STN(opreg);
3187 gen_op_fucom_ST0_FT0();
3190 case 0x33: /* de/3 */
3192 case 1: /* fcompp */
3193 gen_op_fmov_FT0_STN(1);
3194 gen_op_fcom_ST0_FT0();
3202 case 0x3c: /* df/4 */
3205 gen_op_fnstsw_EAX();
3211 case 0x3d: /* fucomip */
3212 if (s->cc_op != CC_OP_DYNAMIC)
3213 gen_op_set_cc_op(s->cc_op);
3214 gen_op_fmov_FT0_STN(opreg);
3215 gen_op_fucomi_ST0_FT0();
3217 s->cc_op = CC_OP_EFLAGS;
3219 case 0x3e: /* fcomip */
3220 if (s->cc_op != CC_OP_DYNAMIC)
3221 gen_op_set_cc_op(s->cc_op);
3222 gen_op_fmov_FT0_STN(opreg);
3223 gen_op_fcomi_ST0_FT0();
3225 s->cc_op = CC_OP_EFLAGS;
3227 case 0x10 ... 0x13: /* fcmovxx */
3231 const static uint8_t fcmov_cc[8] = {
3237 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
3239 gen_op_fcmov_ST0_STN_T0(opreg);
3246 #ifdef USE_CODE_COPY
3247 s->tb->cflags |= CF_TB_FP_USED;
3250 /************************/
3253 case 0xa4: /* movsS */
3258 ot = dflag ? OT_LONG : OT_WORD;
3260 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3261 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3267 case 0xaa: /* stosS */
3272 ot = dflag ? OT_LONG : OT_WORD;
3274 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3275 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3280 case 0xac: /* lodsS */
3285 ot = dflag ? OT_LONG : OT_WORD;
3286 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3287 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3292 case 0xae: /* scasS */
3297 ot = dflag ? OT_LONG : OT_WORD;
3298 if (prefixes & PREFIX_REPNZ) {
3299 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3300 } else if (prefixes & PREFIX_REPZ) {
3301 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3304 s->cc_op = CC_OP_SUBB + ot;
3308 case 0xa6: /* cmpsS */
3313 ot = dflag ? OT_LONG : OT_WORD;
3314 if (prefixes & PREFIX_REPNZ) {
3315 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3316 } else if (prefixes & PREFIX_REPZ) {
3317 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3320 s->cc_op = CC_OP_SUBB + ot;
3323 case 0x6c: /* insS */
3328 ot = dflag ? OT_LONG : OT_WORD;
3329 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3330 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3331 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3336 case 0x6e: /* outsS */
3341 ot = dflag ? OT_LONG : OT_WORD;
3342 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3343 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3344 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3350 /************************/
3357 ot = dflag ? OT_LONG : OT_WORD;
3358 val = ldub_code(s->pc++);
3359 gen_op_movl_T0_im(val);
3360 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3362 gen_op_mov_reg_T1[ot][R_EAX]();
3369 ot = dflag ? OT_LONG : OT_WORD;
3370 val = ldub_code(s->pc++);
3371 gen_op_movl_T0_im(val);
3372 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3373 gen_op_mov_TN_reg[ot][1][R_EAX]();
3381 ot = dflag ? OT_LONG : OT_WORD;
3382 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3383 gen_op_andl_T0_ffff();
3384 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3386 gen_op_mov_reg_T1[ot][R_EAX]();
3393 ot = dflag ? OT_LONG : OT_WORD;
3394 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3395 gen_op_andl_T0_ffff();
3396 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3397 gen_op_mov_TN_reg[ot][1][R_EAX]();
3401 /************************/
3403 case 0xc2: /* ret im */
3404 val = ldsw_code(s->pc);
3407 gen_stack_update(s, val + (2 << s->dflag));
3409 gen_op_andl_T0_ffff();
3413 case 0xc3: /* ret */
3417 gen_op_andl_T0_ffff();
3421 case 0xca: /* lret im */
3422 val = ldsw_code(s->pc);
3425 if (s->pe && !s->vm86) {
3426 if (s->cc_op != CC_OP_DYNAMIC)
3427 gen_op_set_cc_op(s->cc_op);
3428 gen_op_jmp_im(pc_start - s->cs_base);
3429 gen_op_lret_protected(s->dflag, val);
3433 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3435 gen_op_andl_T0_ffff();
3436 /* NOTE: keeping EIP updated is not a problem in case of
3440 gen_op_addl_A0_im(2 << s->dflag);
3441 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3442 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3443 /* add stack offset */
3444 gen_stack_update(s, val + (4 << s->dflag));
3448 case 0xcb: /* lret */
3451 case 0xcf: /* iret */
3454 gen_op_iret_real(s->dflag);
3455 s->cc_op = CC_OP_EFLAGS;
3456 } else if (s->vm86) {
3458 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3460 gen_op_iret_real(s->dflag);
3461 s->cc_op = CC_OP_EFLAGS;
3464 if (s->cc_op != CC_OP_DYNAMIC)
3465 gen_op_set_cc_op(s->cc_op);
3466 gen_op_jmp_im(pc_start - s->cs_base);
3467 gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
3468 s->cc_op = CC_OP_EFLAGS;
3472 case 0xe8: /* call im */
3474 unsigned int next_eip;
3475 ot = dflag ? OT_LONG : OT_WORD;
3476 val = insn_get(s, ot);
3477 next_eip = s->pc - s->cs_base;
3481 gen_op_movl_T0_im(next_eip);
3486 case 0x9a: /* lcall im */
3488 unsigned int selector, offset;
3490 ot = dflag ? OT_LONG : OT_WORD;
3491 offset = insn_get(s, ot);
3492 selector = insn_get(s, OT_WORD);
3494 gen_op_movl_T0_im(selector);
3495 gen_op_movl_T1_im(offset);
3498 case 0xe9: /* jmp */
3499 ot = dflag ? OT_LONG : OT_WORD;
3500 val = insn_get(s, ot);
3501 val += s->pc - s->cs_base;
3506 case 0xea: /* ljmp im */
3508 unsigned int selector, offset;
3510 ot = dflag ? OT_LONG : OT_WORD;
3511 offset = insn_get(s, ot);
3512 selector = insn_get(s, OT_WORD);
3514 gen_op_movl_T0_im(selector);
3515 gen_op_movl_T1_im(offset);
3518 case 0xeb: /* jmp Jb */
3519 val = (int8_t)insn_get(s, OT_BYTE);
3520 val += s->pc - s->cs_base;
3525 case 0x70 ... 0x7f: /* jcc Jb */
3526 val = (int8_t)insn_get(s, OT_BYTE);
3528 case 0x180 ... 0x18f: /* jcc Jv */
3530 val = insn_get(s, OT_LONG);
3532 val = (int16_t)insn_get(s, OT_WORD);
3535 next_eip = s->pc - s->cs_base;
3539 gen_jcc(s, b, val, next_eip);
3542 case 0x190 ... 0x19f: /* setcc Gv */
3543 modrm = ldub_code(s->pc++);
3545 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3547 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3548 ot = dflag ? OT_LONG : OT_WORD;
3549 modrm = ldub_code(s->pc++);
3550 reg = (modrm >> 3) & 7;
3551 mod = (modrm >> 6) & 3;
3554 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3555 gen_op_ld_T1_A0[ot + s->mem_index]();
3558 gen_op_mov_TN_reg[ot][1][rm]();
3560 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3563 /************************/
3565 case 0x9c: /* pushf */
3566 if (s->vm86 && s->iopl != 3) {
3567 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3569 if (s->cc_op != CC_OP_DYNAMIC)
3570 gen_op_set_cc_op(s->cc_op);
3571 gen_op_movl_T0_eflags();
3575 case 0x9d: /* popf */
3576 if (s->vm86 && s->iopl != 3) {
3577 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3582 gen_op_movl_eflags_T0_cpl0();
3584 gen_op_movw_eflags_T0_cpl0();
3587 if (s->cpl <= s->iopl) {
3589 gen_op_movl_eflags_T0_io();
3591 gen_op_movw_eflags_T0_io();
3595 gen_op_movl_eflags_T0();
3597 gen_op_movw_eflags_T0();
3602 s->cc_op = CC_OP_EFLAGS;
3603 /* abort translation because TF flag may change */
3604 gen_op_jmp_im(s->pc - s->cs_base);
3608 case 0x9e: /* sahf */
3609 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3610 if (s->cc_op != CC_OP_DYNAMIC)
3611 gen_op_set_cc_op(s->cc_op);
3612 gen_op_movb_eflags_T0();
3613 s->cc_op = CC_OP_EFLAGS;
3615 case 0x9f: /* lahf */
3616 if (s->cc_op != CC_OP_DYNAMIC)
3617 gen_op_set_cc_op(s->cc_op);
3618 gen_op_movl_T0_eflags();
3619 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3621 case 0xf5: /* cmc */
3622 if (s->cc_op != CC_OP_DYNAMIC)
3623 gen_op_set_cc_op(s->cc_op);
3625 s->cc_op = CC_OP_EFLAGS;
3627 case 0xf8: /* clc */
3628 if (s->cc_op != CC_OP_DYNAMIC)
3629 gen_op_set_cc_op(s->cc_op);
3631 s->cc_op = CC_OP_EFLAGS;
3633 case 0xf9: /* stc */
3634 if (s->cc_op != CC_OP_DYNAMIC)
3635 gen_op_set_cc_op(s->cc_op);
3637 s->cc_op = CC_OP_EFLAGS;
3639 case 0xfc: /* cld */
3642 case 0xfd: /* std */
3646 /************************/
3647 /* bit operations */
3648 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3649 ot = dflag ? OT_LONG : OT_WORD;
3650 modrm = ldub_code(s->pc++);
3651 op = (modrm >> 3) & 7;
3652 mod = (modrm >> 6) & 3;
3655 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3656 gen_op_ld_T0_A0[ot + s->mem_index]();
3658 gen_op_mov_TN_reg[ot][0][rm]();
3661 val = ldub_code(s->pc++);
3662 gen_op_movl_T1_im(val);
3666 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3667 s->cc_op = CC_OP_SARB + ot;
3670 gen_op_st_T0_A0[ot + s->mem_index]();
3672 gen_op_mov_reg_T0[ot][rm]();
3673 gen_op_update_bt_cc();
3676 case 0x1a3: /* bt Gv, Ev */
3679 case 0x1ab: /* bts */
3682 case 0x1b3: /* btr */
3685 case 0x1bb: /* btc */
3688 ot = dflag ? OT_LONG : OT_WORD;
3689 modrm = ldub_code(s->pc++);
3690 reg = (modrm >> 3) & 7;
3691 mod = (modrm >> 6) & 3;
3693 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3695 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3696 /* specific case: we need to add a displacement */
3698 gen_op_add_bitw_A0_T1();
3700 gen_op_add_bitl_A0_T1();
3701 gen_op_ld_T0_A0[ot + s->mem_index]();
3703 gen_op_mov_TN_reg[ot][0][rm]();
3705 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3706 s->cc_op = CC_OP_SARB + ot;
3709 gen_op_st_T0_A0[ot + s->mem_index]();
3711 gen_op_mov_reg_T0[ot][rm]();
3712 gen_op_update_bt_cc();
3715 case 0x1bc: /* bsf */
3716 case 0x1bd: /* bsr */
3717 ot = dflag ? OT_LONG : OT_WORD;
3718 modrm = ldub_code(s->pc++);
3719 reg = (modrm >> 3) & 7;
3720 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3721 /* NOTE: in order to handle the 0 case, we must load the
3722 result. It could be optimized with a generated jump */
3723 gen_op_mov_TN_reg[ot][1][reg]();
3724 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3725 gen_op_mov_reg_T1[ot][reg]();
3726 s->cc_op = CC_OP_LOGICB + ot;
3728 /************************/
3730 case 0x27: /* daa */
3731 if (s->cc_op != CC_OP_DYNAMIC)
3732 gen_op_set_cc_op(s->cc_op);
3734 s->cc_op = CC_OP_EFLAGS;
3736 case 0x2f: /* das */
3737 if (s->cc_op != CC_OP_DYNAMIC)
3738 gen_op_set_cc_op(s->cc_op);
3740 s->cc_op = CC_OP_EFLAGS;
3742 case 0x37: /* aaa */
3743 if (s->cc_op != CC_OP_DYNAMIC)
3744 gen_op_set_cc_op(s->cc_op);
3746 s->cc_op = CC_OP_EFLAGS;
3748 case 0x3f: /* aas */
3749 if (s->cc_op != CC_OP_DYNAMIC)
3750 gen_op_set_cc_op(s->cc_op);
3752 s->cc_op = CC_OP_EFLAGS;
3754 case 0xd4: /* aam */
3755 val = ldub_code(s->pc++);
3757 s->cc_op = CC_OP_LOGICB;
3759 case 0xd5: /* aad */
3760 val = ldub_code(s->pc++);
3762 s->cc_op = CC_OP_LOGICB;
3764 /************************/
3766 case 0x90: /* nop */
3767 /* XXX: correct lock test for all insn */
3768 if (prefixes & PREFIX_LOCK)
3771 case 0x9b: /* fwait */
3772 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
3773 (HF_MP_MASK | HF_TS_MASK)) {
3774 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3776 if (s->cc_op != CC_OP_DYNAMIC)
3777 gen_op_set_cc_op(s->cc_op);
3778 gen_op_jmp_im(pc_start - s->cs_base);
3782 case 0xcc: /* int3 */
3783 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3785 case 0xcd: /* int N */
3786 val = ldub_code(s->pc++);
3787 if (s->vm86 && s->iopl != 3) {
3788 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3790 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3793 case 0xce: /* into */
3794 if (s->cc_op != CC_OP_DYNAMIC)
3795 gen_op_set_cc_op(s->cc_op);
3796 gen_op_into(s->pc - s->cs_base);
3798 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3799 gen_debug(s, pc_start - s->cs_base);
3801 case 0xfa: /* cli */
3803 if (s->cpl <= s->iopl) {
3806 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3812 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3816 case 0xfb: /* sti */
3818 if (s->cpl <= s->iopl) {
3821 /* interruptions are enabled only the first insn after sti */
3822 /* If several instructions disable interrupts, only the
3824 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3825 gen_op_set_inhibit_irq();
3826 /* give a chance to handle pending irqs */
3827 gen_op_jmp_im(s->pc - s->cs_base);
3830 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3836 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3840 case 0x62: /* bound */
3841 ot = dflag ? OT_LONG : OT_WORD;
3842 modrm = ldub_code(s->pc++);
3843 reg = (modrm >> 3) & 7;
3844 mod = (modrm >> 6) & 3;
3847 gen_op_mov_TN_reg[ot][0][reg]();
3848 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3850 gen_op_boundw(pc_start - s->cs_base);
3852 gen_op_boundl(pc_start - s->cs_base);
3854 case 0x1c8 ... 0x1cf: /* bswap reg */
3856 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3858 gen_op_mov_reg_T0[OT_LONG][reg]();
3860 case 0xd6: /* salc */
3861 if (s->cc_op != CC_OP_DYNAMIC)
3862 gen_op_set_cc_op(s->cc_op);
3865 case 0xe0: /* loopnz */
3866 case 0xe1: /* loopz */
3867 if (s->cc_op != CC_OP_DYNAMIC)
3868 gen_op_set_cc_op(s->cc_op);
3870 case 0xe2: /* loop */
3871 case 0xe3: /* jecxz */
3872 val = (int8_t)insn_get(s, OT_BYTE);
3873 next_eip = s->pc - s->cs_base;
3877 gen_op_loop[s->aflag][b & 3](val, next_eip);
3880 case 0x130: /* wrmsr */
3881 case 0x132: /* rdmsr */
3883 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3891 case 0x131: /* rdtsc */
3894 case 0x134: /* sysenter */
3896 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3898 if (s->cc_op != CC_OP_DYNAMIC) {
3899 gen_op_set_cc_op(s->cc_op);
3900 s->cc_op = CC_OP_DYNAMIC;
3902 gen_op_jmp_im(pc_start - s->cs_base);
3907 case 0x135: /* sysexit */
3909 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3911 if (s->cc_op != CC_OP_DYNAMIC) {
3912 gen_op_set_cc_op(s->cc_op);
3913 s->cc_op = CC_OP_DYNAMIC;
3915 gen_op_jmp_im(pc_start - s->cs_base);
3920 case 0x1a2: /* cpuid */
3923 case 0xf4: /* hlt */
3925 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3927 if (s->cc_op != CC_OP_DYNAMIC)
3928 gen_op_set_cc_op(s->cc_op);
3929 gen_op_jmp_im(s->pc - s->cs_base);
3935 modrm = ldub_code(s->pc++);
3936 mod = (modrm >> 6) & 3;
3937 op = (modrm >> 3) & 7;
3940 if (!s->pe || s->vm86)
3942 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3946 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3949 if (!s->pe || s->vm86)
3952 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3954 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3955 gen_op_jmp_im(pc_start - s->cs_base);
3960 if (!s->pe || s->vm86)
3962 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3966 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3969 if (!s->pe || s->vm86)
3972 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3974 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3975 gen_op_jmp_im(pc_start - s->cs_base);
3981 if (!s->pe || s->vm86)
3983 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3984 if (s->cc_op != CC_OP_DYNAMIC)
3985 gen_op_set_cc_op(s->cc_op);
3990 s->cc_op = CC_OP_EFLAGS;
3997 modrm = ldub_code(s->pc++);
3998 mod = (modrm >> 6) & 3;
3999 op = (modrm >> 3) & 7;
4005 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4007 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
4009 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
4010 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
4011 gen_op_addl_A0_im(2);
4013 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
4015 gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
4017 gen_op_andl_T0_im(0xffffff);
4018 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
4025 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4027 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4028 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
4029 gen_op_addl_A0_im(2);
4030 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
4032 gen_op_andl_T0_im(0xffffff);
4034 gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
4035 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
4037 gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
4038 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
4043 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
4044 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
4048 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4050 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4052 gen_op_jmp_im(s->pc - s->cs_base);
4056 case 7: /* invlpg */
4058 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4062 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4064 gen_op_jmp_im(s->pc - s->cs_base);
4072 case 0x108: /* invd */
4073 case 0x109: /* wbinvd */
4075 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4080 case 0x63: /* arpl */
4081 if (!s->pe || s->vm86)
4083 ot = dflag ? OT_LONG : OT_WORD;
4084 modrm = ldub_code(s->pc++);
4085 reg = (modrm >> 3) & 7;
4086 mod = (modrm >> 6) & 3;
4089 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4090 gen_op_ld_T0_A0[ot + s->mem_index]();
4092 gen_op_mov_TN_reg[ot][0][rm]();
4094 if (s->cc_op != CC_OP_DYNAMIC)
4095 gen_op_set_cc_op(s->cc_op);
4097 s->cc_op = CC_OP_EFLAGS;
4099 gen_op_st_T0_A0[ot + s->mem_index]();
4101 gen_op_mov_reg_T0[ot][rm]();
4103 gen_op_arpl_update();
4105 case 0x102: /* lar */
4106 case 0x103: /* lsl */
4107 if (!s->pe || s->vm86)
4109 ot = dflag ? OT_LONG : OT_WORD;
4110 modrm = ldub_code(s->pc++);
4111 reg = (modrm >> 3) & 7;
4112 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4113 gen_op_mov_TN_reg[ot][1][reg]();
4114 if (s->cc_op != CC_OP_DYNAMIC)
4115 gen_op_set_cc_op(s->cc_op);
4120 s->cc_op = CC_OP_EFLAGS;
4121 gen_op_mov_reg_T1[ot][reg]();
4124 modrm = ldub_code(s->pc++);
4125 mod = (modrm >> 6) & 3;
4126 op = (modrm >> 3) & 7;
4128 case 0: /* prefetchnta */
4129 case 1: /* prefetchnt0 */
4130 case 2: /* prefetchnt0 */
4131 case 3: /* prefetchnt0 */
4134 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4135 /* nothing more to do */
4141 case 0x120: /* mov reg, crN */
4142 case 0x122: /* mov crN, reg */
4144 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4146 modrm = ldub_code(s->pc++);
4147 if ((modrm & 0xc0) != 0xc0)
4150 reg = (modrm >> 3) & 7;
4157 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4158 gen_op_movl_crN_T0(reg);
4159 gen_op_jmp_im(s->pc - s->cs_base);
4162 gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
4163 gen_op_mov_reg_T0[OT_LONG][rm]();
4171 case 0x121: /* mov reg, drN */
4172 case 0x123: /* mov drN, reg */
4174 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4176 modrm = ldub_code(s->pc++);
4177 if ((modrm & 0xc0) != 0xc0)
4180 reg = (modrm >> 3) & 7;
4181 /* XXX: do it dynamically with CR4.DE bit */
4182 if (reg == 4 || reg == 5)
4185 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4186 gen_op_movl_drN_T0(reg);
4187 gen_op_jmp_im(s->pc - s->cs_base);
4190 gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
4191 gen_op_mov_reg_T0[OT_LONG][rm]();
4195 case 0x106: /* clts */
4197 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4200 /* abort block because static cpu state changed */
4201 gen_op_jmp_im(s->pc - s->cs_base);
4208 /* lock generation */
4209 if (s->prefix & PREFIX_LOCK)
4213 if (s->prefix & PREFIX_LOCK)
4215 /* XXX: ensure that no lock was generated */
4216 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4220 #define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4221 #define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4223 /* flags read by an operation */
4224 static uint16_t opc_read_flags[NB_OPS] = {
4225 [INDEX_op_aas] = CC_A,
4226 [INDEX_op_aaa] = CC_A,
4227 [INDEX_op_das] = CC_A | CC_C,
4228 [INDEX_op_daa] = CC_A | CC_C,
4230 /* subtle: due to the incl/decl implementation, C is used */
4231 [INDEX_op_update_inc_cc] = CC_C,
4233 [INDEX_op_into] = CC_O,
4235 [INDEX_op_jb_subb] = CC_C,
4236 [INDEX_op_jb_subw] = CC_C,
4237 [INDEX_op_jb_subl] = CC_C,
4239 [INDEX_op_jz_subb] = CC_Z,
4240 [INDEX_op_jz_subw] = CC_Z,
4241 [INDEX_op_jz_subl] = CC_Z,
4243 [INDEX_op_jbe_subb] = CC_Z | CC_C,
4244 [INDEX_op_jbe_subw] = CC_Z | CC_C,
4245 [INDEX_op_jbe_subl] = CC_Z | CC_C,
4247 [INDEX_op_js_subb] = CC_S,
4248 [INDEX_op_js_subw] = CC_S,
4249 [INDEX_op_js_subl] = CC_S,
4251 [INDEX_op_jl_subb] = CC_O | CC_S,
4252 [INDEX_op_jl_subw] = CC_O | CC_S,
4253 [INDEX_op_jl_subl] = CC_O | CC_S,
4255 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4256 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4257 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4259 [INDEX_op_loopnzw] = CC_Z,
4260 [INDEX_op_loopnzl] = CC_Z,
4261 [INDEX_op_loopzw] = CC_Z,
4262 [INDEX_op_loopzl] = CC_Z,
4264 [INDEX_op_seto_T0_cc] = CC_O,
4265 [INDEX_op_setb_T0_cc] = CC_C,
4266 [INDEX_op_setz_T0_cc] = CC_Z,
4267 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4268 [INDEX_op_sets_T0_cc] = CC_S,
4269 [INDEX_op_setp_T0_cc] = CC_P,
4270 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4271 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4273 [INDEX_op_setb_T0_subb] = CC_C,
4274 [INDEX_op_setb_T0_subw] = CC_C,
4275 [INDEX_op_setb_T0_subl] = CC_C,
4277 [INDEX_op_setz_T0_subb] = CC_Z,
4278 [INDEX_op_setz_T0_subw] = CC_Z,
4279 [INDEX_op_setz_T0_subl] = CC_Z,
4281 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4282 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4283 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4285 [INDEX_op_sets_T0_subb] = CC_S,
4286 [INDEX_op_sets_T0_subw] = CC_S,
4287 [INDEX_op_sets_T0_subl] = CC_S,
4289 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4290 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4291 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4293 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4294 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4295 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4297 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4298 [INDEX_op_cmc] = CC_C,
4299 [INDEX_op_salc] = CC_C,
4301 /* needed for correct flag optimisation before string ops */
4302 [INDEX_op_jz_ecxw] = CC_OSZAPC,
4303 [INDEX_op_jz_ecxl] = CC_OSZAPC,
4304 [INDEX_op_jz_ecxw_im] = CC_OSZAPC,
4305 [INDEX_op_jz_ecxl_im] = CC_OSZAPC,
4307 #define DEF_READF(SUFFIX)\
4308 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4309 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4310 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4311 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4312 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4313 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4315 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4316 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4317 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
4318 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4319 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4320 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,
4325 #ifndef CONFIG_USER_ONLY
4331 /* flags written by an operation */
4332 static uint16_t opc_write_flags[NB_OPS] = {
4333 [INDEX_op_update2_cc] = CC_OSZAPC,
4334 [INDEX_op_update1_cc] = CC_OSZAPC,
4335 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4336 [INDEX_op_update_neg_cc] = CC_OSZAPC,
4337 /* subtle: due to the incl/decl implementation, C is used */
4338 [INDEX_op_update_inc_cc] = CC_OSZAPC,
4339 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4341 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4342 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4343 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4344 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4345 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4346 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4347 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4348 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4351 [INDEX_op_aam] = CC_OSZAPC,
4352 [INDEX_op_aad] = CC_OSZAPC,
4353 [INDEX_op_aas] = CC_OSZAPC,
4354 [INDEX_op_aaa] = CC_OSZAPC,
4355 [INDEX_op_das] = CC_OSZAPC,
4356 [INDEX_op_daa] = CC_OSZAPC,
4358 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4359 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4360 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4361 [INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
4362 [INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
4363 [INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
4364 [INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
4365 [INDEX_op_clc] = CC_C,
4366 [INDEX_op_stc] = CC_C,
4367 [INDEX_op_cmc] = CC_C,
4369 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4370 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4371 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4372 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4373 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4374 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4375 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4376 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4378 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4379 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4380 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4381 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4383 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4384 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4385 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4387 [INDEX_op_cmpxchg8b] = CC_Z,
4388 [INDEX_op_lar] = CC_Z,
4389 [INDEX_op_lsl] = CC_Z,
4390 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4391 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4393 #define DEF_WRITEF(SUFFIX)\
4394 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4395 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4396 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4397 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4398 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4399 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4401 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4402 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4403 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4404 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4405 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4406 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4408 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4409 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4410 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4411 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4412 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4413 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4415 [INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4416 [INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4417 [INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4419 [INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4420 [INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4421 [INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4423 [INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4424 [INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4425 [INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4427 [INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4428 [INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4429 [INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4430 [INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4432 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4433 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4434 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4435 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4437 [INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4438 [INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4439 [INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,
4444 #ifndef CONFIG_USER_ONLY
4450 /* simpler form of an operation if no flags need to be generated */
4451 static uint16_t opc_simpler[NB_OPS] = {
4452 [INDEX_op_update2_cc] = INDEX_op_nop,
4453 [INDEX_op_update1_cc] = INDEX_op_nop,
4454 [INDEX_op_update_neg_cc] = INDEX_op_nop,
4456 /* broken: CC_OP logic must be rewritten */
4457 [INDEX_op_update_inc_cc] = INDEX_op_nop,
4460 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4461 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4462 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4464 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4465 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4466 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4468 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4469 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4470 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4472 #define DEF_SIMPLER(SUFFIX)\
4473 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
4474 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
4475 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
4477 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
4478 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
4479 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,
4483 #ifndef CONFIG_USER_ONLY
4484 DEF_SIMPLER(_kernel)
4489 void optimize_flags_init(void)
4492 /* put default values in arrays */
4493 for(i = 0; i < NB_OPS; i++) {
4494 if (opc_simpler[i] == 0)
4499 /* CPU flags computation optimization: we move backward thru the
4500 generated code to see which flags are needed. The operation is
4501 modified if suitable */
4502 static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4505 int live_flags, write_flags, op;
4507 opc_ptr = opc_buf + opc_buf_len;
4508 /* live_flags contains the flags needed by the next instructions
4509 in the code. At the end of the bloc, we consider that all the
4511 live_flags = CC_OSZAPC;
4512 while (opc_ptr > opc_buf) {
4514 /* if none of the flags written by the instruction is used,
4515 then we can try to find a simpler instruction */
4516 write_flags = opc_write_flags[op];
4517 if ((live_flags & write_flags) == 0) {
4518 *opc_ptr = opc_simpler[op];
4520 /* compute the live flags before the instruction */
4521 live_flags &= ~write_flags;
4522 live_flags |= opc_read_flags[op];
4526 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4527 basic block 'tb'. If search_pc is TRUE, also generate PC
4528 information for each intermediate instruction. */
4529 static inline int gen_intermediate_code_internal(CPUState *env,
4530 TranslationBlock *tb,
4533 DisasContext dc1, *dc = &dc1;
4535 uint16_t *gen_opc_end;
4536 int flags, j, lj, cflags;
4540 /* generate intermediate code */
4541 pc_start = (uint8_t *)tb->pc;
4542 cs_base = (uint8_t *)tb->cs_base;
4544 cflags = tb->cflags;
4546 dc->pe = (flags >> HF_PE_SHIFT) & 1;
4547 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4548 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4549 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4551 dc->vm86 = (flags >> VM_SHIFT) & 1;
4552 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4553 dc->iopl = (flags >> IOPL_SHIFT) & 3;
4554 dc->tf = (flags >> TF_SHIFT) & 1;
4555 dc->singlestep_enabled = env->singlestep_enabled;
4556 dc->cc_op = CC_OP_DYNAMIC;
4557 dc->cs_base = cs_base;
4559 dc->popl_esp_hack = 0;
4560 /* select memory access functions */
4562 if (flags & HF_SOFTMMU_MASK) {
4569 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
4570 (flags & HF_INHIBIT_IRQ_MASK)
4571 #ifndef CONFIG_SOFTMMU
4572 || (flags & HF_SOFTMMU_MASK)
4576 /* check addseg logic */
4577 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
4578 printf("ERROR addseg\n");
4581 gen_opc_ptr = gen_opc_buf;
4582 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4583 gen_opparam_ptr = gen_opparam_buf;
4585 dc->is_jmp = DISAS_NEXT;
4590 if (env->nb_breakpoints > 0) {
4591 for(j = 0; j < env->nb_breakpoints; j++) {
4592 if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4593 gen_debug(dc, pc_ptr - dc->cs_base);
4599 j = gen_opc_ptr - gen_opc_buf;
4603 gen_opc_instr_start[lj++] = 0;
4605 gen_opc_pc[lj] = (uint32_t)pc_ptr;
4606 gen_opc_cc_op[lj] = dc->cc_op;
4607 gen_opc_instr_start[lj] = 1;
4609 pc_ptr = disas_insn(dc, pc_ptr);
4610 /* stop translation if indicated */
4613 /* if single step mode, we generate only one instruction and
4614 generate an exception */
4615 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
4616 the flag and abort the translation to give the irqs a
4617 change to be happen */
4618 if (dc->tf || dc->singlestep_enabled ||
4619 (flags & HF_INHIBIT_IRQ_MASK) ||
4620 (cflags & CF_SINGLE_INSN)) {
4621 gen_op_jmp_im(pc_ptr - dc->cs_base);
4625 /* if too long translation, stop generation too */
4626 if (gen_opc_ptr >= gen_opc_end ||
4627 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4628 gen_op_jmp_im(pc_ptr - dc->cs_base);
4633 *gen_opc_ptr = INDEX_op_end;
4634 /* we don't forget to fill the last values */
4636 j = gen_opc_ptr - gen_opc_buf;
4639 gen_opc_instr_start[lj++] = 0;
4643 if (loglevel & CPU_LOG_TB_CPU) {
4644 cpu_dump_state(env, logfile, X86_DUMP_CCOP);
4646 if (loglevel & CPU_LOG_TB_IN_ASM) {
4647 fprintf(logfile, "----------------\n");
4648 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4649 disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4650 fprintf(logfile, "\n");
4651 if (loglevel & CPU_LOG_TB_OP) {
4652 fprintf(logfile, "OP:\n");
4653 dump_ops(gen_opc_buf, gen_opparam_buf);
4654 fprintf(logfile, "\n");
4659 /* optimize flag computations */
4660 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4663 if (loglevel & CPU_LOG_TB_OP_OPT) {
4664 fprintf(logfile, "AFTER FLAGS OPT:\n");
4665 dump_ops(gen_opc_buf, gen_opparam_buf);
4666 fprintf(logfile, "\n");
4670 tb->size = pc_ptr - pc_start;
4674 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4676 return gen_intermediate_code_internal(env, tb, 0);
4679 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4681 return gen_intermediate_code_internal(env, tb, 1);