4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #define raise_exception_err(a, b)\
28 fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
29 (raise_exception_err)(a, b);\
33 const uint8_t parity_table[256] = {
34 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
35 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
36 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
37 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
38 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
39 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
40 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
41 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
42 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
43 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
44 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
45 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
46 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
55 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
56 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
57 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
58 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
59 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
61 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64 CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65 0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
69 const uint8_t rclw_table[32] = {
70 0, 1, 2, 3, 4, 5, 6, 7,
71 8, 9,10,11,12,13,14,15,
72 16, 0, 1, 2, 3, 4, 5, 6,
73 7, 8, 9,10,11,12,13,14,
77 const uint8_t rclb_table[32] = {
78 0, 1, 2, 3, 4, 5, 6, 7,
79 8, 0, 1, 2, 3, 4, 5, 6,
80 7, 8, 0, 1, 2, 3, 4, 5,
81 6, 7, 8, 0, 1, 2, 3, 4,
84 const CPU86_LDouble f15rk[7] =
86 0.00000000000000000000L,
87 1.00000000000000000000L,
88 3.14159265358979323851L, /*pi*/
89 0.30102999566398119523L, /*lg2*/
90 0.69314718055994530943L, /*ln2*/
91 1.44269504088896340739L, /*l2e*/
92 3.32192809488736234781L, /*l2t*/
97 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
101 spin_lock(&global_cpu_lock);
104 void cpu_unlock(void)
106 spin_unlock(&global_cpu_lock);
109 void cpu_loop_exit(void)
111 /* NOTE: the register at this point must be saved by hand because
112 longjmp restore them */
114 longjmp(env->jmp_env, 1);
117 /* return non zero if error */
118 static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
129 index = selector & ~7;
130 if ((index + 7) > dt->limit)
132 ptr = dt->base + index;
133 *e1_ptr = ldl_kernel(ptr);
134 *e2_ptr = ldl_kernel(ptr + 4);
138 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
141 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
142 if (e2 & DESC_G_MASK)
143 limit = (limit << 12) | 0xfff;
147 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
149 return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
152 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
154 sc->base = get_seg_base(e1, e2);
155 sc->limit = get_seg_limit(e1, e2);
159 /* init the segment cache in vm86 mode. */
160 static inline void load_seg_vm(int seg, int selector)
163 cpu_x86_load_seg_cache(env, seg, selector,
164 (selector << 4), 0xffff, 0);
167 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
168 uint32_t *esp_ptr, int dpl)
170 int type, index, shift;
175 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
176 for(i=0;i<env->tr.limit;i++) {
177 printf("%02x ", env->tr.base[i]);
178 if ((i & 7) == 7) printf("\n");
184 if (!(env->tr.flags & DESC_P_MASK))
185 cpu_abort(env, "invalid tss");
186 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
188 cpu_abort(env, "invalid tss type");
190 index = (dpl * 4 + 2) << shift;
191 if (index + (4 << shift) - 1 > env->tr.limit)
192 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
194 *esp_ptr = lduw_kernel(env->tr.base + index);
195 *ss_ptr = lduw_kernel(env->tr.base + index + 2);
197 *esp_ptr = ldl_kernel(env->tr.base + index);
198 *ss_ptr = lduw_kernel(env->tr.base + index + 4);
202 /* XXX: merge with load_seg() */
203 static void tss_load_seg(int seg_reg, int selector)
208 if ((selector & 0xfffc) != 0) {
209 if (load_segment(&e1, &e2, selector) != 0)
210 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
211 if (!(e2 & DESC_S_MASK))
212 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
214 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
215 cpl = env->hflags & HF_CPL_MASK;
216 if (seg_reg == R_CS) {
217 if (!(e2 & DESC_CS_MASK))
218 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
219 /* XXX: is it correct ? */
221 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
222 if ((e2 & DESC_C_MASK) && dpl > rpl)
223 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
224 } else if (seg_reg == R_SS) {
225 /* SS must be writable data */
226 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
227 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
228 if (dpl != cpl || dpl != rpl)
229 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231 /* not readable code */
232 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
233 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
234 /* if data or non conforming code, checks the rights */
235 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
236 if (dpl < cpl || dpl < rpl)
237 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
240 if (!(e2 & DESC_P_MASK))
241 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
242 cpu_x86_load_seg_cache(env, seg_reg, selector,
243 get_seg_base(e1, e2),
244 get_seg_limit(e1, e2),
247 if (seg_reg == R_SS || seg_reg == R_CS)
248 raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
252 #define SWITCH_TSS_JMP 0
253 #define SWITCH_TSS_IRET 1
254 #define SWITCH_TSS_CALL 2
256 /* XXX: restore CPU state in registers (PowerPC case) */
257 static void switch_tss(int tss_selector,
258 uint32_t e1, uint32_t e2, int source,
261 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
262 target_ulong tss_base;
263 uint32_t new_regs[8], new_segs[6];
264 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
265 uint32_t old_eflags, eflags_mask;
270 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
272 if (loglevel & CPU_LOG_PCALL)
273 fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
276 /* if task gate, we read the TSS segment and we load it */
278 if (!(e2 & DESC_P_MASK))
279 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
280 tss_selector = e1 >> 16;
281 if (tss_selector & 4)
282 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
283 if (load_segment(&e1, &e2, tss_selector) != 0)
284 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
285 if (e2 & DESC_S_MASK)
286 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
287 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
289 raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
292 if (!(e2 & DESC_P_MASK))
293 raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
299 tss_limit = get_seg_limit(e1, e2);
300 tss_base = get_seg_base(e1, e2);
301 if ((tss_selector & 4) != 0 ||
302 tss_limit < tss_limit_max)
303 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
304 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
306 old_tss_limit_max = 103;
308 old_tss_limit_max = 43;
310 /* read all the registers from the new TSS */
313 new_cr3 = ldl_kernel(tss_base + 0x1c);
314 new_eip = ldl_kernel(tss_base + 0x20);
315 new_eflags = ldl_kernel(tss_base + 0x24);
316 for(i = 0; i < 8; i++)
317 new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
318 for(i = 0; i < 6; i++)
319 new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
320 new_ldt = lduw_kernel(tss_base + 0x60);
321 new_trap = ldl_kernel(tss_base + 0x64);
325 new_eip = lduw_kernel(tss_base + 0x0e);
326 new_eflags = lduw_kernel(tss_base + 0x10);
327 for(i = 0; i < 8; i++)
328 new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;
329 for(i = 0; i < 4; i++)
330 new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
331 new_ldt = lduw_kernel(tss_base + 0x2a);
337 /* NOTE: we must avoid memory exceptions during the task switch,
338 so we make dummy accesses before */
339 /* XXX: it can still fail in some cases, so a bigger hack is
340 necessary to valid the TLB after having done the accesses */
342 v1 = ldub_kernel(env->tr.base);
343 v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
344 stb_kernel(env->tr.base, v1);
345 stb_kernel(env->tr.base + old_tss_limit_max, v2);
347 /* clear busy bit (it is restartable) */
348 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
351 ptr = env->gdt.base + (env->tr.selector & ~7);
352 e2 = ldl_kernel(ptr + 4);
353 e2 &= ~DESC_TSS_BUSY_MASK;
354 stl_kernel(ptr + 4, e2);
356 old_eflags = compute_eflags();
357 if (source == SWITCH_TSS_IRET)
358 old_eflags &= ~NT_MASK;
360 /* save the current state in the old TSS */
363 stl_kernel(env->tr.base + 0x20, next_eip);
364 stl_kernel(env->tr.base + 0x24, old_eflags);
365 stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
366 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
367 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
368 stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
369 stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
370 stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
371 stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
372 stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
373 for(i = 0; i < 6; i++)
374 stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
377 stw_kernel(env->tr.base + 0x0e, next_eip);
378 stw_kernel(env->tr.base + 0x10, old_eflags);
379 stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
380 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
381 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
382 stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
383 stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
384 stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
385 stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
386 stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
387 for(i = 0; i < 4; i++)
388 stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
391 /* now if an exception occurs, it will occurs in the next task
394 if (source == SWITCH_TSS_CALL) {
395 stw_kernel(tss_base, env->tr.selector);
396 new_eflags |= NT_MASK;
400 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
403 ptr = env->gdt.base + (tss_selector & ~7);
404 e2 = ldl_kernel(ptr + 4);
405 e2 |= DESC_TSS_BUSY_MASK;
406 stl_kernel(ptr + 4, e2);
409 /* set the new CPU state */
410 /* from this point, any exception which occurs can give problems */
411 env->cr[0] |= CR0_TS_MASK;
412 env->hflags |= HF_TS_MASK;
413 env->tr.selector = tss_selector;
414 env->tr.base = tss_base;
415 env->tr.limit = tss_limit;
416 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
418 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
419 cpu_x86_update_cr3(env, new_cr3);
422 /* load all registers without an exception, then reload them with
423 possible exception */
425 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
426 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
428 eflags_mask &= 0xffff;
429 load_eflags(new_eflags, eflags_mask);
430 /* XXX: what to do in 16 bit case ? */
439 if (new_eflags & VM_MASK) {
440 for(i = 0; i < 6; i++)
441 load_seg_vm(i, new_segs[i]);
442 /* in vm86, CPL is always 3 */
443 cpu_x86_set_cpl(env, 3);
445 /* CPL is set the RPL of CS */
446 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
447 /* first just selectors as the rest may trigger exceptions */
448 for(i = 0; i < 6; i++)
449 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
452 env->ldt.selector = new_ldt & ~4;
459 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
461 if ((new_ldt & 0xfffc) != 0) {
463 index = new_ldt & ~7;
464 if ((index + 7) > dt->limit)
465 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
466 ptr = dt->base + index;
467 e1 = ldl_kernel(ptr);
468 e2 = ldl_kernel(ptr + 4);
469 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
470 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
471 if (!(e2 & DESC_P_MASK))
472 raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
473 load_seg_cache_raw_dt(&env->ldt, e1, e2);
476 /* load the segments */
477 if (!(new_eflags & VM_MASK)) {
478 tss_load_seg(R_CS, new_segs[R_CS]);
479 tss_load_seg(R_SS, new_segs[R_SS]);
480 tss_load_seg(R_ES, new_segs[R_ES]);
481 tss_load_seg(R_DS, new_segs[R_DS]);
482 tss_load_seg(R_FS, new_segs[R_FS]);
483 tss_load_seg(R_GS, new_segs[R_GS]);
486 /* check that EIP is in the CS segment limits */
487 if (new_eip > env->segs[R_CS].limit) {
488 /* XXX: different exception if CALL ? */
489 raise_exception_err(EXCP0D_GPF, 0);
493 /* check if Port I/O is allowed in TSS */
494 static inline void check_io(int addr, int size)
496 int io_offset, val, mask;
498 /* TSS must be a valid 32 bit one */
499 if (!(env->tr.flags & DESC_P_MASK) ||
500 ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
503 io_offset = lduw_kernel(env->tr.base + 0x66);
504 io_offset += (addr >> 3);
505 /* Note: the check needs two bytes */
506 if ((io_offset + 1) > env->tr.limit)
508 val = lduw_kernel(env->tr.base + io_offset);
510 mask = (1 << size) - 1;
511 /* all bits must be zero to allow the I/O */
512 if ((val & mask) != 0) {
514 raise_exception_err(EXCP0D_GPF, 0);
518 void check_iob_T0(void)
523 void check_iow_T0(void)
528 void check_iol_T0(void)
533 void check_iob_DX(void)
535 check_io(EDX & 0xffff, 1);
538 void check_iow_DX(void)
540 check_io(EDX & 0xffff, 2);
543 void check_iol_DX(void)
545 check_io(EDX & 0xffff, 4);
548 static inline unsigned int get_sp_mask(unsigned int e2)
550 if (e2 & DESC_B_MASK)
557 #define SET_ESP(val, sp_mask)\
559 if ((sp_mask) == 0xffff)\
560 ESP = (ESP & ~0xffff) | ((val) & 0xffff);\
561 else if ((sp_mask) == 0xffffffffLL)\
562 ESP = (uint32_t)(val);\
567 #define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask))
570 /* XXX: add a is_user flag to have proper security support */
571 #define PUSHW(ssp, sp, sp_mask, val)\
574 stw_kernel((ssp) + (sp & (sp_mask)), (val));\
577 #define PUSHL(ssp, sp, sp_mask, val)\
580 stl_kernel((ssp) + (sp & (sp_mask)), (val));\
583 #define POPW(ssp, sp, sp_mask, val)\
585 val = lduw_kernel((ssp) + (sp & (sp_mask)));\
589 #define POPL(ssp, sp, sp_mask, val)\
591 val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
595 /* protected mode interrupt */
596 static void do_interrupt_protected(int intno, int is_int, int error_code,
597 unsigned int next_eip, int is_hw)
600 target_ulong ptr, ssp;
601 int type, dpl, selector, ss_dpl, cpl;
602 int has_error_code, new_stack, shift;
603 uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
604 uint32_t old_eip, sp_mask;
607 if (!is_int && !is_hw) {
626 if (intno * 8 + 7 > dt->limit)
627 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
628 ptr = dt->base + intno * 8;
629 e1 = ldl_kernel(ptr);
630 e2 = ldl_kernel(ptr + 4);
631 /* check gate type */
632 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
634 case 5: /* task gate */
635 /* must do that check here to return the correct error code */
636 if (!(e2 & DESC_P_MASK))
637 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
638 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
639 if (has_error_code) {
642 /* push the error code */
643 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
645 if (env->segs[R_SS].flags & DESC_B_MASK)
649 esp = (ESP - (2 << shift)) & mask;
650 ssp = env->segs[R_SS].base + esp;
652 stl_kernel(ssp, error_code);
654 stw_kernel(ssp, error_code);
658 case 6: /* 286 interrupt gate */
659 case 7: /* 286 trap gate */
660 case 14: /* 386 interrupt gate */
661 case 15: /* 386 trap gate */
664 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
667 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
668 cpl = env->hflags & HF_CPL_MASK;
669 /* check privledge if software int */
670 if (is_int && dpl < cpl)
671 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
672 /* check valid bit */
673 if (!(e2 & DESC_P_MASK))
674 raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
676 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
677 if ((selector & 0xfffc) == 0)
678 raise_exception_err(EXCP0D_GPF, 0);
680 if (load_segment(&e1, &e2, selector) != 0)
681 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
682 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
683 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
684 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
686 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
687 if (!(e2 & DESC_P_MASK))
688 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
689 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
690 /* to inner priviledge */
691 get_ss_esp_from_tss(&ss, &esp, dpl);
692 if ((ss & 0xfffc) == 0)
693 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
695 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
696 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
697 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
698 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
700 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
701 if (!(ss_e2 & DESC_S_MASK) ||
702 (ss_e2 & DESC_CS_MASK) ||
703 !(ss_e2 & DESC_W_MASK))
704 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
705 if (!(ss_e2 & DESC_P_MASK))
706 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
708 sp_mask = get_sp_mask(ss_e2);
709 ssp = get_seg_base(ss_e1, ss_e2);
710 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
711 /* to same priviledge */
712 if (env->eflags & VM_MASK)
713 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
715 sp_mask = get_sp_mask(env->segs[R_SS].flags);
716 ssp = env->segs[R_SS].base;
720 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
721 new_stack = 0; /* avoid warning */
722 sp_mask = 0; /* avoid warning */
723 ssp = 0; /* avoid warning */
724 esp = 0; /* avoid warning */
730 /* XXX: check that enough room is available */
731 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
732 if (env->eflags & VM_MASK)
738 if (env->eflags & VM_MASK) {
739 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
740 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
741 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
742 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
744 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
745 PUSHL(ssp, esp, sp_mask, ESP);
747 PUSHL(ssp, esp, sp_mask, compute_eflags());
748 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
749 PUSHL(ssp, esp, sp_mask, old_eip);
750 if (has_error_code) {
751 PUSHL(ssp, esp, sp_mask, error_code);
755 if (env->eflags & VM_MASK) {
756 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
757 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
758 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
759 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
761 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
762 PUSHW(ssp, esp, sp_mask, ESP);
764 PUSHW(ssp, esp, sp_mask, compute_eflags());
765 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
766 PUSHW(ssp, esp, sp_mask, old_eip);
767 if (has_error_code) {
768 PUSHW(ssp, esp, sp_mask, error_code);
773 if (env->eflags & VM_MASK) {
774 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
775 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
776 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
777 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
779 ss = (ss & ~3) | dpl;
780 cpu_x86_load_seg_cache(env, R_SS, ss,
781 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
783 SET_ESP(esp, sp_mask);
785 selector = (selector & ~3) | dpl;
786 cpu_x86_load_seg_cache(env, R_CS, selector,
787 get_seg_base(e1, e2),
788 get_seg_limit(e1, e2),
790 cpu_x86_set_cpl(env, dpl);
793 /* interrupt gate clear IF mask */
794 if ((type & 1) == 0) {
795 env->eflags &= ~IF_MASK;
797 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
802 #define PUSHQ(sp, val)\
805 stq_kernel(sp, (val));\
808 #define POPQ(sp, val)\
810 val = ldq_kernel(sp);\
814 static inline target_ulong get_rsp_from_tss(int level)
819 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
820 env->tr.base, env->tr.limit);
823 if (!(env->tr.flags & DESC_P_MASK))
824 cpu_abort(env, "invalid tss");
825 index = 8 * level + 4;
826 if ((index + 7) > env->tr.limit)
827 raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
828 return ldq_kernel(env->tr.base + index);
831 /* 64 bit interrupt */
832 static void do_interrupt64(int intno, int is_int, int error_code,
833 target_ulong next_eip, int is_hw)
837 int type, dpl, selector, cpl, ist;
838 int has_error_code, new_stack;
839 uint32_t e1, e2, e3, ss;
840 target_ulong old_eip, esp, offset;
843 if (!is_int && !is_hw) {
862 if (intno * 16 + 15 > dt->limit)
863 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
864 ptr = dt->base + intno * 16;
865 e1 = ldl_kernel(ptr);
866 e2 = ldl_kernel(ptr + 4);
867 e3 = ldl_kernel(ptr + 8);
868 /* check gate type */
869 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
871 case 14: /* 386 interrupt gate */
872 case 15: /* 386 trap gate */
875 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
878 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
879 cpl = env->hflags & HF_CPL_MASK;
880 /* check privledge if software int */
881 if (is_int && dpl < cpl)
882 raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
883 /* check valid bit */
884 if (!(e2 & DESC_P_MASK))
885 raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
887 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
889 if ((selector & 0xfffc) == 0)
890 raise_exception_err(EXCP0D_GPF, 0);
892 if (load_segment(&e1, &e2, selector) != 0)
893 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
894 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
895 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
896 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
898 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
899 if (!(e2 & DESC_P_MASK))
900 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
901 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK))
902 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
903 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
904 /* to inner priviledge */
906 esp = get_rsp_from_tss(ist + 3);
908 esp = get_rsp_from_tss(dpl);
909 esp &= ~0xfLL; /* align stack */
912 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
913 /* to same priviledge */
914 if (env->eflags & VM_MASK)
915 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
918 esp = get_rsp_from_tss(ist + 3);
921 esp &= ~0xfLL; /* align stack */
924 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
925 new_stack = 0; /* avoid warning */
926 esp = 0; /* avoid warning */
929 PUSHQ(esp, env->segs[R_SS].selector);
931 PUSHQ(esp, compute_eflags());
932 PUSHQ(esp, env->segs[R_CS].selector);
934 if (has_error_code) {
935 PUSHQ(esp, error_code);
940 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
944 selector = (selector & ~3) | dpl;
945 cpu_x86_load_seg_cache(env, R_CS, selector,
946 get_seg_base(e1, e2),
947 get_seg_limit(e1, e2),
949 cpu_x86_set_cpl(env, dpl);
952 /* interrupt gate clear IF mask */
953 if ((type & 1) == 0) {
954 env->eflags &= ~IF_MASK;
956 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
960 void helper_syscall(int next_eip_addend)
964 if (!(env->efer & MSR_EFER_SCE)) {
965 raise_exception_err(EXCP06_ILLOP, 0);
967 selector = (env->star >> 32) & 0xffff;
969 if (env->hflags & HF_LMA_MASK) {
972 ECX = env->eip + next_eip_addend;
973 env->regs[11] = compute_eflags();
975 code64 = env->hflags & HF_CS64_MASK;
977 cpu_x86_set_cpl(env, 0);
978 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
980 DESC_G_MASK | DESC_P_MASK |
982 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
983 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
985 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
987 DESC_W_MASK | DESC_A_MASK);
988 env->eflags &= ~env->fmask;
990 env->eip = env->lstar;
992 env->eip = env->cstar;
996 ECX = (uint32_t)(env->eip + next_eip_addend);
998 cpu_x86_set_cpl(env, 0);
999 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1001 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1003 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1004 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1006 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1008 DESC_W_MASK | DESC_A_MASK);
1009 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
1010 env->eip = (uint32_t)env->star;
1014 void helper_sysret(int dflag)
1018 if (!(env->efer & MSR_EFER_SCE)) {
1019 raise_exception_err(EXCP06_ILLOP, 0);
1021 cpl = env->hflags & HF_CPL_MASK;
1022 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1023 raise_exception_err(EXCP0D_GPF, 0);
1025 selector = (env->star >> 48) & 0xffff;
1026 #ifdef TARGET_X86_64
1027 if (env->hflags & HF_LMA_MASK) {
1029 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1031 DESC_G_MASK | DESC_P_MASK |
1032 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1033 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1037 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1039 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1040 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1041 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1042 env->eip = (uint32_t)ECX;
1044 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1046 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1047 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1048 DESC_W_MASK | DESC_A_MASK);
1049 load_eflags((uint32_t)(env->regs[11]), TF_MASK | AC_MASK | ID_MASK |
1050 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK);
1051 cpu_x86_set_cpl(env, 3);
1055 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1057 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1058 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1059 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1060 env->eip = (uint32_t)ECX;
1061 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1063 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1064 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1065 DESC_W_MASK | DESC_A_MASK);
1066 env->eflags |= IF_MASK;
1067 cpu_x86_set_cpl(env, 3);
1070 if (kqemu_is_ok(env)) {
1071 if (env->hflags & HF_LMA_MASK)
1072 CC_OP = CC_OP_EFLAGS;
1073 env->exception_index = -1;
1079 /* real mode interrupt */
1080 static void do_interrupt_real(int intno, int is_int, int error_code,
1081 unsigned int next_eip)
1084 target_ulong ptr, ssp;
1086 uint32_t offset, esp;
1087 uint32_t old_cs, old_eip;
1089 /* real mode (simpler !) */
1091 if (intno * 4 + 3 > dt->limit)
1092 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1093 ptr = dt->base + intno * 4;
1094 offset = lduw_kernel(ptr);
1095 selector = lduw_kernel(ptr + 2);
1097 ssp = env->segs[R_SS].base;
1102 old_cs = env->segs[R_CS].selector;
1103 /* XXX: use SS segment size ? */
1104 PUSHW(ssp, esp, 0xffff, compute_eflags());
1105 PUSHW(ssp, esp, 0xffff, old_cs);
1106 PUSHW(ssp, esp, 0xffff, old_eip);
1108 /* update processor state */
1109 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1111 env->segs[R_CS].selector = selector;
1112 env->segs[R_CS].base = (selector << 4);
1113 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1116 /* fake user mode interrupt */
1117 void do_interrupt_user(int intno, int is_int, int error_code,
1118 target_ulong next_eip)
1126 ptr = dt->base + (intno * 8);
1127 e2 = ldl_kernel(ptr + 4);
1129 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1130 cpl = env->hflags & HF_CPL_MASK;
1131 /* check privledge if software int */
1132 if (is_int && dpl < cpl)
1133 raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1135 /* Since we emulate only user space, we cannot do more than
1136 exiting the emulation with the suitable exception and error
1143 * Begin execution of an interruption. is_int is TRUE if coming from
1144 * the int instruction. next_eip is the EIP value AFTER the interrupt
1145 * instruction. It is only relevant if is_int is TRUE.
1147 void do_interrupt(int intno, int is_int, int error_code,
1148 target_ulong next_eip, int is_hw)
1150 if (loglevel & CPU_LOG_INT) {
1151 if ((env->cr[0] & CR0_PE_MASK)) {
1153 fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1154 count, intno, error_code, is_int,
1155 env->hflags & HF_CPL_MASK,
1156 env->segs[R_CS].selector, EIP,
1157 (int)env->segs[R_CS].base + EIP,
1158 env->segs[R_SS].selector, ESP);
1159 if (intno == 0x0e) {
1160 fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1162 fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1164 fprintf(logfile, "\n");
1165 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1170 fprintf(logfile, " code=");
1171 ptr = env->segs[R_CS].base + env->eip;
1172 for(i = 0; i < 16; i++) {
1173 fprintf(logfile, " %02x", ldub(ptr + i));
1175 fprintf(logfile, "\n");
1181 if (env->cr[0] & CR0_PE_MASK) {
1183 if (env->hflags & HF_LMA_MASK) {
1184 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1188 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1191 do_interrupt_real(intno, is_int, error_code, next_eip);
1196 * Check nested exceptions and change to double or triple fault if
1197 * needed. It should only be called, if this is not an interrupt.
1198 * Returns the new exception number.
1200 int check_exception(int intno, int *error_code)
1202 char first_contributory = env->old_exception == 0 ||
1203 (env->old_exception >= 10 &&
1204 env->old_exception <= 13);
1205 char second_contributory = intno == 0 ||
1206 (intno >= 10 && intno <= 13);
1208 if (loglevel & CPU_LOG_INT)
1209 fprintf(logfile, "check_exception old: %x new %x\n",
1210 env->old_exception, intno);
1212 if (env->old_exception == EXCP08_DBLE)
1213 cpu_abort(env, "triple fault");
1215 if ((first_contributory && second_contributory)
1216 || (env->old_exception == EXCP0E_PAGE &&
1217 (second_contributory || (intno == EXCP0E_PAGE)))) {
1218 intno = EXCP08_DBLE;
1222 if (second_contributory || (intno == EXCP0E_PAGE) ||
1223 (intno == EXCP08_DBLE))
1224 env->old_exception = intno;
1230 * Signal an interruption. It is executed in the main CPU loop.
1231 * is_int is TRUE if coming from the int instruction. next_eip is the
1232 * EIP value AFTER the interrupt instruction. It is only relevant if
1235 void raise_interrupt(int intno, int is_int, int error_code,
1236 int next_eip_addend)
1239 intno = check_exception(intno, &error_code);
1241 env->exception_index = intno;
1242 env->error_code = error_code;
1243 env->exception_is_int = is_int;
1244 env->exception_next_eip = env->eip + next_eip_addend;
1248 /* same as raise_exception_err, but do not restore global registers */
1249 static void raise_exception_err_norestore(int exception_index, int error_code)
1251 exception_index = check_exception(exception_index, &error_code);
1253 env->exception_index = exception_index;
1254 env->error_code = error_code;
1255 env->exception_is_int = 0;
1256 env->exception_next_eip = 0;
1257 longjmp(env->jmp_env, 1);
1260 /* shortcuts to generate exceptions */
1262 void (raise_exception_err)(int exception_index, int error_code)
1264 raise_interrupt(exception_index, 0, error_code, 0);
1267 void raise_exception(int exception_index)
1269 raise_interrupt(exception_index, 0, 0, 0);
1274 #if defined(CONFIG_USER_ONLY)
1276 void do_smm_enter(void)
1280 void helper_rsm(void)
1286 #ifdef TARGET_X86_64
1287 #define SMM_REVISION_ID 0x00020064
1289 #define SMM_REVISION_ID 0x00020000
1292 void do_smm_enter(void)
1294 target_ulong sm_state;
1298 if (loglevel & CPU_LOG_INT) {
1299 fprintf(logfile, "SMM: enter\n");
1300 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1303 env->hflags |= HF_SMM_MASK;
1304 cpu_smm_update(env);
1306 sm_state = env->smbase + 0x8000;
1308 #ifdef TARGET_X86_64
1309 for(i = 0; i < 6; i++) {
1311 offset = 0x7e00 + i * 16;
1312 stw_phys(sm_state + offset, dt->selector);
1313 stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1314 stl_phys(sm_state + offset + 4, dt->limit);
1315 stq_phys(sm_state + offset + 8, dt->base);
1318 stq_phys(sm_state + 0x7e68, env->gdt.base);
1319 stl_phys(sm_state + 0x7e64, env->gdt.limit);
1321 stw_phys(sm_state + 0x7e70, env->ldt.selector);
1322 stq_phys(sm_state + 0x7e78, env->ldt.base);
1323 stl_phys(sm_state + 0x7e74, env->ldt.limit);
1324 stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1326 stq_phys(sm_state + 0x7e88, env->idt.base);
1327 stl_phys(sm_state + 0x7e84, env->idt.limit);
1329 stw_phys(sm_state + 0x7e90, env->tr.selector);
1330 stq_phys(sm_state + 0x7e98, env->tr.base);
1331 stl_phys(sm_state + 0x7e94, env->tr.limit);
1332 stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1334 stq_phys(sm_state + 0x7ed0, env->efer);
1336 stq_phys(sm_state + 0x7ff8, EAX);
1337 stq_phys(sm_state + 0x7ff0, ECX);
1338 stq_phys(sm_state + 0x7fe8, EDX);
1339 stq_phys(sm_state + 0x7fe0, EBX);
1340 stq_phys(sm_state + 0x7fd8, ESP);
1341 stq_phys(sm_state + 0x7fd0, EBP);
1342 stq_phys(sm_state + 0x7fc8, ESI);
1343 stq_phys(sm_state + 0x7fc0, EDI);
1344 for(i = 8; i < 16; i++)
1345 stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1346 stq_phys(sm_state + 0x7f78, env->eip);
1347 stl_phys(sm_state + 0x7f70, compute_eflags());
1348 stl_phys(sm_state + 0x7f68, env->dr[6]);
1349 stl_phys(sm_state + 0x7f60, env->dr[7]);
1351 stl_phys(sm_state + 0x7f48, env->cr[4]);
1352 stl_phys(sm_state + 0x7f50, env->cr[3]);
1353 stl_phys(sm_state + 0x7f58, env->cr[0]);
1355 stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1356 stl_phys(sm_state + 0x7f00, env->smbase);
1358 stl_phys(sm_state + 0x7ffc, env->cr[0]);
1359 stl_phys(sm_state + 0x7ff8, env->cr[3]);
1360 stl_phys(sm_state + 0x7ff4, compute_eflags());
1361 stl_phys(sm_state + 0x7ff0, env->eip);
1362 stl_phys(sm_state + 0x7fec, EDI);
1363 stl_phys(sm_state + 0x7fe8, ESI);
1364 stl_phys(sm_state + 0x7fe4, EBP);
1365 stl_phys(sm_state + 0x7fe0, ESP);
1366 stl_phys(sm_state + 0x7fdc, EBX);
1367 stl_phys(sm_state + 0x7fd8, EDX);
1368 stl_phys(sm_state + 0x7fd4, ECX);
1369 stl_phys(sm_state + 0x7fd0, EAX);
1370 stl_phys(sm_state + 0x7fcc, env->dr[6]);
1371 stl_phys(sm_state + 0x7fc8, env->dr[7]);
1373 stl_phys(sm_state + 0x7fc4, env->tr.selector);
1374 stl_phys(sm_state + 0x7f64, env->tr.base);
1375 stl_phys(sm_state + 0x7f60, env->tr.limit);
1376 stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1378 stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1379 stl_phys(sm_state + 0x7f80, env->ldt.base);
1380 stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1381 stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1383 stl_phys(sm_state + 0x7f74, env->gdt.base);
1384 stl_phys(sm_state + 0x7f70, env->gdt.limit);
1386 stl_phys(sm_state + 0x7f58, env->idt.base);
1387 stl_phys(sm_state + 0x7f54, env->idt.limit);
1389 for(i = 0; i < 6; i++) {
1392 offset = 0x7f84 + i * 12;
1394 offset = 0x7f2c + (i - 3) * 12;
1395 stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1396 stl_phys(sm_state + offset + 8, dt->base);
1397 stl_phys(sm_state + offset + 4, dt->limit);
1398 stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1400 stl_phys(sm_state + 0x7f14, env->cr[4]);
1402 stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1403 stl_phys(sm_state + 0x7ef8, env->smbase);
1405 /* init SMM cpu state */
1407 #ifdef TARGET_X86_64
1409 env->hflags &= ~HF_LMA_MASK;
1411 load_eflags(0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1412 env->eip = 0x00008000;
1413 cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1415 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1416 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1417 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1418 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1419 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1421 cpu_x86_update_cr0(env,
1422 env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | CR0_PG_MASK));
1423 cpu_x86_update_cr4(env, 0);
1424 env->dr[7] = 0x00000400;
1425 CC_OP = CC_OP_EFLAGS;
1428 void helper_rsm(void)
1430 target_ulong sm_state;
1434 sm_state = env->smbase + 0x8000;
1435 #ifdef TARGET_X86_64
1436 env->efer = ldq_phys(sm_state + 0x7ed0);
1437 if (env->efer & MSR_EFER_LMA)
1438 env->hflags |= HF_LMA_MASK;
1440 env->hflags &= ~HF_LMA_MASK;
1442 for(i = 0; i < 6; i++) {
1443 offset = 0x7e00 + i * 16;
1444 cpu_x86_load_seg_cache(env, i,
1445 lduw_phys(sm_state + offset),
1446 ldq_phys(sm_state + offset + 8),
1447 ldl_phys(sm_state + offset + 4),
1448 (lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1451 env->gdt.base = ldq_phys(sm_state + 0x7e68);
1452 env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1454 env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1455 env->ldt.base = ldq_phys(sm_state + 0x7e78);
1456 env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1457 env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1459 env->idt.base = ldq_phys(sm_state + 0x7e88);
1460 env->idt.limit = ldl_phys(sm_state + 0x7e84);
1462 env->tr.selector = lduw_phys(sm_state + 0x7e90);
1463 env->tr.base = ldq_phys(sm_state + 0x7e98);
1464 env->tr.limit = ldl_phys(sm_state + 0x7e94);
1465 env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1467 EAX = ldq_phys(sm_state + 0x7ff8);
1468 ECX = ldq_phys(sm_state + 0x7ff0);
1469 EDX = ldq_phys(sm_state + 0x7fe8);
1470 EBX = ldq_phys(sm_state + 0x7fe0);
1471 ESP = ldq_phys(sm_state + 0x7fd8);
1472 EBP = ldq_phys(sm_state + 0x7fd0);
1473 ESI = ldq_phys(sm_state + 0x7fc8);
1474 EDI = ldq_phys(sm_state + 0x7fc0);
1475 for(i = 8; i < 16; i++)
1476 env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1477 env->eip = ldq_phys(sm_state + 0x7f78);
1478 load_eflags(ldl_phys(sm_state + 0x7f70),
1479 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1480 env->dr[6] = ldl_phys(sm_state + 0x7f68);
1481 env->dr[7] = ldl_phys(sm_state + 0x7f60);
1483 cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1484 cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1485 cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1487 val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1488 if (val & 0x20000) {
1489 env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1492 cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1493 cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1494 load_eflags(ldl_phys(sm_state + 0x7ff4),
1495 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
1496 env->eip = ldl_phys(sm_state + 0x7ff0);
1497 EDI = ldl_phys(sm_state + 0x7fec);
1498 ESI = ldl_phys(sm_state + 0x7fe8);
1499 EBP = ldl_phys(sm_state + 0x7fe4);
1500 ESP = ldl_phys(sm_state + 0x7fe0);
1501 EBX = ldl_phys(sm_state + 0x7fdc);
1502 EDX = ldl_phys(sm_state + 0x7fd8);
1503 ECX = ldl_phys(sm_state + 0x7fd4);
1504 EAX = ldl_phys(sm_state + 0x7fd0);
1505 env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1506 env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1508 env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1509 env->tr.base = ldl_phys(sm_state + 0x7f64);
1510 env->tr.limit = ldl_phys(sm_state + 0x7f60);
1511 env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1513 env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1514 env->ldt.base = ldl_phys(sm_state + 0x7f80);
1515 env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1516 env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1518 env->gdt.base = ldl_phys(sm_state + 0x7f74);
1519 env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1521 env->idt.base = ldl_phys(sm_state + 0x7f58);
1522 env->idt.limit = ldl_phys(sm_state + 0x7f54);
1524 for(i = 0; i < 6; i++) {
1526 offset = 0x7f84 + i * 12;
1528 offset = 0x7f2c + (i - 3) * 12;
1529 cpu_x86_load_seg_cache(env, i,
1530 ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1531 ldl_phys(sm_state + offset + 8),
1532 ldl_phys(sm_state + offset + 4),
1533 (ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1535 cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1537 val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1538 if (val & 0x20000) {
1539 env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1542 CC_OP = CC_OP_EFLAGS;
1543 env->hflags &= ~HF_SMM_MASK;
1544 cpu_smm_update(env);
1546 if (loglevel & CPU_LOG_INT) {
1547 fprintf(logfile, "SMM: after RSM\n");
1548 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1552 #endif /* !CONFIG_USER_ONLY */
1555 #ifdef BUGGY_GCC_DIV64
1556 /* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1557 call it from another function */
1558 uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1564 int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1571 void helper_divl_EAX_T0(void)
1573 unsigned int den, r;
1576 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1579 raise_exception(EXCP00_DIVZ);
1581 #ifdef BUGGY_GCC_DIV64
1582 r = div32(&q, num, den);
1588 raise_exception(EXCP00_DIVZ);
1593 void helper_idivl_EAX_T0(void)
1598 num = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
1601 raise_exception(EXCP00_DIVZ);
1603 #ifdef BUGGY_GCC_DIV64
1604 r = idiv32(&q, num, den);
1609 if (q != (int32_t)q)
1610 raise_exception(EXCP00_DIVZ);
1615 void helper_cmpxchg8b(void)
1620 eflags = cc_table[CC_OP].compute_all();
1622 if (d == (((uint64_t)EDX << 32) | EAX)) {
1623 stq(A0, ((uint64_t)ECX << 32) | EBX);
1633 void helper_cpuid(void)
1636 index = (uint32_t)EAX;
1638 /* test if maximum index reached */
1639 if (index & 0x80000000) {
1640 if (index > env->cpuid_xlevel)
1641 index = env->cpuid_level;
1643 if (index > env->cpuid_level)
1644 index = env->cpuid_level;
1649 EAX = env->cpuid_level;
1650 EBX = env->cpuid_vendor1;
1651 EDX = env->cpuid_vendor2;
1652 ECX = env->cpuid_vendor3;
1655 EAX = env->cpuid_version;
1656 EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1657 ECX = env->cpuid_ext_features;
1658 EDX = env->cpuid_features;
1661 /* cache info: needed for Pentium Pro compatibility */
1668 EAX = env->cpuid_xlevel;
1669 EBX = env->cpuid_vendor1;
1670 EDX = env->cpuid_vendor2;
1671 ECX = env->cpuid_vendor3;
1674 EAX = env->cpuid_features;
1677 EDX = env->cpuid_ext2_features;
1682 EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1683 EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1684 ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1685 EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1688 /* cache info (L1 cache) */
1695 /* cache info (L2 cache) */
1702 /* virtual & phys address size in low 2 bytes. */
1709 /* reserved values: zero */
1718 void helper_enter_level(int level, int data32)
1721 uint32_t esp_mask, esp, ebp;
1723 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1724 ssp = env->segs[R_SS].base;
1733 stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1736 stl(ssp + (esp & esp_mask), T1);
1743 stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1746 stw(ssp + (esp & esp_mask), T1);
1750 #ifdef TARGET_X86_64
1751 void helper_enter64_level(int level, int data64)
1753 target_ulong esp, ebp;
1773 stw(esp, lduw(ebp));
1781 void helper_lldt_T0(void)
1786 int index, entry_limit;
1789 selector = T0 & 0xffff;
1790 if ((selector & 0xfffc) == 0) {
1791 /* XXX: NULL selector case: invalid LDT */
1796 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1798 index = selector & ~7;
1799 #ifdef TARGET_X86_64
1800 if (env->hflags & HF_LMA_MASK)
1805 if ((index + entry_limit) > dt->limit)
1806 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1807 ptr = dt->base + index;
1808 e1 = ldl_kernel(ptr);
1809 e2 = ldl_kernel(ptr + 4);
1810 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1811 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1812 if (!(e2 & DESC_P_MASK))
1813 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1814 #ifdef TARGET_X86_64
1815 if (env->hflags & HF_LMA_MASK) {
1817 e3 = ldl_kernel(ptr + 8);
1818 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1819 env->ldt.base |= (target_ulong)e3 << 32;
1823 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1826 env->ldt.selector = selector;
1829 void helper_ltr_T0(void)
1834 int index, type, entry_limit;
1837 selector = T0 & 0xffff;
1838 if ((selector & 0xfffc) == 0) {
1839 /* NULL selector case: invalid TR */
1845 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1847 index = selector & ~7;
1848 #ifdef TARGET_X86_64
1849 if (env->hflags & HF_LMA_MASK)
1854 if ((index + entry_limit) > dt->limit)
1855 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1856 ptr = dt->base + index;
1857 e1 = ldl_kernel(ptr);
1858 e2 = ldl_kernel(ptr + 4);
1859 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1860 if ((e2 & DESC_S_MASK) ||
1861 (type != 1 && type != 9))
1862 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1863 if (!(e2 & DESC_P_MASK))
1864 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1865 #ifdef TARGET_X86_64
1866 if (env->hflags & HF_LMA_MASK) {
1868 e3 = ldl_kernel(ptr + 8);
1869 load_seg_cache_raw_dt(&env->tr, e1, e2);
1870 env->tr.base |= (target_ulong)e3 << 32;
1874 load_seg_cache_raw_dt(&env->tr, e1, e2);
1876 e2 |= DESC_TSS_BUSY_MASK;
1877 stl_kernel(ptr + 4, e2);
1879 env->tr.selector = selector;
1882 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1883 void load_seg(int seg_reg, int selector)
1892 cpl = env->hflags & HF_CPL_MASK;
1893 if ((selector & 0xfffc) == 0) {
1894 /* null selector case */
1896 #ifdef TARGET_X86_64
1897 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1900 raise_exception_err(EXCP0D_GPF, 0);
1901 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1908 index = selector & ~7;
1909 if ((index + 7) > dt->limit)
1910 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1911 ptr = dt->base + index;
1912 e1 = ldl_kernel(ptr);
1913 e2 = ldl_kernel(ptr + 4);
1915 if (!(e2 & DESC_S_MASK))
1916 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1918 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1919 if (seg_reg == R_SS) {
1920 /* must be writable segment */
1921 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))
1922 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1923 if (rpl != cpl || dpl != cpl)
1924 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1926 /* must be readable segment */
1927 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK)
1928 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1930 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1931 /* if not conforming code, test rights */
1932 if (dpl < cpl || dpl < rpl)
1933 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1937 if (!(e2 & DESC_P_MASK)) {
1938 if (seg_reg == R_SS)
1939 raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
1941 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1944 /* set the access bit if not already set */
1945 if (!(e2 & DESC_A_MASK)) {
1947 stl_kernel(ptr + 4, e2);
1950 cpu_x86_load_seg_cache(env, seg_reg, selector,
1951 get_seg_base(e1, e2),
1952 get_seg_limit(e1, e2),
1955 fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1956 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1961 /* protected mode jump */
1962 void helper_ljmp_protected_T0_T1(int next_eip_addend)
1964 int new_cs, gate_cs, type;
1965 uint32_t e1, e2, cpl, dpl, rpl, limit;
1966 target_ulong new_eip, next_eip;
1970 if ((new_cs & 0xfffc) == 0)
1971 raise_exception_err(EXCP0D_GPF, 0);
1972 if (load_segment(&e1, &e2, new_cs) != 0)
1973 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1974 cpl = env->hflags & HF_CPL_MASK;
1975 if (e2 & DESC_S_MASK) {
1976 if (!(e2 & DESC_CS_MASK))
1977 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1978 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1979 if (e2 & DESC_C_MASK) {
1980 /* conforming code segment */
1982 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1984 /* non conforming code segment */
1987 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1989 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1991 if (!(e2 & DESC_P_MASK))
1992 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
1993 limit = get_seg_limit(e1, e2);
1994 if (new_eip > limit &&
1995 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
1996 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
1997 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1998 get_seg_base(e1, e2), limit, e2);
2001 /* jump to call or task gate */
2002 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2004 cpl = env->hflags & HF_CPL_MASK;
2005 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2007 case 1: /* 286 TSS */
2008 case 9: /* 386 TSS */
2009 case 5: /* task gate */
2010 if (dpl < cpl || dpl < rpl)
2011 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2012 next_eip = env->eip + next_eip_addend;
2013 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2014 CC_OP = CC_OP_EFLAGS;
2016 case 4: /* 286 call gate */
2017 case 12: /* 386 call gate */
2018 if ((dpl < cpl) || (dpl < rpl))
2019 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2020 if (!(e2 & DESC_P_MASK))
2021 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2023 new_eip = (e1 & 0xffff);
2025 new_eip |= (e2 & 0xffff0000);
2026 if (load_segment(&e1, &e2, gate_cs) != 0)
2027 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2028 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2029 /* must be code segment */
2030 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
2031 (DESC_S_MASK | DESC_CS_MASK)))
2032 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2033 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
2034 (!(e2 & DESC_C_MASK) && (dpl != cpl)))
2035 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2036 if (!(e2 & DESC_P_MASK))
2037 raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2038 limit = get_seg_limit(e1, e2);
2039 if (new_eip > limit)
2040 raise_exception_err(EXCP0D_GPF, 0);
2041 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
2042 get_seg_base(e1, e2), limit, e2);
2046 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2052 /* real mode call */
2053 void helper_lcall_real_T0_T1(int shift, int next_eip)
2055 int new_cs, new_eip;
2056 uint32_t esp, esp_mask;
2062 esp_mask = get_sp_mask(env->segs[R_SS].flags);
2063 ssp = env->segs[R_SS].base;
2065 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2066 PUSHL(ssp, esp, esp_mask, next_eip);
2068 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2069 PUSHW(ssp, esp, esp_mask, next_eip);
2072 SET_ESP(esp, esp_mask);
2074 env->segs[R_CS].selector = new_cs;
2075 env->segs[R_CS].base = (new_cs << 4);
2078 /* protected mode call */
2079 void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2081 int new_cs, new_stack, i;
2082 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2083 uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2084 uint32_t val, limit, old_sp_mask;
2085 target_ulong ssp, old_ssp, next_eip, new_eip;
2089 next_eip = env->eip + next_eip_addend;
2091 if (loglevel & CPU_LOG_PCALL) {
2092 fprintf(logfile, "lcall %04x:%08x s=%d\n",
2093 new_cs, (uint32_t)new_eip, shift);
2094 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2097 if ((new_cs & 0xfffc) == 0)
2098 raise_exception_err(EXCP0D_GPF, 0);
2099 if (load_segment(&e1, &e2, new_cs) != 0)
2100 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2101 cpl = env->hflags & HF_CPL_MASK;
2103 if (loglevel & CPU_LOG_PCALL) {
2104 fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2107 if (e2 & DESC_S_MASK) {
2108 if (!(e2 & DESC_CS_MASK))
2109 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2110 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2111 if (e2 & DESC_C_MASK) {
2112 /* conforming code segment */
2114 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2116 /* non conforming code segment */
2119 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2121 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2123 if (!(e2 & DESC_P_MASK))
2124 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2126 #ifdef TARGET_X86_64
2127 /* XXX: check 16/32 bit cases in long mode */
2132 PUSHQ(rsp, env->segs[R_CS].selector);
2133 PUSHQ(rsp, next_eip);
2134 /* from this point, not restartable */
2136 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
2137 get_seg_base(e1, e2),
2138 get_seg_limit(e1, e2), e2);
2144 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2145 ssp = env->segs[R_SS].base;
2147 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2148 PUSHL(ssp, sp, sp_mask, next_eip);
2150 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2151 PUSHW(ssp, sp, sp_mask, next_eip);
2154 limit = get_seg_limit(e1, e2);
2155 if (new_eip > limit)
2156 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2157 /* from this point, not restartable */
2158 SET_ESP(sp, sp_mask);
2159 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
2160 get_seg_base(e1, e2), limit, e2);
2164 /* check gate type */
2165 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
2166 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2169 case 1: /* available 286 TSS */
2170 case 9: /* available 386 TSS */
2171 case 5: /* task gate */
2172 if (dpl < cpl || dpl < rpl)
2173 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2174 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
2175 CC_OP = CC_OP_EFLAGS;
2177 case 4: /* 286 call gate */
2178 case 12: /* 386 call gate */
2181 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2186 if (dpl < cpl || dpl < rpl)
2187 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2188 /* check valid bit */
2189 if (!(e2 & DESC_P_MASK))
2190 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2191 selector = e1 >> 16;
2192 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
2193 param_count = e2 & 0x1f;
2194 if ((selector & 0xfffc) == 0)
2195 raise_exception_err(EXCP0D_GPF, 0);
2197 if (load_segment(&e1, &e2, selector) != 0)
2198 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2199 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))
2200 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2201 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2203 raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2204 if (!(e2 & DESC_P_MASK))
2205 raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2207 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2208 /* to inner priviledge */
2209 get_ss_esp_from_tss(&ss, &sp, dpl);
2211 if (loglevel & CPU_LOG_PCALL)
2212 fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2213 ss, sp, param_count, ESP);
2215 if ((ss & 0xfffc) == 0)
2216 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2217 if ((ss & 3) != dpl)
2218 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2219 if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2220 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2221 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2223 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2224 if (!(ss_e2 & DESC_S_MASK) ||
2225 (ss_e2 & DESC_CS_MASK) ||
2226 !(ss_e2 & DESC_W_MASK))
2227 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2228 if (!(ss_e2 & DESC_P_MASK))
2229 raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2231 // push_size = ((param_count * 2) + 8) << shift;
2233 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2234 old_ssp = env->segs[R_SS].base;
2236 sp_mask = get_sp_mask(ss_e2);
2237 ssp = get_seg_base(ss_e1, ss_e2);
2239 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2240 PUSHL(ssp, sp, sp_mask, ESP);
2241 for(i = param_count - 1; i >= 0; i--) {
2242 val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2243 PUSHL(ssp, sp, sp_mask, val);
2246 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2247 PUSHW(ssp, sp, sp_mask, ESP);
2248 for(i = param_count - 1; i >= 0; i--) {
2249 val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2250 PUSHW(ssp, sp, sp_mask, val);
2255 /* to same priviledge */
2257 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2258 ssp = env->segs[R_SS].base;
2259 // push_size = (4 << shift);
2264 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2265 PUSHL(ssp, sp, sp_mask, next_eip);
2267 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2268 PUSHW(ssp, sp, sp_mask, next_eip);
2271 /* from this point, not restartable */
2274 ss = (ss & ~3) | dpl;
2275 cpu_x86_load_seg_cache(env, R_SS, ss,
2277 get_seg_limit(ss_e1, ss_e2),
2281 selector = (selector & ~3) | dpl;
2282 cpu_x86_load_seg_cache(env, R_CS, selector,
2283 get_seg_base(e1, e2),
2284 get_seg_limit(e1, e2),
2286 cpu_x86_set_cpl(env, dpl);
2287 SET_ESP(sp, sp_mask);
2291 if (kqemu_is_ok(env)) {
2292 env->exception_index = -1;
2298 /* real and vm86 mode iret */
2299 void helper_iret_real(int shift)
2301 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2305 sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2307 ssp = env->segs[R_SS].base;
2310 POPL(ssp, sp, sp_mask, new_eip);
2311 POPL(ssp, sp, sp_mask, new_cs);
2313 POPL(ssp, sp, sp_mask, new_eflags);
2316 POPW(ssp, sp, sp_mask, new_eip);
2317 POPW(ssp, sp, sp_mask, new_cs);
2318 POPW(ssp, sp, sp_mask, new_eflags);
2320 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
2321 load_seg_vm(R_CS, new_cs);
2323 if (env->eflags & VM_MASK)
2324 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | NT_MASK;
2326 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | RF_MASK | NT_MASK;
2328 eflags_mask &= 0xffff;
2329 load_eflags(new_eflags, eflags_mask);
2332 static inline void validate_seg(int seg_reg, int cpl)
2337 /* XXX: on x86_64, we do not want to nullify FS and GS because
2338 they may still contain a valid base. I would be interested to
2339 know how a real x86_64 CPU behaves */
2340 if ((seg_reg == R_FS || seg_reg == R_GS) &&
2341 (env->segs[seg_reg].selector & 0xfffc) == 0)
2344 e2 = env->segs[seg_reg].flags;
2345 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2346 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
2347 /* data or non conforming code segment */
2349 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2354 /* protected mode iret */
2355 static inline void helper_ret_protected(int shift, int is_iret, int addend)
2357 uint32_t new_cs, new_eflags, new_ss;
2358 uint32_t new_es, new_ds, new_fs, new_gs;
2359 uint32_t e1, e2, ss_e1, ss_e2;
2360 int cpl, dpl, rpl, eflags_mask, iopl;
2361 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2363 #ifdef TARGET_X86_64
2368 sp_mask = get_sp_mask(env->segs[R_SS].flags);
2370 ssp = env->segs[R_SS].base;
2371 new_eflags = 0; /* avoid warning */
2372 #ifdef TARGET_X86_64
2378 POPQ(sp, new_eflags);
2384 POPL(ssp, sp, sp_mask, new_eip);
2385 POPL(ssp, sp, sp_mask, new_cs);
2388 POPL(ssp, sp, sp_mask, new_eflags);
2389 if (new_eflags & VM_MASK)
2390 goto return_to_vm86;
2394 POPW(ssp, sp, sp_mask, new_eip);
2395 POPW(ssp, sp, sp_mask, new_cs);
2397 POPW(ssp, sp, sp_mask, new_eflags);
2400 if (loglevel & CPU_LOG_PCALL) {
2401 fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2402 new_cs, new_eip, shift, addend);
2403 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2406 if ((new_cs & 0xfffc) == 0)
2407 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2408 if (load_segment(&e1, &e2, new_cs) != 0)
2409 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2410 if (!(e2 & DESC_S_MASK) ||
2411 !(e2 & DESC_CS_MASK))
2412 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2413 cpl = env->hflags & HF_CPL_MASK;
2416 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2417 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2418 if (e2 & DESC_C_MASK) {
2420 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2423 raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2425 if (!(e2 & DESC_P_MASK))
2426 raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2429 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2430 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2431 /* return to same priledge level */
2432 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2433 get_seg_base(e1, e2),
2434 get_seg_limit(e1, e2),
2437 /* return to different priviledge level */
2438 #ifdef TARGET_X86_64
2447 POPL(ssp, sp, sp_mask, new_esp);
2448 POPL(ssp, sp, sp_mask, new_ss);
2452 POPW(ssp, sp, sp_mask, new_esp);
2453 POPW(ssp, sp, sp_mask, new_ss);
2456 if (loglevel & CPU_LOG_PCALL) {
2457 fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2461 if ((new_ss & 0xfffc) == 0) {
2462 #ifdef TARGET_X86_64
2463 /* NULL ss is allowed in long mode if cpl != 3*/
2464 /* XXX: test CS64 ? */
2465 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2466 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2468 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2469 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2470 DESC_W_MASK | DESC_A_MASK);
2471 ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
2475 raise_exception_err(EXCP0D_GPF, 0);
2478 if ((new_ss & 3) != rpl)
2479 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2480 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2481 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2482 if (!(ss_e2 & DESC_S_MASK) ||
2483 (ss_e2 & DESC_CS_MASK) ||
2484 !(ss_e2 & DESC_W_MASK))
2485 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2486 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2488 raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2489 if (!(ss_e2 & DESC_P_MASK))
2490 raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2491 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2492 get_seg_base(ss_e1, ss_e2),
2493 get_seg_limit(ss_e1, ss_e2),
2497 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2498 get_seg_base(e1, e2),
2499 get_seg_limit(e1, e2),
2501 cpu_x86_set_cpl(env, rpl);
2503 #ifdef TARGET_X86_64
2504 if (env->hflags & HF_CS64_MASK)
2508 sp_mask = get_sp_mask(ss_e2);
2510 /* validate data segments */
2511 validate_seg(R_ES, rpl);
2512 validate_seg(R_DS, rpl);
2513 validate_seg(R_FS, rpl);
2514 validate_seg(R_GS, rpl);
2518 SET_ESP(sp, sp_mask);
2521 /* NOTE: 'cpl' is the _old_ CPL */
2522 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2524 eflags_mask |= IOPL_MASK;
2525 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2527 eflags_mask |= IF_MASK;
2529 eflags_mask &= 0xffff;
2530 load_eflags(new_eflags, eflags_mask);
2535 POPL(ssp, sp, sp_mask, new_esp);
2536 POPL(ssp, sp, sp_mask, new_ss);
2537 POPL(ssp, sp, sp_mask, new_es);
2538 POPL(ssp, sp, sp_mask, new_ds);
2539 POPL(ssp, sp, sp_mask, new_fs);
2540 POPL(ssp, sp, sp_mask, new_gs);
2542 /* modify processor state */
2543 load_eflags(new_eflags, TF_MASK | AC_MASK | ID_MASK |
2544 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | VIP_MASK);
2545 load_seg_vm(R_CS, new_cs & 0xffff);
2546 cpu_x86_set_cpl(env, 3);
2547 load_seg_vm(R_SS, new_ss & 0xffff);
2548 load_seg_vm(R_ES, new_es & 0xffff);
2549 load_seg_vm(R_DS, new_ds & 0xffff);
2550 load_seg_vm(R_FS, new_fs & 0xffff);
2551 load_seg_vm(R_GS, new_gs & 0xffff);
2553 env->eip = new_eip & 0xffff;
2557 void helper_iret_protected(int shift, int next_eip)
2559 int tss_selector, type;
2562 /* specific case for TSS */
2563 if (env->eflags & NT_MASK) {
2564 #ifdef TARGET_X86_64
2565 if (env->hflags & HF_LMA_MASK)
2566 raise_exception_err(EXCP0D_GPF, 0);
2568 tss_selector = lduw_kernel(env->tr.base + 0);
2569 if (tss_selector & 4)
2570 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2571 if (load_segment(&e1, &e2, tss_selector) != 0)
2572 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2573 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2574 /* NOTE: we check both segment and busy TSS */
2576 raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2577 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2579 helper_ret_protected(shift, 1, 0);
2582 if (kqemu_is_ok(env)) {
2583 CC_OP = CC_OP_EFLAGS;
2584 env->exception_index = -1;
2590 void helper_lret_protected(int shift, int addend)
2592 helper_ret_protected(shift, 0, addend);
2594 if (kqemu_is_ok(env)) {
2595 env->exception_index = -1;
2601 void helper_sysenter(void)
2603 if (env->sysenter_cs == 0) {
2604 raise_exception_err(EXCP0D_GPF, 0);
2606 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2607 cpu_x86_set_cpl(env, 0);
2608 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2610 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2612 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2613 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2615 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2617 DESC_W_MASK | DESC_A_MASK);
2618 ESP = env->sysenter_esp;
2619 EIP = env->sysenter_eip;
2622 void helper_sysexit(void)
2626 cpl = env->hflags & HF_CPL_MASK;
2627 if (env->sysenter_cs == 0 || cpl != 0) {
2628 raise_exception_err(EXCP0D_GPF, 0);
2630 cpu_x86_set_cpl(env, 3);
2631 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | 3,
2633 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2634 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2635 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2636 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | 3,
2638 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2639 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2640 DESC_W_MASK | DESC_A_MASK);
2644 if (kqemu_is_ok(env)) {
2645 env->exception_index = -1;
2651 void helper_movl_crN_T0(int reg)
2653 #if !defined(CONFIG_USER_ONLY)
2656 cpu_x86_update_cr0(env, T0);
2659 cpu_x86_update_cr3(env, T0);
2662 cpu_x86_update_cr4(env, T0);
2665 cpu_set_apic_tpr(env, T0);
2675 void helper_movl_drN_T0(int reg)
2680 void helper_invlpg(target_ulong addr)
2682 cpu_x86_flush_tlb(env, addr);
2685 void helper_rdtsc(void)
2689 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2690 raise_exception(EXCP0D_GPF);
2692 val = cpu_get_tsc(env);
2693 EAX = (uint32_t)(val);
2694 EDX = (uint32_t)(val >> 32);
2697 #if defined(CONFIG_USER_ONLY)
2698 void helper_wrmsr(void)
2702 void helper_rdmsr(void)
2706 void helper_wrmsr(void)
2710 val = ((uint32_t)EAX) | ((uint64_t)((uint32_t)EDX) << 32);
2712 switch((uint32_t)ECX) {
2713 case MSR_IA32_SYSENTER_CS:
2714 env->sysenter_cs = val & 0xffff;
2716 case MSR_IA32_SYSENTER_ESP:
2717 env->sysenter_esp = val;
2719 case MSR_IA32_SYSENTER_EIP:
2720 env->sysenter_eip = val;
2722 case MSR_IA32_APICBASE:
2723 cpu_set_apic_base(env, val);
2727 uint64_t update_mask;
2729 if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
2730 update_mask |= MSR_EFER_SCE;
2731 if (env->cpuid_ext2_features & CPUID_EXT2_LM)
2732 update_mask |= MSR_EFER_LME;
2733 if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
2734 update_mask |= MSR_EFER_FFXSR;
2735 if (env->cpuid_ext2_features & CPUID_EXT2_NX)
2736 update_mask |= MSR_EFER_NXE;
2737 env->efer = (env->efer & ~update_mask) |
2738 (val & update_mask);
2747 #ifdef TARGET_X86_64
2758 env->segs[R_FS].base = val;
2761 env->segs[R_GS].base = val;
2763 case MSR_KERNELGSBASE:
2764 env->kernelgsbase = val;
2768 /* XXX: exception ? */
2773 void helper_rdmsr(void)
2776 switch((uint32_t)ECX) {
2777 case MSR_IA32_SYSENTER_CS:
2778 val = env->sysenter_cs;
2780 case MSR_IA32_SYSENTER_ESP:
2781 val = env->sysenter_esp;
2783 case MSR_IA32_SYSENTER_EIP:
2784 val = env->sysenter_eip;
2786 case MSR_IA32_APICBASE:
2787 val = cpu_get_apic_base(env);
2798 #ifdef TARGET_X86_64
2809 val = env->segs[R_FS].base;
2812 val = env->segs[R_GS].base;
2814 case MSR_KERNELGSBASE:
2815 val = env->kernelgsbase;
2819 /* XXX: exception ? */
2823 EAX = (uint32_t)(val);
2824 EDX = (uint32_t)(val >> 32);
2828 void helper_lsl(void)
2830 unsigned int selector, limit;
2831 uint32_t e1, e2, eflags;
2832 int rpl, dpl, cpl, type;
2834 eflags = cc_table[CC_OP].compute_all();
2835 selector = T0 & 0xffff;
2836 if (load_segment(&e1, &e2, selector) != 0)
2839 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2840 cpl = env->hflags & HF_CPL_MASK;
2841 if (e2 & DESC_S_MASK) {
2842 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2845 if (dpl < cpl || dpl < rpl)
2849 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2860 if (dpl < cpl || dpl < rpl) {
2862 CC_SRC = eflags & ~CC_Z;
2866 limit = get_seg_limit(e1, e2);
2868 CC_SRC = eflags | CC_Z;
2871 void helper_lar(void)
2873 unsigned int selector;
2874 uint32_t e1, e2, eflags;
2875 int rpl, dpl, cpl, type;
2877 eflags = cc_table[CC_OP].compute_all();
2878 selector = T0 & 0xffff;
2879 if ((selector & 0xfffc) == 0)
2881 if (load_segment(&e1, &e2, selector) != 0)
2884 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2885 cpl = env->hflags & HF_CPL_MASK;
2886 if (e2 & DESC_S_MASK) {
2887 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2890 if (dpl < cpl || dpl < rpl)
2894 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2908 if (dpl < cpl || dpl < rpl) {
2910 CC_SRC = eflags & ~CC_Z;
2914 T1 = e2 & 0x00f0ff00;
2915 CC_SRC = eflags | CC_Z;
2918 void helper_verr(void)
2920 unsigned int selector;
2921 uint32_t e1, e2, eflags;
2924 eflags = cc_table[CC_OP].compute_all();
2925 selector = T0 & 0xffff;
2926 if ((selector & 0xfffc) == 0)
2928 if (load_segment(&e1, &e2, selector) != 0)
2930 if (!(e2 & DESC_S_MASK))
2933 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2934 cpl = env->hflags & HF_CPL_MASK;
2935 if (e2 & DESC_CS_MASK) {
2936 if (!(e2 & DESC_R_MASK))
2938 if (!(e2 & DESC_C_MASK)) {
2939 if (dpl < cpl || dpl < rpl)
2943 if (dpl < cpl || dpl < rpl) {
2945 CC_SRC = eflags & ~CC_Z;
2949 CC_SRC = eflags | CC_Z;
2952 void helper_verw(void)
2954 unsigned int selector;
2955 uint32_t e1, e2, eflags;
2958 eflags = cc_table[CC_OP].compute_all();
2959 selector = T0 & 0xffff;
2960 if ((selector & 0xfffc) == 0)
2962 if (load_segment(&e1, &e2, selector) != 0)
2964 if (!(e2 & DESC_S_MASK))
2967 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2968 cpl = env->hflags & HF_CPL_MASK;
2969 if (e2 & DESC_CS_MASK) {
2972 if (dpl < cpl || dpl < rpl)
2974 if (!(e2 & DESC_W_MASK)) {
2976 CC_SRC = eflags & ~CC_Z;
2980 CC_SRC = eflags | CC_Z;
2985 void helper_fldt_ST0_A0(void)
2988 new_fpstt = (env->fpstt - 1) & 7;
2989 env->fpregs[new_fpstt].d = helper_fldt(A0);
2990 env->fpstt = new_fpstt;
2991 env->fptags[new_fpstt] = 0; /* validate stack entry */
2994 void helper_fstt_ST0_A0(void)
2996 helper_fstt(ST0, A0);
2999 void fpu_set_exception(int mask)
3002 if (env->fpus & (~env->fpuc & FPUC_EM))
3003 env->fpus |= FPUS_SE | FPUS_B;
3006 CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
3009 fpu_set_exception(FPUS_ZE);
3013 void fpu_raise_exception(void)
3015 if (env->cr[0] & CR0_NE_MASK) {
3016 raise_exception(EXCP10_COPR);
3018 #if !defined(CONFIG_USER_ONLY)
3027 void helper_fbld_ST0_A0(void)
3035 for(i = 8; i >= 0; i--) {
3037 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
3040 if (ldub(A0 + 9) & 0x80)
3046 void helper_fbst_ST0_A0(void)
3049 target_ulong mem_ref, mem_end;
3052 val = floatx_to_int64(ST0, &env->fp_status);
3054 mem_end = mem_ref + 9;
3061 while (mem_ref < mem_end) {
3066 v = ((v / 10) << 4) | (v % 10);
3069 while (mem_ref < mem_end) {
3074 void helper_f2xm1(void)
3076 ST0 = pow(2.0,ST0) - 1.0;
3079 void helper_fyl2x(void)
3081 CPU86_LDouble fptemp;
3085 fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3089 env->fpus &= (~0x4700);
3094 void helper_fptan(void)
3096 CPU86_LDouble fptemp;
3099 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3105 env->fpus &= (~0x400); /* C2 <-- 0 */
3106 /* the above code is for |arg| < 2**52 only */
3110 void helper_fpatan(void)
3112 CPU86_LDouble fptemp, fpsrcop;
3116 ST1 = atan2(fpsrcop,fptemp);
3120 void helper_fxtract(void)
3122 CPU86_LDoubleU temp;
3123 unsigned int expdif;
3126 expdif = EXPD(temp) - EXPBIAS;
3127 /*DP exponent bias*/
3134 void helper_fprem1(void)
3136 CPU86_LDouble dblq, fpsrcop, fptemp;
3137 CPU86_LDoubleU fpsrcop1, fptemp1;
3143 fpsrcop1.d = fpsrcop;
3145 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3147 dblq = fpsrcop / fptemp;
3148 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3149 ST0 = fpsrcop - fptemp*dblq;
3150 q = (int)dblq; /* cutting off top bits is assumed here */
3151 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3152 /* (C0,C1,C3) <-- (q2,q1,q0) */
3153 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
3154 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
3155 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
3157 env->fpus |= 0x400; /* C2 <-- 1 */
3158 fptemp = pow(2.0, expdif-50);
3159 fpsrcop = (ST0 / ST1) / fptemp;
3160 /* fpsrcop = integer obtained by rounding to the nearest */
3161 fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3162 floor(fpsrcop): ceil(fpsrcop);
3163 ST0 -= (ST1 * fpsrcop * fptemp);
3167 void helper_fprem(void)
3169 CPU86_LDouble dblq, fpsrcop, fptemp;
3170 CPU86_LDoubleU fpsrcop1, fptemp1;
3176 fpsrcop1.d = fpsrcop;
3178 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3179 if ( expdif < 53 ) {
3180 dblq = fpsrcop / fptemp;
3181 dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3182 ST0 = fpsrcop - fptemp*dblq;
3183 q = (int)dblq; /* cutting off top bits is assumed here */
3184 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3185 /* (C0,C1,C3) <-- (q2,q1,q0) */
3186 env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
3187 env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
3188 env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
3190 env->fpus |= 0x400; /* C2 <-- 1 */
3191 fptemp = pow(2.0, expdif-50);
3192 fpsrcop = (ST0 / ST1) / fptemp;
3193 /* fpsrcop = integer obtained by chopping */
3194 fpsrcop = (fpsrcop < 0.0)?
3195 -(floor(fabs(fpsrcop))): floor(fpsrcop);
3196 ST0 -= (ST1 * fpsrcop * fptemp);
3200 void helper_fyl2xp1(void)
3202 CPU86_LDouble fptemp;
3205 if ((fptemp+1.0)>0.0) {
3206 fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3210 env->fpus &= (~0x4700);
3215 void helper_fsqrt(void)
3217 CPU86_LDouble fptemp;
3221 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3227 void helper_fsincos(void)
3229 CPU86_LDouble fptemp;
3232 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3238 env->fpus &= (~0x400); /* C2 <-- 0 */
3239 /* the above code is for |arg| < 2**63 only */
3243 void helper_frndint(void)
3245 ST0 = floatx_round_to_int(ST0, &env->fp_status);
3248 void helper_fscale(void)
3250 ST0 = ldexp (ST0, (int)(ST1));
3253 void helper_fsin(void)
3255 CPU86_LDouble fptemp;
3258 if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3262 env->fpus &= (~0x400); /* C2 <-- 0 */
3263 /* the above code is for |arg| < 2**53 only */
3267 void helper_fcos(void)
3269 CPU86_LDouble fptemp;
3272 if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
3276 env->fpus &= (~0x400); /* C2 <-- 0 */
3277 /* the above code is for |arg5 < 2**63 only */
3281 void helper_fxam_ST0(void)
3283 CPU86_LDoubleU temp;
3288 env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3290 env->fpus |= 0x200; /* C1 <-- 1 */
3292 /* XXX: test fptags too */
3293 expdif = EXPD(temp);
3294 if (expdif == MAXEXPD) {
3295 #ifdef USE_X86LDOUBLE
3296 if (MANTD(temp) == 0x8000000000000000ULL)
3298 if (MANTD(temp) == 0)
3300 env->fpus |= 0x500 /*Infinity*/;
3302 env->fpus |= 0x100 /*NaN*/;
3303 } else if (expdif == 0) {
3304 if (MANTD(temp) == 0)
3305 env->fpus |= 0x4000 /*Zero*/;
3307 env->fpus |= 0x4400 /*Denormal*/;
3313 void helper_fstenv(target_ulong ptr, int data32)
3315 int fpus, fptag, exp, i;
3319 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3321 for (i=7; i>=0; i--) {
3323 if (env->fptags[i]) {
3326 tmp.d = env->fpregs[i].d;
3329 if (exp == 0 && mant == 0) {
3332 } else if (exp == 0 || exp == MAXEXPD
3333 #ifdef USE_X86LDOUBLE
3334 || (mant & (1LL << 63)) == 0
3337 /* NaNs, infinity, denormal */
3344 stl(ptr, env->fpuc);
3346 stl(ptr + 8, fptag);
3347 stl(ptr + 12, 0); /* fpip */
3348 stl(ptr + 16, 0); /* fpcs */
3349 stl(ptr + 20, 0); /* fpoo */
3350 stl(ptr + 24, 0); /* fpos */
3353 stw(ptr, env->fpuc);
3355 stw(ptr + 4, fptag);
3363 void helper_fldenv(target_ulong ptr, int data32)
3368 env->fpuc = lduw(ptr);
3369 fpus = lduw(ptr + 4);
3370 fptag = lduw(ptr + 8);
3373 env->fpuc = lduw(ptr);
3374 fpus = lduw(ptr + 2);
3375 fptag = lduw(ptr + 4);
3377 env->fpstt = (fpus >> 11) & 7;
3378 env->fpus = fpus & ~0x3800;
3379 for(i = 0;i < 8; i++) {
3380 env->fptags[i] = ((fptag & 3) == 3);
3385 void helper_fsave(target_ulong ptr, int data32)
3390 helper_fstenv(ptr, data32);
3392 ptr += (14 << data32);
3393 for(i = 0;i < 8; i++) {
3395 helper_fstt(tmp, ptr);
3413 void helper_frstor(target_ulong ptr, int data32)
3418 helper_fldenv(ptr, data32);
3419 ptr += (14 << data32);
3421 for(i = 0;i < 8; i++) {
3422 tmp = helper_fldt(ptr);
3428 void helper_fxsave(target_ulong ptr, int data64)
3430 int fpus, fptag, i, nb_xmm_regs;
3434 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
3436 for(i = 0; i < 8; i++) {
3437 fptag |= (env->fptags[i] << i);
3439 stw(ptr, env->fpuc);
3441 stw(ptr + 4, fptag ^ 0xff);
3444 for(i = 0;i < 8; i++) {
3446 helper_fstt(tmp, addr);
3450 if (env->cr[4] & CR4_OSFXSR_MASK) {
3451 /* XXX: finish it */
3452 stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3453 stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3454 nb_xmm_regs = 8 << data64;
3456 for(i = 0; i < nb_xmm_regs; i++) {
3457 stq(addr, env->xmm_regs[i].XMM_Q(0));
3458 stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3464 void helper_fxrstor(target_ulong ptr, int data64)
3466 int i, fpus, fptag, nb_xmm_regs;
3470 env->fpuc = lduw(ptr);
3471 fpus = lduw(ptr + 2);
3472 fptag = lduw(ptr + 4);
3473 env->fpstt = (fpus >> 11) & 7;
3474 env->fpus = fpus & ~0x3800;
3476 for(i = 0;i < 8; i++) {
3477 env->fptags[i] = ((fptag >> i) & 1);
3481 for(i = 0;i < 8; i++) {
3482 tmp = helper_fldt(addr);
3487 if (env->cr[4] & CR4_OSFXSR_MASK) {
3488 /* XXX: finish it */
3489 env->mxcsr = ldl(ptr + 0x18);
3491 nb_xmm_regs = 8 << data64;
3493 for(i = 0; i < nb_xmm_regs; i++) {
3494 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3495 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3501 #ifndef USE_X86LDOUBLE
3503 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3505 CPU86_LDoubleU temp;
3510 *pmant = (MANTD(temp) << 11) | (1LL << 63);
3511 /* exponent + sign */
3512 e = EXPD(temp) - EXPBIAS + 16383;
3513 e |= SIGND(temp) >> 16;
3517 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3519 CPU86_LDoubleU temp;
3523 /* XXX: handle overflow ? */
3524 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3525 e |= (upper >> 4) & 0x800; /* sign */
3526 ll = (mant >> 11) & ((1LL << 52) - 1);
3528 temp.l.upper = (e << 20) | (ll >> 32);
3531 temp.ll = ll | ((uint64_t)e << 52);
3538 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f)
3540 CPU86_LDoubleU temp;
3543 *pmant = temp.l.lower;
3544 *pexp = temp.l.upper;
3547 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3549 CPU86_LDoubleU temp;
3551 temp.l.upper = upper;
3552 temp.l.lower = mant;
3557 #ifdef TARGET_X86_64
3559 //#define DEBUG_MULDIV
3561 static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3570 static void neg128(uint64_t *plow, uint64_t *phigh)
3574 add128(plow, phigh, 1, 0);
3577 static void mul64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
3579 uint32_t a0, a1, b0, b1;
3588 v = (uint64_t)a0 * (uint64_t)b0;
3592 v = (uint64_t)a0 * (uint64_t)b1;
3593 add128(plow, phigh, v << 32, v >> 32);
3595 v = (uint64_t)a1 * (uint64_t)b0;
3596 add128(plow, phigh, v << 32, v >> 32);
3598 v = (uint64_t)a1 * (uint64_t)b1;
3601 printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
3602 a, b, *phigh, *plow);
3606 static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
3615 mul64(plow, phigh, a, b);
3617 neg128(plow, phigh);
3621 /* return TRUE if overflow */
3622 static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
3624 uint64_t q, r, a1, a0;
3637 /* XXX: use a better algorithm */
3638 for(i = 0; i < 64; i++) {
3640 a1 = (a1 << 1) | (a0 >> 63);
3641 if (ab || a1 >= b) {
3647 a0 = (a0 << 1) | qb;
3649 #if defined(DEBUG_MULDIV)
3650 printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
3651 *phigh, *plow, b, a0, a1);
3659 /* return TRUE if overflow */
3660 static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
3663 sa = ((int64_t)*phigh < 0);
3665 neg128(plow, phigh);
3669 if (div64(plow, phigh, b) != 0)
3672 if (*plow > (1ULL << 63))
3676 if (*plow >= (1ULL << 63))
3684 void helper_mulq_EAX_T0(void)
3688 mul64(&r0, &r1, EAX, T0);
3695 void helper_imulq_EAX_T0(void)
3699 imul64(&r0, &r1, EAX, T0);
3703 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3706 void helper_imulq_T0_T1(void)
3710 imul64(&r0, &r1, T0, T1);
3713 CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
3716 void helper_divq_EAX_T0(void)
3720 raise_exception(EXCP00_DIVZ);
3724 if (div64(&r0, &r1, T0))
3725 raise_exception(EXCP00_DIVZ);
3730 void helper_idivq_EAX_T0(void)
3734 raise_exception(EXCP00_DIVZ);
3738 if (idiv64(&r0, &r1, T0))
3739 raise_exception(EXCP00_DIVZ);
3744 void helper_bswapq_T0(void)
3750 void helper_hlt(void)
3752 env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
3753 env->hflags |= HF_HALTED_MASK;
3754 env->exception_index = EXCP_HLT;
3758 void helper_monitor(void)
3760 if ((uint32_t)ECX != 0)
3761 raise_exception(EXCP0D_GPF);
3762 /* XXX: store address ? */
3765 void helper_mwait(void)
3767 if ((uint32_t)ECX != 0)
3768 raise_exception(EXCP0D_GPF);
3769 /* XXX: not complete but not completely erroneous */
3770 if (env->cpu_index != 0 || env->next_cpu != NULL) {
3771 /* more than one CPU: do not sleep because another CPU may
3778 float approx_rsqrt(float a)
3780 return 1.0 / sqrt(a);
3783 float approx_rcp(float a)
3788 void update_fp_status(void)
3792 /* set rounding mode */
3793 switch(env->fpuc & RC_MASK) {
3796 rnd_type = float_round_nearest_even;
3799 rnd_type = float_round_down;
3802 rnd_type = float_round_up;
3805 rnd_type = float_round_to_zero;
3808 set_float_rounding_mode(rnd_type, &env->fp_status);
3810 switch((env->fpuc >> 8) & 3) {
3822 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
3826 #if !defined(CONFIG_USER_ONLY)
3828 #define MMUSUFFIX _mmu
3829 #define GETPC() (__builtin_return_address(0))
3832 #include "softmmu_template.h"
3835 #include "softmmu_template.h"
3838 #include "softmmu_template.h"
3841 #include "softmmu_template.h"
3845 /* try to fill the TLB and return an exception if error. If retaddr is
3846 NULL, it means that the function was called in C code (i.e. not
3847 from generated code or from helper.c) */
3848 /* XXX: fix it to restore all registers */
3849 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
3851 TranslationBlock *tb;
3854 CPUX86State *saved_env;
3856 /* XXX: hack to restore env in all cases, even if not called from
3859 env = cpu_single_env;
3861 ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
3864 /* now we have a real cpu fault */
3865 pc = (unsigned long)retaddr;
3866 tb = tb_find_pc(pc);
3868 /* the PC is inside the translated code. It means that we have
3869 a virtual CPU fault */
3870 cpu_restore_state(tb, env, pc, NULL);
3874 raise_exception_err(env->exception_index, env->error_code);
3876 raise_exception_err_norestore(env->exception_index, env->error_code);