4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #define DATA_SIZE (1 << SHIFT)
25 #define DATA_TYPE uint64_t
29 #define DATA_TYPE uint32_t
33 #define DATA_TYPE uint16_t
37 #define DATA_TYPE uint8_t
39 #error unsupported data size
42 #ifdef SOFTMMU_CODE_ACCESS
43 #define READ_ACCESS_TYPE 2
44 #define ADDR_READ addr_code
46 #define READ_ACCESS_TYPE 0
47 #define ADDR_READ addr_read
50 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
53 static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
58 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
59 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
62 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
64 #ifdef TARGET_WORDS_BIGENDIAN
65 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
66 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
68 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
69 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
71 #endif /* SHIFT > 2 */
73 env->last_io_time = cpu_get_time_fast();
78 /* handle all cases except unaligned access which span two pages */
79 DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
84 target_ulong tlb_addr;
85 target_phys_addr_t addend;
88 /* test if there is match for unaligned or IO access */
89 /* XXX: could done more in memory macro in a non portable way */
90 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
92 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
93 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
94 if (tlb_addr & ~TARGET_PAGE_MASK) {
96 if ((addr & (DATA_SIZE - 1)) != 0)
97 goto do_unaligned_access;
98 addend = env->iotlb[mmu_idx][index];
99 res = glue(io_read, SUFFIX)(addend, addr);
100 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
101 /* slow unaligned access (it spans two pages or IO) */
105 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
107 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
110 /* unaligned/aligned access in the same page */
112 if ((addr & (DATA_SIZE - 1)) != 0) {
114 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
117 addend = env->tlb_table[mmu_idx][index].addend;
118 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
121 /* the page is not in the TLB : fill it */
124 if ((addr & (DATA_SIZE - 1)) != 0)
125 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
127 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
133 /* handle all unaligned cases */
134 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
138 DATA_TYPE res, res1, res2;
140 target_phys_addr_t addend;
141 target_ulong tlb_addr, addr1, addr2;
143 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
145 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
146 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
147 if (tlb_addr & ~TARGET_PAGE_MASK) {
149 if ((addr & (DATA_SIZE - 1)) != 0)
150 goto do_unaligned_access;
151 addend = env->iotlb[mmu_idx][index];
152 res = glue(io_read, SUFFIX)(addend, addr);
153 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
155 /* slow unaligned access (it spans two pages) */
156 addr1 = addr & ~(DATA_SIZE - 1);
157 addr2 = addr1 + DATA_SIZE;
158 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
160 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
162 shift = (addr & (DATA_SIZE - 1)) * 8;
163 #ifdef TARGET_WORDS_BIGENDIAN
164 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
166 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
168 res = (DATA_TYPE)res;
170 /* unaligned/aligned access in the same page */
171 addend = env->tlb_table[mmu_idx][index].addend;
172 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
175 /* the page is not in the TLB : fill it */
176 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
182 #ifndef SOFTMMU_CODE_ACCESS
184 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
189 static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
195 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
196 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
198 env->mem_write_vaddr = addr;
199 env->mem_write_pc = (unsigned long)retaddr;
201 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
203 #ifdef TARGET_WORDS_BIGENDIAN
204 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
205 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
207 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
208 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
210 #endif /* SHIFT > 2 */
212 env->last_io_time = cpu_get_time_fast();
216 void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
220 target_phys_addr_t addend;
221 target_ulong tlb_addr;
225 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
227 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
228 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
229 if (tlb_addr & ~TARGET_PAGE_MASK) {
231 if ((addr & (DATA_SIZE - 1)) != 0)
232 goto do_unaligned_access;
234 addend = env->iotlb[mmu_idx][index];
235 glue(io_write, SUFFIX)(addend, val, addr, retaddr);
236 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
240 do_unaligned_access(addr, 1, mmu_idx, retaddr);
242 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
245 /* aligned/unaligned access in the same page */
247 if ((addr & (DATA_SIZE - 1)) != 0) {
249 do_unaligned_access(addr, 1, mmu_idx, retaddr);
252 addend = env->tlb_table[mmu_idx][index].addend;
253 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
256 /* the page is not in the TLB : fill it */
259 if ((addr & (DATA_SIZE - 1)) != 0)
260 do_unaligned_access(addr, 1, mmu_idx, retaddr);
262 tlb_fill(addr, 1, mmu_idx, retaddr);
267 /* handles all unaligned cases */
268 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
273 target_phys_addr_t addend;
274 target_ulong tlb_addr;
277 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
279 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
280 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
281 if (tlb_addr & ~TARGET_PAGE_MASK) {
283 if ((addr & (DATA_SIZE - 1)) != 0)
284 goto do_unaligned_access;
285 addend = env->iotlb[mmu_idx][index];
286 glue(io_write, SUFFIX)(addend, val, addr, retaddr);
287 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
289 /* XXX: not efficient, but simple */
290 /* Note: relies on the fact that tlb_fill() does not remove the
291 * previous page from the TLB cache. */
292 for(i = DATA_SIZE - 1; i >= 0; i--) {
293 #ifdef TARGET_WORDS_BIGENDIAN
294 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
297 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
302 /* aligned/unaligned access in the same page */
303 addend = env->tlb_table[mmu_idx][index].addend;
304 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
307 /* the page is not in the TLB : fill it */
308 tlb_fill(addr, 1, mmu_idx, retaddr);
313 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
315 #undef READ_ACCESS_TYPE