4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define DATA_TYPE uint64_t
27 #define DATA_TYPE uint32_t
31 #define DATA_TYPE uint16_t
32 #define DATA_STYPE int16_t
36 #define DATA_TYPE uint8_t
37 #define DATA_STYPE int8_t
39 #error unsupported data size
44 #define CPU_MEM_INDEX 0
45 #define MMUSUFFIX _mmu
47 #elif ACCESS_TYPE == 1
49 #define CPU_MEM_INDEX 1
50 #define MMUSUFFIX _mmu
52 #elif ACCESS_TYPE == 2
55 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
56 #elif defined (TARGET_PPC)
57 #define CPU_MEM_INDEX (msr_pr)
58 #elif defined (TARGET_MIPS)
59 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
60 #elif defined (TARGET_SPARC)
61 #define CPU_MEM_INDEX ((env->psrs) == 0)
62 #elif defined (TARGET_ARM)
63 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
64 #elif defined (TARGET_SH4)
65 #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
66 #elif defined (TARGET_ALPHA)
67 #define CPU_MEM_INDEX ((env->ps >> 3) & 3)
69 #error unsupported CPU
71 #define MMUSUFFIX _mmu
73 #elif ACCESS_TYPE == 3
76 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
77 #elif defined (TARGET_PPC)
78 #define CPU_MEM_INDEX (msr_pr)
79 #elif defined (TARGET_MIPS)
80 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
81 #elif defined (TARGET_SPARC)
82 #define CPU_MEM_INDEX ((env->psrs) == 0)
83 #elif defined (TARGET_ARM)
84 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
85 #elif defined (TARGET_SH4)
86 #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
87 #elif defined (TARGET_ALPHA)
88 #define CPU_MEM_INDEX ((env->ps >> 3) & 3)
90 #error unsupported CPU
92 #define MMUSUFFIX _cmmu
95 #error invalid ACCESS_TYPE
99 #define RES_TYPE uint64_t
105 #define ADDR_READ addr_code
107 #define ADDR_READ addr_read
110 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
112 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
114 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
115 (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
117 #define CPU_TLB_ENTRY_BITS 4
119 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
123 asm volatile ("movl %1, %%edx\n"
128 "leal %5(%%edx, %%ebp), %%edx\n"
129 "cmpl (%%edx), %%eax\n"
138 "addl 12(%%edx), %%eax\n"
140 "movzbl (%%eax), %0\n"
142 "movzwl (%%eax), %0\n"
146 #error unsupported size
151 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
152 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
153 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
154 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
156 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
157 : "%eax", "%ecx", "%edx", "memory", "cc");
162 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
166 asm volatile ("movl %1, %%edx\n"
171 "leal %5(%%edx, %%ebp), %%edx\n"
172 "cmpl (%%edx), %%eax\n"
183 #error unsupported size
187 "addl 12(%%edx), %%eax\n"
189 "movsbl (%%eax), %0\n"
191 "movswl (%%eax), %0\n"
193 #error unsupported size
198 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
199 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
200 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
201 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
203 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
204 : "%eax", "%ecx", "%edx", "memory", "cc");
209 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
211 asm volatile ("movl %0, %%edx\n"
216 "leal %5(%%edx, %%ebp), %%edx\n"
217 "cmpl (%%edx), %%eax\n"
221 "movzbl %b1, %%edx\n"
223 "movzwl %w1, %%edx\n"
227 #error unsupported size
234 "addl 8(%%edx), %%eax\n"
236 "movb %b1, (%%eax)\n"
238 "movw %w1, (%%eax)\n"
242 #error unsupported size
247 /* NOTE: 'q' would be needed as constraint, but we could not use it
250 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
251 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
252 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
253 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
255 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
256 : "%eax", "%ecx", "%edx", "memory", "cc");
261 /* generic load/store macros */
263 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
268 unsigned long physaddr;
272 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
273 is_user = CPU_MEM_INDEX;
274 if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
275 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
276 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
278 physaddr = addr + env->tlb_table[is_user][index].addend;
279 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
285 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
289 unsigned long physaddr;
293 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
294 is_user = CPU_MEM_INDEX;
295 if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
296 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
297 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
299 physaddr = addr + env->tlb_table[is_user][index].addend;
300 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
308 /* generic store macro */
310 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
314 unsigned long physaddr;
318 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
319 is_user = CPU_MEM_INDEX;
320 if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
321 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
322 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
324 physaddr = addr + env->tlb_table[is_user][index].addend;
325 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
329 #endif /* ACCESS_TYPE != 3 */
336 static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
342 u.i = glue(ldq, MEMSUFFIX)(ptr);
346 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
353 glue(stq, MEMSUFFIX)(ptr, u.i);
355 #endif /* DATA_SIZE == 8 */
358 static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
364 u.i = glue(ldl, MEMSUFFIX)(ptr);
368 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
375 glue(stl, MEMSUFFIX)(ptr, u.i);
377 #endif /* DATA_SIZE == 4 */
379 #endif /* ACCESS_TYPE != 3 */