4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define DATA_TYPE uint64_t
27 #define DATA_TYPE uint32_t
31 #define DATA_TYPE uint16_t
32 #define DATA_STYPE int16_t
36 #define DATA_TYPE uint8_t
37 #define DATA_STYPE int8_t
39 #error unsupported data size
44 #define CPU_MEM_INDEX 0
45 #define MMUSUFFIX _mmu
47 #elif ACCESS_TYPE == 1
49 #define CPU_MEM_INDEX 1
50 #define MMUSUFFIX _mmu
52 #elif ACCESS_TYPE == 2
55 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
56 #elif defined (TARGET_PPC)
57 #define CPU_MEM_INDEX (msr_pr)
58 #elif defined (TARGET_MIPS)
59 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
60 #elif defined (TARGET_SPARC)
61 #define CPU_MEM_INDEX ((env->psrs) == 0)
62 #elif defined (TARGET_ARM)
63 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
64 #elif defined (TARGET_SH4)
65 #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
66 #elif defined (TARGET_ALPHA)
67 #define CPU_MEM_INDEX ((env->ps >> 3) & 3)
68 #elif defined (TARGET_M68K)
69 #define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
70 #elif defined (TARGET_CRIS)
71 /* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */
72 #define CPU_MEM_INDEX (0)
74 #error unsupported CPU
76 #define MMUSUFFIX _mmu
78 #elif ACCESS_TYPE == 3
81 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
82 #elif defined (TARGET_PPC)
83 #define CPU_MEM_INDEX (msr_pr)
84 #elif defined (TARGET_MIPS)
85 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
86 #elif defined (TARGET_SPARC)
87 #define CPU_MEM_INDEX ((env->psrs) == 0)
88 #elif defined (TARGET_ARM)
89 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
90 #elif defined (TARGET_SH4)
91 #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
92 #elif defined (TARGET_ALPHA)
93 #define CPU_MEM_INDEX ((env->ps >> 3) & 3)
94 #elif defined (TARGET_M68K)
95 #define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
96 #elif defined (TARGET_CRIS)
97 /* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */
98 #define CPU_MEM_INDEX (0)
100 #error unsupported CPU
102 #define MMUSUFFIX _cmmu
105 #error invalid ACCESS_TYPE
109 #define RES_TYPE uint64_t
115 #define ADDR_READ addr_code
117 #define ADDR_READ addr_read
120 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
122 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
124 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
125 (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
127 #define CPU_TLB_ENTRY_BITS 4
129 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
133 asm volatile ("movl %1, %%edx\n"
138 "leal %5(%%edx, %%ebp), %%edx\n"
139 "cmpl (%%edx), %%eax\n"
148 "addl 12(%%edx), %%eax\n"
150 "movzbl (%%eax), %0\n"
152 "movzwl (%%eax), %0\n"
156 #error unsupported size
161 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
162 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
163 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
164 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
166 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
167 : "%eax", "%ecx", "%edx", "memory", "cc");
172 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
176 asm volatile ("movl %1, %%edx\n"
181 "leal %5(%%edx, %%ebp), %%edx\n"
182 "cmpl (%%edx), %%eax\n"
193 #error unsupported size
197 "addl 12(%%edx), %%eax\n"
199 "movsbl (%%eax), %0\n"
201 "movswl (%%eax), %0\n"
203 #error unsupported size
208 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
209 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
210 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
211 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
213 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
214 : "%eax", "%ecx", "%edx", "memory", "cc");
219 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
221 asm volatile ("movl %0, %%edx\n"
226 "leal %5(%%edx, %%ebp), %%edx\n"
227 "cmpl (%%edx), %%eax\n"
231 "movzbl %b1, %%edx\n"
233 "movzwl %w1, %%edx\n"
237 #error unsupported size
244 "addl 8(%%edx), %%eax\n"
246 "movb %b1, (%%eax)\n"
248 "movw %w1, (%%eax)\n"
252 #error unsupported size
257 /* NOTE: 'q' would be needed as constraint, but we could not use it
260 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
261 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
262 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
263 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
265 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
266 : "%eax", "%ecx", "%edx", "memory", "cc");
271 /* generic load/store macros */
273 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
278 unsigned long physaddr;
282 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
283 is_user = CPU_MEM_INDEX;
284 if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
285 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
286 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
288 physaddr = addr + env->tlb_table[is_user][index].addend;
289 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
295 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
299 unsigned long physaddr;
303 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
304 is_user = CPU_MEM_INDEX;
305 if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
306 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
307 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
309 physaddr = addr + env->tlb_table[is_user][index].addend;
310 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
318 /* generic store macro */
320 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
324 unsigned long physaddr;
328 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
329 is_user = CPU_MEM_INDEX;
330 if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
331 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
332 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
334 physaddr = addr + env->tlb_table[is_user][index].addend;
335 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
339 #endif /* ACCESS_TYPE != 3 */
346 static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
352 u.i = glue(ldq, MEMSUFFIX)(ptr);
356 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
363 glue(stq, MEMSUFFIX)(ptr, u.i);
365 #endif /* DATA_SIZE == 8 */
368 static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
374 u.i = glue(ldl, MEMSUFFIX)(ptr);
378 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
385 glue(stl, MEMSUFFIX)(ptr, u.i);
387 #endif /* DATA_SIZE == 4 */
389 #endif /* ACCESS_TYPE != 3 */