1 #if !defined(__QEMU_MIPS_EXEC_H__)
2 #define __QEMU_MIPS_EXEC_H__
7 #include "dyngen-exec.h"
9 register struct CPUMIPSState *env asm(AREG0);
11 #if defined (USE_64BITS_REGS)
12 typedef int64_t host_int_t;
13 typedef uint64_t host_uint_t;
15 typedef int32_t host_int_t;
16 typedef uint32_t host_uint_t;
19 register host_uint_t T0 asm(AREG1);
20 register host_uint_t T1 asm(AREG2);
21 register host_uint_t T2 asm(AREG3);
23 #if defined (USE_HOST_FLOAT_REGS)
24 register double FT0 asm(FREG0);
25 register double FT1 asm(FREG1);
26 register double FT2 asm(FREG2);
28 #define FT0 (env->ft0.d)
29 #define FT1 (env->ft1.d)
30 #define FT2 (env->ft2.d)
33 #if defined (DEBUG_OP)
34 #define RETURN() __asm__ __volatile__("nop");
36 #define RETURN() __asm__ __volatile__("");
42 #if !defined(CONFIG_USER_ONLY)
44 #define ldul_user ldl_user
45 #define ldul_kernel ldl_kernel
48 #define MEMSUFFIX _kernel
50 #include "softmmu_header.h"
53 #include "softmmu_header.h"
56 #include "softmmu_header.h"
59 #include "softmmu_header.h"
64 #define MEMSUFFIX _user
66 #include "softmmu_header.h"
69 #include "softmmu_header.h"
72 #include "softmmu_header.h"
75 #include "softmmu_header.h"
79 /* these access are slower, they must be as rare as possible */
81 #define MEMSUFFIX _data
83 #include "softmmu_header.h"
86 #include "softmmu_header.h"
89 #include "softmmu_header.h"
92 #include "softmmu_header.h"
96 #define ldub(p) ldub_data(p)
97 #define ldsb(p) ldsb_data(p)
98 #define lduw(p) lduw_data(p)
99 #define ldsw(p) ldsw_data(p)
100 #define ldl(p) ldl_data(p)
101 #define ldq(p) ldq_data(p)
103 #define stb(p, v) stb_data(p, v)
104 #define stw(p, v) stw_data(p, v)
105 #define stl(p, v) stl_data(p, v)
106 #define stq(p, v) stq_data(p, v)
108 #endif /* !defined(CONFIG_USER_ONLY) */
110 static inline void env_to_regs(void)
114 static inline void regs_to_env(void)
118 #if (HOST_LONG_BITS == 32)
120 void do_multu (void);
122 void do_maddu (void);
124 void do_msubu (void);
126 void do_mfc0(int reg, int sel);
127 void do_mtc0(int reg, int sel);
128 void do_tlbwi (void);
129 void do_tlbwr (void);
132 void do_lwl_raw (void);
133 void do_lwr_raw (void);
134 void do_swl_raw (void);
135 void do_swr_raw (void);
136 #if !defined(CONFIG_USER_ONLY)
137 void do_lwl_user (void);
138 void do_lwl_kernel (void);
139 void do_lwr_user (void);
140 void do_lwr_kernel (void);
141 void do_swl_user (void);
142 void do_swl_kernel (void);
143 void do_swr_user (void);
144 void do_swr_kernel (void);
146 void do_pmon (int function);
148 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
149 int is_user, int is_softmmu);
150 void do_interrupt (CPUState *env);
152 void cpu_loop_exit(void);
153 void do_raise_exception_err (uint32_t exception, int error_code);
154 void do_raise_exception (uint32_t exception);
156 void cpu_dump_state(CPUState *env, FILE *f,
157 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
159 void cpu_mips_irqctrl_init (void);
160 uint32_t cpu_mips_get_random (CPUState *env);
161 uint32_t cpu_mips_get_count (CPUState *env);
162 void cpu_mips_store_count (CPUState *env, uint32_t value);
163 void cpu_mips_store_compare (CPUState *env, uint32_t value);
164 void cpu_mips_clock_init (CPUState *env);
166 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */