2 * QEMU NE2000 emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug NE2000 card */
27 //#define DEBUG_NE2000
29 #define MAX_ETH_FRAME_SIZE 1514
31 #define E8390_CMD 0x00 /* The command register (for all pages) */
32 /* Page 0 register offsets. */
33 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
34 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
35 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
36 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
37 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
38 #define EN0_TSR 0x04 /* Transmit status reg RD */
39 #define EN0_TPSR 0x04 /* Transmit starting page WR */
40 #define EN0_NCR 0x05 /* Number of collision reg RD */
41 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
42 #define EN0_FIFO 0x06 /* FIFO RD */
43 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
44 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
45 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
46 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
50 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
51 #define EN0_RSR 0x0c /* rx status reg RD */
52 #define EN0_RXCR 0x0c /* RX configuration reg WR */
53 #define EN0_TXCR 0x0d /* TX configuration reg WR */
54 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
55 #define EN0_DCFG 0x0e /* Data configuration reg WR */
56 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
57 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
58 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
61 #define EN1_CURPAG 0x17
64 /* Register accessed at EN_CMD, the 8390 base addr. */
65 #define E8390_STOP 0x01 /* Stop and reset the chip */
66 #define E8390_START 0x02 /* Start the chip, clear reset */
67 #define E8390_TRANS 0x04 /* Transmit a frame */
68 #define E8390_RREAD 0x08 /* Remote read */
69 #define E8390_RWRITE 0x10 /* Remote write */
70 #define E8390_NODMA 0x20 /* Remote DMA */
71 #define E8390_PAGE0 0x00 /* Select page chip registers */
72 #define E8390_PAGE1 0x40 /* using the two high-order bits */
73 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
75 /* Bits in EN0_ISR - Interrupt status register */
76 #define ENISR_RX 0x01 /* Receiver, no error */
77 #define ENISR_TX 0x02 /* Transmitter, no error */
78 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
79 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
80 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
81 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
82 #define ENISR_RDC 0x40 /* remote dma complete */
83 #define ENISR_RESET 0x80 /* Reset completed */
84 #define ENISR_ALL 0x3f /* Interrupts we will enable */
86 /* Bits in received packet status byte and EN0_RSR*/
87 #define ENRSR_RXOK 0x01 /* Received a good packet */
88 #define ENRSR_CRC 0x02 /* CRC error */
89 #define ENRSR_FAE 0x04 /* frame alignment error */
90 #define ENRSR_FO 0x08 /* FIFO overrun */
91 #define ENRSR_MPA 0x10 /* missed pkt */
92 #define ENRSR_PHY 0x20 /* physical/multicast address */
93 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
94 #define ENRSR_DEF 0x80 /* deferring */
96 /* Transmitted packet status, EN0_TSR. */
97 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
98 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
99 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
100 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
101 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
102 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
103 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
104 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
106 #define NE2000_PMEM_SIZE (32*1024)
107 #define NE2000_PMEM_START (16*1024)
108 #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
109 #define NE2000_MEM_SIZE NE2000_PMEM_END
111 typedef struct NE2000State {
125 uint8_t phys[6]; /* mac address */
127 uint8_t mult[8]; /* multicast mask array */
131 uint8_t mem[NE2000_MEM_SIZE];
134 static void ne2000_reset(NE2000State *s)
138 s->isr = ENISR_RESET;
139 memcpy(s->mem, s->nd->macaddr, 6);
143 /* duplicate prom data */
144 for(i = 15;i >= 0; i--) {
145 s->mem[2 * i] = s->mem[i];
146 s->mem[2 * i + 1] = s->mem[i];
150 static void ne2000_update_irq(NE2000State *s)
153 isr = s->isr & s->imr;
154 #if defined(DEBUG_NE2000)
155 printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
156 s->irq, isr ? 1 : 0, s->isr, s->imr);
160 pci_set_irq(s->pci_dev, 0, (isr != 0));
163 pic_set_irq(s->irq, (isr != 0));
167 /* return the max buffer size if the NE2000 can receive more data */
168 static int ne2000_can_receive(void *opaque)
170 NE2000State *s = opaque;
171 int avail, index, boundary;
173 if (s->cmd & E8390_STOP)
175 index = s->curpag << 8;
176 boundary = s->boundary << 8;
177 if (index < boundary)
178 avail = boundary - index;
180 avail = (s->stop - s->start) - (index - boundary);
181 if (avail < (MAX_ETH_FRAME_SIZE + 4))
183 return MAX_ETH_FRAME_SIZE;
186 #define MIN_BUF_SIZE 60
188 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
190 NE2000State *s = opaque;
192 int total_len, next, avail, len, index;
195 #if defined(DEBUG_NE2000)
196 printf("NE2000: received len=%d\n", size);
199 /* if too small buffer, then expand it */
200 if (size < MIN_BUF_SIZE) {
201 memcpy(buf1, buf, size);
202 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
207 index = s->curpag << 8;
208 /* 4 bytes for header */
209 total_len = size + 4;
210 /* address for next packet (4 bytes for CRC) */
211 next = index + ((total_len + 4 + 255) & ~0xff);
213 next -= (s->stop - s->start);
214 /* prepare packet header */
216 s->rsr = ENRSR_RXOK; /* receive status */
217 /* XXX: check this */
223 p[3] = total_len >> 8;
226 /* write packet data */
228 avail = s->stop - index;
232 memcpy(s->mem + index, buf, len);
235 if (index == s->stop)
239 s->curpag = next >> 8;
241 /* now we can signal we have receive something */
243 ne2000_update_irq(s);
246 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
248 NE2000State *s = opaque;
249 int offset, page, index;
253 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
255 if (addr == E8390_CMD) {
256 /* control register */
258 if (val & E8390_START) {
259 s->isr &= ~ENISR_RESET;
260 /* test specific case: zero length transfert */
261 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
264 ne2000_update_irq(s);
266 if (val & E8390_TRANS) {
267 index = (s->tpsr << 8);
268 /* XXX: next 2 lines are a hack to make netware 3.11 work */
269 if (index >= NE2000_PMEM_END)
270 index -= NE2000_PMEM_SIZE;
271 /* fail safe: check range on the transmitted length */
272 if (index + s->tcnt <= NE2000_PMEM_END) {
273 qemu_send_packet(s->nd, s->mem + index, s->tcnt);
275 /* signal end of transfert */
278 s->cmd &= ~E8390_TRANS;
279 ne2000_update_irq(s);
284 offset = addr | (page << 4);
297 ne2000_update_irq(s);
303 s->tcnt = (s->tcnt & 0xff00) | val;
306 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
309 s->rsar = (s->rsar & 0xff00) | val;
312 s->rsar = (s->rsar & 0x00ff) | (val << 8);
315 s->rcnt = (s->rcnt & 0xff00) | val;
318 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
324 s->isr &= ~(val & 0x7f);
325 ne2000_update_irq(s);
327 case EN1_PHYS ... EN1_PHYS + 5:
328 s->phys[offset - EN1_PHYS] = val;
333 case EN1_MULT ... EN1_MULT + 7:
334 s->mult[offset - EN1_MULT] = val;
340 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
342 NE2000State *s = opaque;
343 int offset, page, ret;
346 if (addr == E8390_CMD) {
350 offset = addr | (page << 4);
362 ret = s->rsar & 0x00ff;
367 case EN1_PHYS ... EN1_PHYS + 5:
368 ret = s->phys[offset - EN1_PHYS];
373 case EN1_MULT ... EN1_MULT + 7:
374 ret = s->mult[offset - EN1_MULT];
385 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
390 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
394 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
399 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
402 addr &= ~1; /* XXX: check exact behaviour if not even */
404 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
405 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
409 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
412 addr &= ~1; /* XXX: check exact behaviour if not even */
414 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
415 cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
419 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
422 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
429 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
431 addr &= ~1; /* XXX: check exact behaviour if not even */
433 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
434 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
440 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
442 addr &= ~1; /* XXX: check exact behaviour if not even */
444 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
445 return le32_to_cpupu((uint32_t *)(s->mem + addr));
451 static inline void ne2000_dma_update(NE2000State *s, int len)
455 /* XXX: check what to do if rsar > stop */
456 if (s->rsar == s->stop)
459 if (s->rcnt <= len) {
461 /* signal end of transfert */
463 ne2000_update_irq(s);
469 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
471 NE2000State *s = opaque;
474 printf("NE2000: asic write val=0x%04x\n", val);
478 if (s->dcfg & 0x01) {
480 ne2000_mem_writew(s, s->rsar, val);
481 ne2000_dma_update(s, 2);
484 ne2000_mem_writeb(s, s->rsar, val);
485 ne2000_dma_update(s, 1);
489 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
491 NE2000State *s = opaque;
494 if (s->dcfg & 0x01) {
496 ret = ne2000_mem_readw(s, s->rsar);
497 ne2000_dma_update(s, 2);
500 ret = ne2000_mem_readb(s, s->rsar);
501 ne2000_dma_update(s, 1);
504 printf("NE2000: asic read val=0x%04x\n", ret);
509 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
511 NE2000State *s = opaque;
514 printf("NE2000: asic writel val=0x%04x\n", val);
519 ne2000_mem_writel(s, s->rsar, val);
520 ne2000_dma_update(s, 4);
523 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
525 NE2000State *s = opaque;
529 ret = ne2000_mem_readl(s, s->rsar);
530 ne2000_dma_update(s, 4);
532 printf("NE2000: asic readl val=0x%04x\n", ret);
537 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
539 /* nothing to do (end of reset pulse) */
542 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
544 NE2000State *s = opaque;
549 static void ne2000_save(QEMUFile* f,void* opaque)
551 NE2000State* s=(NE2000State*)opaque;
553 qemu_put_8s(f, &s->cmd);
554 qemu_put_be32s(f, &s->start);
555 qemu_put_be32s(f, &s->stop);
556 qemu_put_8s(f, &s->boundary);
557 qemu_put_8s(f, &s->tsr);
558 qemu_put_8s(f, &s->tpsr);
559 qemu_put_be16s(f, &s->tcnt);
560 qemu_put_be16s(f, &s->rcnt);
561 qemu_put_be32s(f, &s->rsar);
562 qemu_put_8s(f, &s->rsr);
563 qemu_put_8s(f, &s->isr);
564 qemu_put_8s(f, &s->dcfg);
565 qemu_put_8s(f, &s->imr);
566 qemu_put_buffer(f, s->phys, 6);
567 qemu_put_8s(f, &s->curpag);
568 qemu_put_buffer(f, s->mult, 8);
569 qemu_put_be32s(f, &s->irq);
570 qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
573 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
575 NE2000State* s=(NE2000State*)opaque;
580 qemu_get_8s(f, &s->cmd);
581 qemu_get_be32s(f, &s->start);
582 qemu_get_be32s(f, &s->stop);
583 qemu_get_8s(f, &s->boundary);
584 qemu_get_8s(f, &s->tsr);
585 qemu_get_8s(f, &s->tpsr);
586 qemu_get_be16s(f, &s->tcnt);
587 qemu_get_be16s(f, &s->rcnt);
588 qemu_get_be32s(f, &s->rsar);
589 qemu_get_8s(f, &s->rsr);
590 qemu_get_8s(f, &s->isr);
591 qemu_get_8s(f, &s->dcfg);
592 qemu_get_8s(f, &s->imr);
593 qemu_get_buffer(f, s->phys, 6);
594 qemu_get_8s(f, &s->curpag);
595 qemu_get_buffer(f, s->mult, 8);
596 qemu_get_be32s(f, &s->irq);
597 qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
602 void isa_ne2000_init(int base, int irq, NetDriverState *nd)
606 s = qemu_mallocz(sizeof(NE2000State));
610 register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
611 register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
613 register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
614 register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
615 register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
616 register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
618 register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
619 register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
625 qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
627 register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
631 /***********************************************************/
632 /* PCI NE2000 definitions */
634 typedef struct PCINE2000State {
639 static void ne2000_map(PCIDevice *pci_dev, int region_num,
640 uint32_t addr, uint32_t size, int type)
642 PCINE2000State *d = (PCINE2000State *)pci_dev;
643 NE2000State *s = &d->ne2000;
645 register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
646 register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
648 register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
649 register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
650 register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
651 register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
652 register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
653 register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
655 register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
656 register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
659 void pci_ne2000_init(PCIBus *bus, NetDriverState *nd)
665 d = (PCINE2000State *)pci_register_device(bus,
666 "NE2000", sizeof(PCINE2000State),
669 pci_conf = d->dev.config;
670 pci_conf[0x00] = 0xec; // Realtek 8029
671 pci_conf[0x01] = 0x10;
672 pci_conf[0x02] = 0x29;
673 pci_conf[0x03] = 0x80;
674 pci_conf[0x0a] = 0x00; // ethernet network controller
675 pci_conf[0x0b] = 0x02;
676 pci_conf[0x0e] = 0x00; // header_type
677 pci_conf[0x3d] = 1; // interrupt pin 0
679 pci_register_io_region(&d->dev, 0, 0x100,
680 PCI_ADDRESS_SPACE_IO, ne2000_map);
682 s->irq = 16; // PCI interrupt
683 s->pci_dev = (PCIDevice *)d;
686 qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
688 /* XXX: instance number ? */
689 register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
690 register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load,