4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 //#define DEBUG_IOAPIC
25 /* APIC Local Vector Table */
26 #define APIC_LVT_TIMER 0
27 #define APIC_LVT_THERMAL 1
28 #define APIC_LVT_PERFORM 2
29 #define APIC_LVT_LINT0 3
30 #define APIC_LVT_LINT1 4
31 #define APIC_LVT_ERROR 5
34 /* APIC delivery modes */
35 #define APIC_DM_FIXED 0
36 #define APIC_DM_LOWPRI 1
39 #define APIC_DM_INIT 5
40 #define APIC_DM_SIPI 6
41 #define APIC_DM_EXTINT 7
43 /* APIC destination mode */
44 #define APIC_DESTMODE_FLAT 0xf
45 #define APIC_DESTMODE_CLUSTER 1
47 #define APIC_TRIGGER_EDGE 0
48 #define APIC_TRIGGER_LEVEL 1
50 #define APIC_LVT_TIMER_PERIODIC (1<<17)
51 #define APIC_LVT_MASKED (1<<16)
52 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
53 #define APIC_LVT_REMOTE_IRR (1<<14)
54 #define APIC_INPUT_POLARITY (1<<13)
55 #define APIC_SEND_PENDING (1<<12)
57 #define IOAPIC_NUM_PINS 0x18
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
63 typedef struct APICState {
69 uint32_t spurious_vec;
72 uint32_t isr[8]; /* in service register */
73 uint32_t tmr[8]; /* trigger mode register */
74 uint32_t irr[8]; /* interrupt request register */
75 uint32_t lvt[APIC_LVT_NB];
76 uint32_t esr; /* error register */
81 uint32_t initial_count;
82 int64_t initial_count_load_time, next_time;
85 struct APICState *next_apic;
93 uint64_t ioredtbl[IOAPIC_NUM_PINS];
96 static int apic_io_memory;
97 static APICState *first_local_apic = NULL;
98 static int last_apic_id = 0;
100 static void apic_init_ipi(APICState *s);
101 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
102 static void apic_update_irq(APICState *s);
104 static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
105 uint8_t vector_num, uint8_t polarity,
106 uint8_t trigger_mode)
108 APICState *apic_iter;
110 switch (delivery_mode) {
113 /* XXX: arbitration */
121 /* normal INIT IPI sent to processors */
122 for (apic_iter = first_local_apic; apic_iter != NULL;
123 apic_iter = apic_iter->next_apic) {
124 apic_init_ipi(apic_iter);
129 /* handled in I/O APIC code */
136 for (apic_iter = first_local_apic; apic_iter != NULL;
137 apic_iter = apic_iter->next_apic) {
138 if (deliver_bitmask & (1 << apic_iter->id))
139 apic_set_irq(apic_iter, vector_num, trigger_mode);
143 void cpu_set_apic_base(CPUState *env, uint64_t val)
145 APICState *s = env->apic_state;
147 printf("cpu_set_apic_base: %016llx\n", val);
149 s->apicbase = (val & 0xfffff000) |
150 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
151 /* if disabled, cannot be enabled again */
152 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
153 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
154 env->cpuid_features &= ~CPUID_APIC;
155 s->spurious_vec &= ~APIC_SV_ENABLE;
159 uint64_t cpu_get_apic_base(CPUState *env)
161 APICState *s = env->apic_state;
163 printf("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase);
168 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
170 APICState *s = env->apic_state;
171 s->tpr = (val & 0x0f) << 4;
175 uint8_t cpu_get_apic_tpr(CPUX86State *env)
177 APICState *s = env->apic_state;
181 static int fls_bit(int value)
183 unsigned int ret = 0;
186 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
190 value >>= 16, ret = 16;
192 value >>= 8, ret += 8;
194 value >>= 4, ret += 4;
196 value >>= 2, ret += 2;
197 return ret + (value >> 1);
201 static inline void set_bit(uint32_t *tab, int index)
205 mask = 1 << (index & 0x1f);
209 static inline void reset_bit(uint32_t *tab, int index)
213 mask = 1 << (index & 0x1f);
217 /* return -1 if no bit is set */
218 static int get_highest_priority_int(uint32_t *tab)
221 for(i = 7; i >= 0; i--) {
223 return i * 32 + fls_bit(tab[i]);
229 static int apic_get_ppr(APICState *s)
234 isrv = get_highest_priority_int(s->isr);
245 static int apic_get_arb_pri(APICState *s)
247 /* XXX: arbitration */
251 /* signal the CPU if an irq is pending */
252 static void apic_update_irq(APICState *s)
255 if (!(s->spurious_vec & APIC_SV_ENABLE))
257 irrv = get_highest_priority_int(s->irr);
260 ppr = apic_get_ppr(s);
261 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
263 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
266 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
268 set_bit(s->irr, vector_num);
270 set_bit(s->tmr, vector_num);
272 reset_bit(s->tmr, vector_num);
276 static void apic_eoi(APICState *s)
279 isrv = get_highest_priority_int(s->isr);
282 reset_bit(s->isr, isrv);
283 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
284 set the remote IRR bit for level triggered interrupts. */
288 static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
291 APICState *apic_iter;
293 if (dest_mode == 0) {
299 /* XXX: cluster mode */
300 for (apic_iter = first_local_apic; apic_iter != NULL;
301 apic_iter = apic_iter->next_apic) {
302 if (dest & apic_iter->log_dest)
303 mask |= (1 << apic_iter->id);
311 static void apic_init_ipi(APICState *s)
315 for(i = 0; i < APIC_LVT_NB; i++)
316 s->lvt[i] = 1 << 16; /* mask LVT */
318 s->spurious_vec = 0xff;
321 memset(s->isr, 0, sizeof(s->isr));
322 memset(s->tmr, 0, sizeof(s->tmr));
323 memset(s->irr, 0, sizeof(s->irr));
324 memset(s->lvt, 0, sizeof(s->lvt));
326 memset(s->icr, 0, sizeof(s->icr));
329 s->initial_count = 0;
330 s->initial_count_load_time = 0;
334 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
335 uint8_t delivery_mode, uint8_t vector_num,
336 uint8_t polarity, uint8_t trigger_mode)
338 uint32_t deliver_bitmask = 0;
339 int dest_shorthand = (s->icr[0] >> 18) & 3;
340 APICState *apic_iter;
342 switch (delivery_mode) {
344 /* XXX: serch for focus processor, arbitration */
349 int trig_mode = (s->icr[0] >> 15) & 1;
350 int level = (s->icr[0] >> 14) & 1;
351 if (level == 0 && trig_mode == 1) {
352 for (apic_iter = first_local_apic; apic_iter != NULL;
353 apic_iter = apic_iter->next_apic) {
354 if (deliver_bitmask & (1 << apic_iter->id)) {
355 apic_iter->arb_id = apic_iter->id;
364 for (apic_iter = first_local_apic; apic_iter != NULL;
365 apic_iter = apic_iter->next_apic) {
366 if (deliver_bitmask & (1 << apic_iter->id)) {
367 /* XXX: SMP support */
368 /* apic_startup(apic_iter); */
374 switch (dest_shorthand) {
376 deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
379 deliver_bitmask = (1 << s->id);
382 deliver_bitmask = 0xffffffff;
385 deliver_bitmask = 0xffffffff & ~(1 << s->id);
389 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
393 int apic_get_interrupt(CPUState *env)
395 APICState *s = env->apic_state;
398 /* if the APIC is installed or enabled, we let the 8259 handle the
402 if (!(s->spurious_vec & APIC_SV_ENABLE))
405 /* XXX: spurious IRQ handling */
406 intno = get_highest_priority_int(s->irr);
409 reset_bit(s->irr, intno);
410 if (s->tpr && intno <= s->tpr)
411 return s->spurious_vec & 0xff;
412 set_bit(s->isr, intno);
417 static uint32_t apic_get_current_count(APICState *s)
421 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
423 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
425 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
427 if (d >= s->initial_count)
430 val = s->initial_count - d;
435 static void apic_timer_update(APICState *s, int64_t current_time)
437 int64_t next_time, d;
439 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
440 d = (current_time - s->initial_count_load_time) >>
442 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
443 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
445 if (d >= s->initial_count)
447 d = (uint64_t)s->initial_count + 1;
449 next_time = s->initial_count_load_time + (d << s->count_shift);
450 qemu_mod_timer(s->timer, next_time);
451 s->next_time = next_time;
454 qemu_del_timer(s->timer);
458 static void apic_timer(void *opaque)
460 APICState *s = opaque;
462 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
463 apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
465 apic_timer_update(s, s->next_time);
468 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
473 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
478 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
482 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
486 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
493 env = cpu_single_env;
498 index = (addr >> 4) & 0xff;
503 case 0x03: /* version */
504 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
510 val = apic_get_arb_pri(s);
514 val = apic_get_ppr(s);
517 val = s->log_dest << 24;
520 val = s->dest_mode << 28;
523 val = s->spurious_vec;
526 val = s->isr[index & 7];
529 val = s->tmr[index & 7];
532 val = s->irr[index & 7];
538 val = s->lvt[index - 0x32];
542 val = s->icr[index & 1];
545 val = s->initial_count;
548 val = apic_get_current_count(s);
551 val = s->divide_conf;
554 s->esr |= ESR_ILLEGAL_ADDRESS;
559 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
564 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
570 env = cpu_single_env;
576 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
579 index = (addr >> 4) & 0xff;
592 s->log_dest = val >> 24;
595 s->dest_mode = val >> 28;
598 s->spurious_vec = val & 0x1ff;
603 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
604 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
605 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
612 int n = index - 0x32;
614 if (n == APIC_LVT_TIMER)
615 apic_timer_update(s, qemu_get_clock(vm_clock));
619 s->initial_count = val;
620 s->initial_count_load_time = qemu_get_clock(vm_clock);
621 apic_timer_update(s, s->initial_count_load_time);
626 s->divide_conf = val & 0xb;
627 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
628 s->count_shift = (v + 1) & 7;
632 s->esr |= ESR_ILLEGAL_ADDRESS;
637 static void apic_save(QEMUFile *f, void *opaque)
639 APICState *s = opaque;
642 qemu_put_be32s(f, &s->apicbase);
643 qemu_put_8s(f, &s->id);
644 qemu_put_8s(f, &s->arb_id);
645 qemu_put_8s(f, &s->tpr);
646 qemu_put_be32s(f, &s->spurious_vec);
647 qemu_put_8s(f, &s->log_dest);
648 qemu_put_8s(f, &s->dest_mode);
649 for (i = 0; i < 8; i++) {
650 qemu_put_be32s(f, &s->isr[i]);
651 qemu_put_be32s(f, &s->tmr[i]);
652 qemu_put_be32s(f, &s->irr[i]);
654 for (i = 0; i < APIC_LVT_NB; i++) {
655 qemu_put_be32s(f, &s->lvt[i]);
657 qemu_put_be32s(f, &s->esr);
658 qemu_put_be32s(f, &s->icr[0]);
659 qemu_put_be32s(f, &s->icr[1]);
660 qemu_put_be32s(f, &s->divide_conf);
661 qemu_put_be32s(f, &s->count_shift);
662 qemu_put_be32s(f, &s->initial_count);
663 qemu_put_be64s(f, &s->initial_count_load_time);
664 qemu_put_be64s(f, &s->next_time);
667 static int apic_load(QEMUFile *f, void *opaque, int version_id)
669 APICState *s = opaque;
675 /* XXX: what if the base changes? (registered memory regions) */
676 qemu_get_be32s(f, &s->apicbase);
677 qemu_get_8s(f, &s->id);
678 qemu_get_8s(f, &s->arb_id);
679 qemu_get_8s(f, &s->tpr);
680 qemu_get_be32s(f, &s->spurious_vec);
681 qemu_get_8s(f, &s->log_dest);
682 qemu_get_8s(f, &s->dest_mode);
683 for (i = 0; i < 8; i++) {
684 qemu_get_be32s(f, &s->isr[i]);
685 qemu_get_be32s(f, &s->tmr[i]);
686 qemu_get_be32s(f, &s->irr[i]);
688 for (i = 0; i < APIC_LVT_NB; i++) {
689 qemu_get_be32s(f, &s->lvt[i]);
691 qemu_get_be32s(f, &s->esr);
692 qemu_get_be32s(f, &s->icr[0]);
693 qemu_get_be32s(f, &s->icr[1]);
694 qemu_get_be32s(f, &s->divide_conf);
695 qemu_get_be32s(f, &s->count_shift);
696 qemu_get_be32s(f, &s->initial_count);
697 qemu_get_be64s(f, &s->initial_count_load_time);
698 qemu_get_be64s(f, &s->next_time);
702 static void apic_reset(void *opaque)
704 APICState *s = opaque;
708 static CPUReadMemoryFunc *apic_mem_read[3] = {
714 static CPUWriteMemoryFunc *apic_mem_write[3] = {
720 int apic_init(CPUState *env)
724 s = qemu_mallocz(sizeof(APICState));
729 s->id = last_apic_id++;
731 s->apicbase = 0xfee00000 |
732 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
734 /* XXX: mapping more APICs at the same memory location */
735 if (apic_io_memory == 0) {
736 /* NOTE: the APIC is directly connected to the CPU - it is not
737 on the global memory bus. */
738 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
739 apic_mem_write, NULL);
740 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
743 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
745 register_savevm("apic", 0, 1, apic_save, apic_load, s);
746 qemu_register_reset(apic_reset, s);
748 s->next_apic = first_local_apic;
749 first_local_apic = s;
754 static void ioapic_service(IOAPICState *s)
759 uint8_t delivery_mode;
766 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
769 entry = s->ioredtbl[i];
770 if (!(entry & APIC_LVT_MASKED)) {
771 trig_mode = ((entry >> 15) & 1);
773 dest_mode = (entry >> 11) & 1;
774 delivery_mode = (entry >> 8) & 7;
775 polarity = (entry >> 13) & 1;
776 if (trig_mode == APIC_TRIGGER_EDGE)
778 if (delivery_mode == APIC_DM_EXTINT)
779 vector = pic_read_irq(isa_pic);
781 vector = entry & 0xff;
782 apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
783 delivery_mode, vector, polarity, trig_mode);
789 void ioapic_set_irq(void *opaque, int vector, int level)
791 IOAPICState *s = opaque;
793 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
794 uint32_t mask = 1 << vector;
795 uint64_t entry = s->ioredtbl[vector];
797 if ((entry >> 15) & 1) {
798 /* level triggered */
815 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
817 IOAPICState *s = opaque;
824 } else if (addr == 0x10) {
825 switch (s->ioregsel) {
830 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
836 index = (s->ioregsel - 0x10) >> 1;
837 if (index >= 0 && index < IOAPIC_NUM_PINS) {
839 val = s->ioredtbl[index] >> 32;
841 val = s->ioredtbl[index] & 0xffffffff;
845 printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
851 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
853 IOAPICState *s = opaque;
860 } else if (addr == 0x10) {
862 printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
864 switch (s->ioregsel) {
866 s->id = (val >> 24) & 0xff;
872 index = (s->ioregsel - 0x10) >> 1;
873 if (index >= 0 && index < IOAPIC_NUM_PINS) {
874 if (s->ioregsel & 1) {
875 s->ioredtbl[index] &= 0xffffffff;
876 s->ioredtbl[index] |= (uint64_t)val << 32;
878 s->ioredtbl[index] &= ~0xffffffffULL;
879 s->ioredtbl[index] |= val;
887 static void ioapic_save(QEMUFile *f, void *opaque)
889 IOAPICState *s = opaque;
892 qemu_put_8s(f, &s->id);
893 qemu_put_8s(f, &s->ioregsel);
894 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
895 qemu_put_be64s(f, &s->ioredtbl[i]);
899 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
901 IOAPICState *s = opaque;
907 qemu_get_8s(f, &s->id);
908 qemu_get_8s(f, &s->ioregsel);
909 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
910 qemu_get_be64s(f, &s->ioredtbl[i]);
915 static void ioapic_reset(void *opaque)
917 IOAPICState *s = opaque;
920 memset(s, 0, sizeof(*s));
921 for(i = 0; i < IOAPIC_NUM_PINS; i++)
922 s->ioredtbl[i] = 1 << 16; /* mask LVT */
925 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
931 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
937 IOAPICState *ioapic_init(void)
942 s = qemu_mallocz(sizeof(IOAPICState));
946 s->id = last_apic_id++;
948 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
949 ioapic_mem_write, s);
950 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
952 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
953 qemu_register_reset(ioapic_reset, s);