1 /*****************************************************************
3 *****************************************************************/
6 // CC : ARM Carry Clear
7 BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
9 ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
12 // NE : ARM Zero Clear
13 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
15 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
18 // NE : ARM Zero Clear
19 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
21 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
23 BICPL rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
25 ORRMI rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set N to one
28 /*****************************************************************
30 *****************************************************************/
36 TST rstatus, #MASK_DECIMAL
42 MOV rscratch4,#0x0F000000
43 //rscratch2=xxW1xxxxxxxxxxxx
44 AND rscratch2, rscratch, rscratch4
45 //rscratch=xxW2xxxxxxxxxxxx
46 AND rscratch, rscratch4, rscratch, LSR #4
47 //rscratch3=xxA2xxxxxxxxxxxx
48 AND rscratch3, rscratch4, regA, LSR #4
49 //rscratch4=xxA1xxxxxxxxxxxx
50 AND rscratch4,regA,rscratch4
52 TST rstatus, #MASK_CARRY
53 ADDNE rscratch2, rscratch2, #0x01000000
54 ADD rscratch2,rscratch2,rscratch4
56 CMP rscratch2, #0x09000000
58 SUBGT rscratch2, rscratch2, #0x0A000000
60 ADDGT rscratch3, rscratch3, #0x01000000
62 ADD rscratch3, rscratch3, rscratch
64 CMP rscratch3, #0x09000000
66 SUBGT rscratch3, rscratch3, #0x0A000000
68 ORRGT rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
70 BICLE rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
71 // gather rscratch3 and rscratch2 into ans8
72 // rscratch3 : 0R2000000
73 // rscratch2 : 0R1000000
75 ORR rscratch2, rscratch2, rscratch3, LSL #4
78 AND rscratch,rscratch,#0x80000000
79 // (register.AL ^ Work8)
80 EORS rscratch3, regA, rscratch
81 BICNE rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
84 EORS rscratch3, rscratch2, rscratch
86 TSTNE rscratch3,#0x80000000
87 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
88 ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
95 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
96 SUBCS rscratch, rscratch, #0x100
97 ADCS regA, regA, rscratch, ROR #8
99 ORRVS rstatus, rstatus, #MASK_OVERFLOW
100 BICVC rstatus, rstatus, #MASK_OVERFLOW
104 ANDS regA, regA, #0xFF000000
111 TST rstatus, #MASK_DECIMAL
115 //rscratch = W3W2W1W0........
116 LDR rscratch4, = 0x0F0F0000
117 // rscratch2 = xxW2xxW0xxxxxx
118 // rscratch3 = xxW3xxW1xxxxxx
119 AND rscratch2, rscratch4, rscratch
120 AND rscratch3, rscratch4, rscratch, LSR #4
121 // rscratch2 = xxW3xxW1xxW2xxW0
122 ORR rscratch2, rscratch3, rscratch2, LSR #16
123 // rscratch3 = xxA2xxA0xxxxxx
124 // rscratch4 = xxA3xxA1xxxxxx
125 // rscratch2 = xxA3xxA1xxA2xxA0
126 AND rscratch3, rscratch4, regA
127 AND rscratch4, rscratch4, regA, LSR #4
128 ORR rscratch3, rscratch4, rscratch3, LSR #16
129 ADD rscratch2, rscratch3, rscratch2
130 LDR rscratch4, = 0x0F0F0000
132 TST rstatus, #MASK_CARRY
133 ADDNE rscratch2, rscratch2, #0x1
134 // rscratch2 = A + W + C
136 AND rscratch3, rscratch2, #0x0000001F
137 CMP rscratch3, #0x00000009
138 ADDHI rscratch2, rscratch2, #0x00010000
139 SUBHI rscratch2, rscratch2, #0x0000000A
141 AND rscratch3, rscratch2, #0x001F0000
142 CMP rscratch3, #0x00090000
143 ADDHI rscratch2, rscratch2, #0x00000100
144 SUBHI rscratch2, rscratch2, #0x000A0000
146 AND rscratch3, rscratch2, #0x00001F00
147 CMP rscratch3, #0x00000900
148 SUBHI rscratch2, rscratch2, #0x00000A00
149 ADDHI rscratch2, rscratch2, #0x01000000
151 AND rscratch3, rscratch2, #0x1F000000
152 CMP rscratch3, #0x09000000
153 SUBHI rscratch2, rscratch2, #0x0A000000
155 ORRHI rstatus, rstatus, #MASK_CARRY
157 BICLS rstatus, rstatus, #MASK_CARRY
158 //rscratch2 = xxR3xxR1xxR2xxR0
160 //rscratch3 = xxR3xxR1xxxxxxxx
161 AND rscratch3, rscratch4, rscratch2
162 //rscratch2 = xxR2xxR0xxxxxxxx
163 AND rscratch2, rscratch4, rscratch2,LSL #16
164 //rscratch2 = R3R2R1R0xxxxxxxx
165 ORR rscratch2, rscratch2,rscratch3,LSL #4
167 AND rscratch,rscratch,#0x80000000
168 // (register.AL ^ Work8)
169 EORS rscratch3, regA, rscratch
170 BICNE rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
173 EORS rscratch3, rscratch2, rscratch
174 TSTNE rscratch3,#0x80000000
175 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
176 ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
183 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
184 SUBCS rscratch, rscratch, #0x10000
185 ADCS regA, regA,rscratch, ROR #16
187 ORRVS rstatus, rstatus, #MASK_OVERFLOW
188 BICVC rstatus, rstatus, #MASK_OVERFLOW
189 MOV regA, regA, LSR #16
193 MOVS regA, regA, LSL #16
202 ANDS regA, regA, rscratch
207 ANDS regA, regA, rscratch
212 MOVS regA, regA, LSL #1
219 MOVS regA, regA, LSL #1
225 S9xGetWordRegNS rscratch2 // do not destroy Opadress in rscratch
226 MOVS rscratch2, rscratch2, LSL #1
233 S9xGetByteRegNS rscratch2 // do not destroy Opadress in rscratch
234 MOVS rscratch2, rscratch2, LSL #1
242 MOVS rscratch2, rscratch, LSL #1
243 // Trick in ASM : shift one more bit : ARM C = Snes N
245 // If Carry Set, then Set Neg in SNES
246 BICCC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set C to zero
247 ORRCS rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set C to one
248 // If Neg Set, then Set Overflow in SNES
249 BICPL rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set N to zero
250 ORRMI rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set N to one
252 // Now do a real AND with A register
253 // Set Zero Flag, bit test
254 ANDS rscratch2, regA, rscratch
255 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
256 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
261 MOVS rscratch2, rscratch, LSL #1
262 // Trick in ASM : shift one more bit : ARM C = Snes N
264 // If Carry Set, then Set Neg in SNES
265 BICCC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
266 ORRCS rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set N to one
267 // If Neg Set, then Set Overflow in SNES
268 BICPL rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
269 ORRMI rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
270 // Now do a real AND with A register
271 // Set Zero Flag, bit test
272 ANDS rscratch2, regA, rscratch
273 // Bit set ->Z=0->xxxNE Clear flag
274 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
275 // Bit clear->Z=1->xxxEQ Set flag
276 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
280 SUBS rscratch2,regA,rscratch
281 BICCC rstatus, rstatus, #MASK_CARRY
282 ORRCS rstatus, rstatus, #MASK_CARRY
288 SUBS rscratch2,regA,rscratch
289 BICCC rstatus, rstatus, #MASK_CARRY
290 ORRCS rstatus, rstatus, #MASK_CARRY
296 SUBS rscratch2,regX,rscratch
297 BICCC rstatus, rstatus, #MASK_CARRY
298 ORRCS rstatus, rstatus, #MASK_CARRY
303 SUBS rscratch2,regX,rscratch
304 BICCC rstatus, rstatus, #MASK_CARRY
305 ORRCS rstatus, rstatus, #MASK_CARRY
310 SUBS rscratch2,regY,rscratch
311 BICCC rstatus, rstatus, #MASK_CARRY
312 ORRCS rstatus, rstatus, #MASK_CARRY
317 SUBS rscratch2,regY,rscratch
318 BICCC rstatus, rstatus, #MASK_CARRY
319 ORRCS rstatus, rstatus, #MASK_CARRY
324 SUBS regA, regA, #0x01000000
325 STR rscratch,[regCPUvar,#WaitAddress_ofs]
331 SUBS regA, regA, #0x00010000
332 STR rscratch,[regCPUvar,#WaitAddress_ofs]
337 S9xGetWordRegNS rscratch2 // do not destroy Opadress in rscratch
339 SUBS rscratch2, rscratch2, #0x00010000
340 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
346 S9xGetByteRegNS rscratch2 // do not destroy Opadress in rscratch
348 SUBS rscratch2, rscratch2, #0x01000000
349 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
356 EORS regA, regA, rscratch
361 EORS regA, regA, rscratch
366 ADDS regA, regA, #0x01000000
367 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
373 ADDS regA, regA, #0x00010000
374 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
379 S9xGetWordRegNS rscratch2
381 ADDS rscratch2, rscratch2, #0x00010000
382 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
388 S9xGetByteRegNS rscratch2
390 ADDS rscratch2, rscratch2, #0x01000000
391 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
397 S9xGetWordRegStatus regA
401 S9xGetByteRegStatus regA
405 S9xGetWordRegStatus regX
409 S9xGetByteRegStatus regX
413 S9xGetWordRegStatus regY
417 S9xGetByteRegStatus regY
421 BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
422 MOVS regA, regA, LSR #17 // hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
424 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
425 MOV regA, regA, LSL #16 // -> 0lllllll 00000000 00000000 00000000
426 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
427 // Note : the two MOV are included between instruction, to optimize
433 BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
434 MOVS regA, regA, LSR #25 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
436 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
437 MOV regA, regA, LSL #24 // -> 00000000 00000000 00000000 0lllllll
438 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
439 // Note : the two MOV are included between instruction, to optimize
445 S9xGetWordRegNS rscratch2
446 // N set to zero by >> 1 LSR
447 BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
448 MOVS rscratch2, rscratch2, LSR #17 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
450 BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
451 ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
453 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
454 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
455 S9xSetWordLow rscratch2
459 S9xGetByteRegNS rscratch2
460 // N set to zero by >> 1 LSR
461 BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero
462 MOVS rscratch2, rscratch2, LSR #25 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
464 BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
465 ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
467 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
468 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
469 S9xSetByteLow rscratch2
474 ORRS regA, regA, rscratch
479 ORRS regA, regA, rscratch
483 TST rstatus, #MASK_CARRY
484 ORRNE regA, regA, #0x00008000
485 MOVS regA, regA, LSL #1
491 TST rstatus, #MASK_CARRY
492 ORRNE regA, regA, #0x00800000
493 MOVS regA, regA, LSL #1
499 S9xGetWordRegNS rscratch2
500 TST rstatus, #MASK_CARRY
501 ORRNE rscratch2, rscratch2, #0x00008000
502 MOVS rscratch2, rscratch2, LSL #1
509 S9xGetByteRegNS rscratch2
510 TST rstatus, #MASK_CARRY
511 ORRNE rscratch2, rscratch2, #0x00800000
512 MOVS rscratch2, rscratch2, LSL #1
519 MOV regA,regA, LSR #16
520 TST rstatus, #MASK_CARRY
521 ORRNE regA, regA, #0x00010000
522 ORRNE rstatus,rstatus,#MASK_NEG
523 BICEQ rstatus,rstatus,#MASK_NEG
524 MOVS regA,regA,LSR #1
527 MOV regA,regA, LSL #16
531 MOV regA,regA, LSR #24
532 TST rstatus, #MASK_CARRY
533 ORRNE regA, regA, #0x00000100
534 ORRNE rstatus,rstatus,#MASK_NEG
535 BICEQ rstatus,rstatus,#MASK_NEG
536 MOVS regA,regA,LSR #1
539 MOV regA,regA, LSL #24
543 S9xGetWordLowRegNS rscratch2
544 TST rstatus, #MASK_CARRY
545 ORRNE rscratch2, rscratch2, #0x00010000
546 ORRNE rstatus,rstatus,#MASK_NEG
547 BICEQ rstatus,rstatus,#MASK_NEG
548 MOVS rscratch2,rscratch2,LSR #1
551 S9xSetWordLow rscratch2
556 S9xGetByteLowRegNS rscratch2
557 TST rstatus, #MASK_CARRY
558 ORRNE rscratch2, rscratch2, #0x00000100
559 ORRNE rstatus,rstatus,#MASK_NEG
560 BICEQ rstatus,rstatus,#MASK_NEG
561 MOVS rscratch2,rscratch2,LSR #1
564 S9xSetByteLow rscratch2
569 TST rstatus, #MASK_DECIMAL
574 STMFD R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9}
575 MOV rscratch9,#0x000F0000
576 //rscratch2=xxxxxxW1xxxxxxxxxx + !Carry
577 //rscratch3=xxxxxxW2xxxxxxxxxx
578 //rscratch4=xxxxxxW3xxxxxxxxxx
579 //rscratch5=xxxxxxW4xxxxxxxxxx
580 AND rscratch2, rscratch9, rscratch
581 TST rstatus, #MASK_CARRY
582 ADDEQ rscratch2, rscratch2, #0x00010000 //W1=W1+!Carry
583 AND rscratch3, rscratch9, rscratch, LSR #4
584 AND rscratch4, rscratch9, rscratch, LSR #8
585 AND rscratch5, rscratch9, rscratch, LSR #12
587 //rscratch6=xxxxxxA1xxxxxxxxxx
588 //rscratch7=xxxxxxA2xxxxxxxxxx
589 //rscratch8=xxxxxxA3xxxxxxxxxx
590 //rscratch9=xxxxxxA4xxxxxxxxxx
591 AND rscratch6, rscratch9, regA
592 AND rscratch7, rscratch9, regA, LSR #4
593 AND rscratch8, rscratch9, regA, LSR #8
594 AND rscratch9, rscratch9, regA, LSR #12
596 SUB rscratch2,rscratch6,rscratch2 //R1=A1-W1-!Carry
597 CMP rscratch2, #0x00090000 // if R1 > 9
598 ADDHI rscratch2, rscratch2, #0x000A0000 // then R1 += 10
599 ADDHI rscratch3, rscratch3, #0x00010000 // then (W2++)
600 SUB rscratch3,rscratch7,rscratch3 //R2=A2-W2
601 CMP rscratch3, #0x00090000 // if R2 > 9
602 ADDHI rscratch3, rscratch3, #0x000A0000 // then R2 += 10
603 ADDHI rscratch4, rscratch4, #0x00010000 // then (W3++)
604 SUB rscratch4,rscratch8,rscratch4 //R3=A3-W3
605 CMP rscratch4, #0x00090000 // if R3 > 9
606 ADDHI rscratch4, rscratch4, #0x000A0000 // then R3 += 10
607 ADDHI rscratch5, rscratch5, #0x00010000 // then (W3++)
608 SUB rscratch5,rscratch9,rscratch5 //R4=A4-W4
609 CMP rscratch5, #0x00090000 // if R4 > 9
610 ADDHI rscratch5, rscratch5, #0x000A0000 // then R4 += 10
611 BICHI rstatus, rstatus, #MASK_CARRY // then ClearCarry
612 ORRLS rstatus, rstatus, #MASK_CARRY // else SetCarry
614 MOV rscratch9,#0x000F0000
615 AND rscratch2,rscratch9,rscratch2
616 AND rscratch3,rscratch9,rscratch3
617 AND rscratch4,rscratch9,rscratch4
618 AND rscratch5,rscratch9,rscratch5
619 ORR rscratch2,rscratch2,rscratch3,LSL #4
620 ORR rscratch2,rscratch2,rscratch4,LSL #8
621 ORR rscratch2,rscratch2,rscratch5,LSL #12
623 LDMFD R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9}
625 AND regA,regA,#0x80000000
626 // (register.A.W ^ Work8)
627 EORS rscratch3, regA, rscratch
628 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
630 // (register.A.W ^ Ans8)
631 EORS rscratch3, regA, rscratch2
633 TSTNE rscratch3,#0x80000000
634 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
635 ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
642 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
643 SBCS regA, regA, rscratch, LSL #16
645 ORRVS rstatus, rstatus, #MASK_OVERFLOW
646 BICVC rstatus, rstatus, #MASK_OVERFLOW
647 MOV regA, regA, LSR #16
650 MOVS regA, regA, LSL #16
657 TST rstatus, #MASK_DECIMAL
660 STMFD R13!,{rscratch}
661 MOV rscratch4,#0x0F000000
662 //rscratch2=xxW1xxxxxxxxxxxx
663 AND rscratch2, rscratch, rscratch4
664 //rscratch=xxW2xxxxxxxxxxxx
665 AND rscratch, rscratch4, rscratch, LSR #4
666 //rscratch3=xxA2xxxxxxxxxxxx
667 AND rscratch3, rscratch4, regA, LSR #4
668 //rscratch4=xxA1xxxxxxxxxxxx
669 AND rscratch4,regA,rscratch4
671 TST rstatus, #MASK_CARRY
672 ADDEQ rscratch2, rscratch2, #0x01000000
673 SUB rscratch2,rscratch4,rscratch2
675 CMP rscratch2, #0x09000000
677 ADDHI rscratch2, rscratch2, #0x0A000000
679 ADDHI rscratch, rscratch, #0x01000000
681 SUB rscratch3, rscratch3, rscratch
683 CMP rscratch3, #0x09000000
685 ADDHI rscratch3, rscratch3, #0x0A000000
687 BICHI rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
689 ORRLS rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero
690 // gather rscratch3 and rscratch2 into ans8
691 AND rscratch3,rscratch3,#0x0F000000
692 AND rscratch2,rscratch2,#0x0F000000
693 // rscratch3 : 0R2000000
694 // rscratch2 : 0R1000000
696 ORR rscratch2, rscratch2, rscratch3, LSL #4
697 LDMFD R13!,{rscratch}
699 AND regA,regA,#0x80000000
700 // (register.AL ^ Work8)
701 EORS rscratch3, regA, rscratch
702 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
704 // (register.AL ^ Ans8)
705 EORS rscratch3, regA, rscratch2
707 TSTNE rscratch3,#0x80000000
708 BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero
709 ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one
716 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
717 SBCS regA, regA, rscratch, LSL #24
719 ORRVS rstatus, rstatus, #MASK_OVERFLOW
720 BICVC rstatus, rstatus, #MASK_OVERFLOW
724 ANDS regA, regA, #0xFF000000
754 S9xGetWordRegNS rscratch2
756 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
757 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
758 ORR rscratch2, regA, rscratch2
763 S9xGetByteRegNS rscratch2
765 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
766 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
767 ORR rscratch2, regA, rscratch2
772 S9xGetWordRegNS rscratch2
774 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
775 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
777 AND rscratch2, rscratch3, rscratch2
782 S9xGetByteRegNS rscratch2
784 BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero
785 ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one
787 AND rscratch2, rscratch3, rscratch2
791 /**************************************************************************/
794 /**************************************************************************/
796 .macro Op09M0 /*ORA*/
797 LDRB rscratch2, [rpc,#1]
798 LDRB rscratch, [rpc], #2
799 ORR rscratch2,rscratch,rscratch2,LSL #8
800 ORRS regA,regA,rscratch2,LSL #16
804 .macro Op09M1 /*ORA*/
805 LDRB rscratch, [rpc], #1
806 ORRS regA,regA,rscratch,LSL #24
810 /***********************************************************************/
814 TST rstatus, #MASK_CARRY
816 ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
824 TST rstatus, #MASK_CARRY
826 ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
834 TST rstatus, #MASK_ZERO
836 ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
844 TST rstatus, #MASK_ZERO
846 ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
854 TST rstatus, #MASK_NEG
856 ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase
864 TST rstatus, #MASK_NEG // neg, z!=0, NE
866 ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
874 TST rstatus, #MASK_OVERFLOW // neg, z!=0, NE
876 ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
884 TST rstatus, #MASK_OVERFLOW // neg, z!=0, NE
886 ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
893 ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase
898 /*******************************************************************************************/
899 /************************************************************/
900 /* SetFlag Instructions ********************************************************************** */
902 ORR rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one
915 /****************************************************************************************/
916 /* ClearFlag Instructions ******************************************************************** */
918 BIC rstatus, rstatus, #MASK_CARRY
931 BIC rstatus, rstatus, #MASK_OVERFLOW
935 /******************************************************************************************/
936 /* DEX/DEY *********************************************************************************** */
938 .macro OpCAX1 /*DEX*/
940 SUBS regX, regX, #0x01000000
941 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
945 .macro OpCAX0 /*DEX*/
947 SUBS regX, regX, #0x00010000
948 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
952 .macro Op88X1 /*DEY*/
954 SUBS regY, regY, #0x01000000
955 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
959 .macro Op88X0 /*DEY*/
961 SUBS regY, regY, #0x00010000
962 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
967 /******************************************************************************************/
968 /* INX/INY *********************************************************************************** */
971 ADDS regX, regX, #0x01000000
972 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
978 ADDS regX, regX, #0x00010000
979 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
985 ADDS regY, regY, #0x01000000
986 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
992 ADDS regY, regY, #0x00010000
993 STR rscratch3,[regCPUvar,#WaitAddress_ofs]
998 /**********************************************************************************************/
1000 /* NOP *************************************************************************************** */
1005 /**************************************************************************/
1006 /* PUSH Instructions **************************************************** */
1028 AND rscratch2, regDBank, #0xFF
1060 /**************************************************************************/
1061 /* PULL Instructions **************************************************** */
1073 BIC regDBank,regDBank, #0xFF
1075 ORR regDBank,regDBank,rscratch, LSR #24
1080 BIC regD,regD, #0xFF000000
1081 BIC regD,regD, #0x00FF0000
1083 ORR regD,rscratch,regD
1087 .macro Op28X1M1 /*PLP*/
1088 //INDEX set, MEMORY set
1089 BIC rstatus,rstatus,#0xFF000000
1091 ORR rstatus,rscratch,rstatus
1092 TST rstatus, #MASK_INDEX
1093 //INDEX clear & was set : 8->16
1094 MOVEQ regX,regX,LSR #8
1095 MOVEQ regY,regY,LSR #8
1096 TST rstatus, #MASK_MEM
1097 //MEMORY cleared & was set : 8->16
1098 LDREQB rscratch,[regCPUvar,#RAH_ofs]
1099 MOVEQ regA,regA,LSR #8
1100 ORREQ regA,regA,rscratch, LSL #24
1104 .macro Op28X0M1 /*PLP*/
1105 //INDEX cleared, MEMORY set
1106 BIC rstatus,rstatus,#0xFF000000
1108 ORR rstatus,rscratch,rstatus
1109 TST rstatus, #MASK_INDEX
1110 //INDEX set & was cleared : 16->8
1111 MOVNE regX,regX,LSL #8
1112 MOVNE regY,regY,LSL #8
1113 TST rstatus, #MASK_MEM
1114 //MEMORY cleared & was set : 8->16
1115 LDREQB rscratch,[regCPUvar,#RAH_ofs]
1116 MOVEQ regA,regA,LSR #8
1117 ORREQ regA,regA,rscratch, LSL #24
1121 .macro Op28X1M0 /*PLP*/
1122 //INDEX set, MEMORY set
1123 BIC rstatus,rstatus,#0xFF000000
1125 ORR rstatus,rscratch,rstatus
1126 TST rstatus, #MASK_INDEX
1127 //INDEX clear & was set : 8->16
1128 MOVEQ regX,regX,LSR #8
1129 MOVEQ regY,regY,LSR #8
1130 TST rstatus, #MASK_MEM
1131 //MEMORY set & was cleared : 16->8
1132 MOVNE rscratch,regA,LSR #24
1133 MOVNE regA,regA,LSL #8
1134 STRNEB rscratch,[regCPUvar,#RAH_ofs]
1138 .macro Op28X0M0 /*PLP*/
1139 //INDEX set, MEMORY set
1140 BIC rstatus,rstatus,#0xFF000000
1142 ORR rstatus,rscratch,rstatus
1143 TST rstatus, #MASK_INDEX
1144 //INDEX set & was cleared : 16->8
1145 MOVNE regX,regX,LSL #8
1146 MOVNE regY,regY,LSL #8
1147 TST rstatus, #MASK_MEM
1148 //MEMORY set & was cleared : 16->8
1149 MOVNE rscratch,regA,LSR #24
1150 MOVNE regA,regA,LSL #8
1151 STRNEB rscratch,[regCPUvar,#RAH_ofs]
1176 /**********************************************************************************************/
1177 /* Transfer Instructions ********************************************************************* */
1178 .macro OpAAX1M1 /*TAX8*/
1183 .macro OpAAX0M1 /*TAX16*/
1184 LDRB regX, [regCPUvar,#RAH_ofs]
1185 MOV regX, regX,LSL #24
1186 ORRS regX, regX,regA, LSR #8
1190 .macro OpAAX1M0 /*TAX8*/
1191 MOVS regX, regA, LSL #8
1195 .macro OpAAX0M0 /*TAX16*/
1200 .macro OpA8X1M1 /*TAY8*/
1205 .macro OpA8X0M1 /*TAY16*/
1206 LDRB regY, [regCPUvar,#RAH_ofs]
1207 MOV regY, regY,LSL #24
1208 ORRS regY, regY,regA, LSR #8
1212 .macro OpA8X1M0 /*TAY8*/
1213 MOVS regY, regA, LSL #8
1217 .macro OpA8X0M0 /*TAY16*/
1223 LDRB rscratch, [regCPUvar,#RAH_ofs]
1224 MOV regD,regD,LSL #16
1225 MOV rscratch,rscratch,LSL #24
1226 ORRS rscratch,rscratch,regA, LSR #8
1228 ORR regD,rscratch,regD,LSR #16
1232 MOV regD,regD,LSL #16
1235 ORR regD,regA,regD,LSR #16
1239 TST rstatus, #MASK_EMUL
1240 MOVNE regS, regA, LSR #24
1241 ORRNE regS, regS, #0x100
1242 LDREQB regS, [regCPUvar,#RAH_ofs]
1243 ORREQ regS, regS, regA
1244 MOVEQ regS, regS, ROR #24
1248 MOV regS, regA, LSR #16
1252 MOVS regA, regD, ASR #16
1254 MOV rscratch,regA,LSR #8
1255 MOV regA,regA, LSL #24
1256 STRB rscratch, [regCPUvar,#RAH_ofs]
1260 MOVS regA, regD, ASR #16
1262 MOV regA,regA, LSL #16
1266 MOV rscratch,regS, LSR #8
1267 MOVS regA, regS, LSL #16
1268 STRB rscratch, [regCPUvar,#RAH_ofs]
1270 MOV regA,regA, LSL #8
1274 MOVS regA, regS, LSL #16
1279 MOVS regX, regS, LSL #24
1284 MOVS regX, regS, LSL #16
1294 MOVS regA, regX, LSL #8
1299 MOVS regA, regX, LSR #8
1309 MOV regS, regX, LSR #24
1310 TST rstatus, #MASK_EMUL
1311 ORRNE regS, regS, #0x100
1315 MOV regS, regX, LSR #16
1334 MOVS regA, regY, LSL #8
1339 MOVS regA, regY, LSR #8
1359 /**********************************************************************************************/
1360 /* XCE *************************************************************************************** */
1363 TST rstatus,#MASK_CARRY
1366 TST rstatus,#MASK_EMUL
1369 BIC rstatus,rstatus,#(MASK_CARRY)
1370 TST rstatus,#MASK_INDEX
1371 //X & Y were 16bits before
1372 MOVEQ regX,regX,LSL #8
1373 MOVEQ regY,regY,LSL #8
1374 TST rstatus,#MASK_MEM
1375 //A was 16bits before
1377 MOVEQ rscratch,regA,LSR #24
1378 STREQB rscratch,[regCPUvar,#RAH_ofs]
1379 MOVEQ regA,regA,LSL #8
1380 ORR rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
1382 ORR regS,regS,#0x100
1386 TST rstatus,#MASK_INDEX
1387 //X & Y were 16bits before
1388 MOVEQ regX,regX,LSL #8
1389 MOVEQ regY,regY,LSL #8
1390 TST rstatus,#MASK_MEM
1391 //A was 16bits before
1393 MOVEQ rscratch,regA,LSR #24
1394 STREQB rscratch,[regCPUvar,#RAH_ofs]
1395 MOVEQ regA,regA,LSL #8
1396 ORR rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
1398 ORR regS,regS,#0x100
1402 TST rstatus,#MASK_EMUL
1404 //EMUL was set : X,Y & A were 8bits
1405 //Now have to check MEMORY & INDEX for potential conversions to 16bits
1406 TST rstatus,#MASK_INDEX
1407 // X & Y are now 16bits
1408 MOVEQ regX,regX,LSR #8
1409 MOVEQ regY,regY,LSR #8
1410 TST rstatus,#MASK_MEM
1412 MOVEQ regA,regA,LSR #8
1414 LDREQB rscratch,[regCPUvar,#RAH_ofs]
1415 ORREQ regA,regA,rscratch,LSL #24
1417 BIC rstatus,rstatus,#(MASK_EMUL)
1418 ORR rstatus,rstatus,#(MASK_CARRY)
1424 /*******************************************************************************/
1425 /* BRK *************************************************************************/
1428 STRB rscratch,[regCPUvar,#BRKTriggered_ofs]
1430 TST rstatus, #MASK_EMUL
1431 // EQ is flag to zero (!CheckEmu)
1434 SUB rscratch, rpc, regpcbase
1435 ADD rscratch2, rscratch, #1
1441 BIC regPBank, regPBank, #0xFF
1443 ORR rscratch, rscratch, #0xFF00
1449 SUB rscratch2, rpc, regpcbase
1455 BIC regPBank,regPBank, #0xFF
1457 ORR rscratch, rscratch, #0xFF00
1465 /**********************************************************************************************/
1466 /* BRL ************************************************************************************** */
1469 ORR rscratch, rscratch, regPBank, LSL #16
1472 /**********************************************************************************************/
1473 /* IRQ *************************************************************************************** */
1474 //void S9xOpcode_IRQ (void)
1476 if (!CheckEmulation())
1478 PushB (Registers.PB);
1479 PushW (CPU.PC - CPU.PCBase);
1481 PushB (Registers.PL);
1487 if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40))
1488 S9xSetPCBase (Memory.FillRAM [0x220e] |
1489 (Memory.FillRAM [0x220f] << 8));
1491 S9xSetPCBase (S9xGetWord (0xFFEE));
1492 CPU.Cycles += TWO_CYCLES;
1496 PushW (CPU.PC - CPU.PCBase);
1498 PushB (Registers.PL);
1504 if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40))
1505 S9xSetPCBase (Memory.FillRAM [0x220e] |
1506 (Memory.FillRAM [0x220f] << 8));
1508 S9xSetPCBase (S9xGetWord (0xFFFE));
1509 CPU.Cycles += ONE_CYCLE;
1514 /**********************************************************************************************/
1515 /* NMI *************************************************************************************** */
1516 //void S9xOpcode_NMI (void)
1518 if (!CheckEmulation())
1520 PushB (Registers.PB);
1521 PushW (CPU.PC - CPU.PCBase);
1523 PushB (Registers.PL);
1529 if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20))
1530 S9xSetPCBase (Memory.FillRAM [0x220c] |
1531 (Memory.FillRAM [0x220d] << 8));
1533 S9xSetPCBase (S9xGetWord (0xFFEA));
1534 CPU.Cycles += TWO_CYCLES;
1538 PushW (CPU.PC - CPU.PCBase);
1540 PushB (Registers.PL);
1546 if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20))
1547 S9xSetPCBase (Memory.FillRAM [0x220c] |
1548 (Memory.FillRAM [0x220d] << 8));
1550 S9xSetPCBase (S9xGetWord (0xFFFA));
1551 CPU.Cycles += ONE_CYCLE;
1556 /**********************************************************************************************/
1557 /* COP *************************************************************************************** */
1559 TST rstatus, #MASK_EMUL
1560 // EQ is flag to zero (!CheckEmu)
1563 SUB rscratch, rpc, regpcbase
1564 ADD rscratch2, rscratch, #1
1570 BIC regPBank, regPBank,#0xFF
1572 ORR rscratch, rscratch, #0xFF00
1578 SUB rscratch2, rpc, regpcbase
1584 BIC regPBank,regPBank, #0xFF
1586 ORR rscratch, rscratch, #0xFF00
1593 /**********************************************************************************************/
1594 /* JML *************************************************************************************** */
1596 AbsoluteIndirectLong
1597 BIC regPBank,regPBank,#0xFF
1598 ORR regPBank,regPBank, rscratch, LSR #16
1604 BIC regPBank,regPBank,#0xFF
1605 ORR regPBank,regPBank, rscratch, LSR #16
1609 /**********************************************************************************************/
1610 /* JMP *************************************************************************************** */
1613 BIC rscratch, rscratch, #0xFF0000
1614 ORR rscratch, rscratch, regPBank, LSL #16
1620 BIC rscratch, rscratch, #0xFF0000
1621 ORR rscratch, rscratch, regPBank, LSL #16
1625 ADD rscratch, rscratch, regPBank, LSL #16
1630 /**********************************************************************************************/
1631 /* JSL/RTL *********************************************************************************** */
1634 SUB rscratch, rpc, regpcbase
1635 //SUB rscratch2, rscratch2, #1
1636 ADD rscratch2, rscratch, #2
1639 BIC regPBank,regPBank,#0xFF
1640 ORR regPBank, regPBank, rscratch, LSR #16
1645 BIC regPBank,regPBank,#0xFF
1647 ORR regPBank, regPBank, rscratch
1648 ADD rscratch, rpc, #1
1649 BIC rscratch, rscratch,#0xFF0000
1650 ORR rscratch, rscratch, regPBank, LSL #16
1654 /**********************************************************************************************/
1655 /* JSR/RTS *********************************************************************************** */
1657 SUB rscratch, rpc, regpcbase
1658 //SUB rscratch2, rscratch2, #1
1659 ADD rscratch2, rscratch, #1
1662 BIC rscratch, rscratch, #0xFF0000
1663 ORR rscratch, rscratch, regPBank, LSL #16
1668 SUB rscratch, rpc, regpcbase
1669 //SUB rscratch2, rscratch2, #1
1670 ADD rscratch2, rscratch, #1
1672 AbsoluteIndexedIndirectX0
1673 ORR rscratch, rscratch, regPBank, LSL #16
1678 SUB rscratch, rpc, regpcbase
1679 //SUB rscratch2, rscratch2, #1
1680 ADD rscratch2, rscratch, #1
1682 AbsoluteIndexedIndirectX1
1683 ORR rscratch, rscratch, regPBank, LSL #16
1689 ADD rscratch, rpc, #1
1690 BIC rscratch, rscratch,#0x10000
1691 ORR rscratch, rscratch, regPBank, LSL #16
1696 /**********************************************************************************************/
1697 /* MVN/MVP *********************************************************************************** */
1699 //Save RegStatus = regDBank >> 24
1700 MOV rscratch, regDBank, LSR #16
1701 LDRB regDBank , [rpc], #1
1702 LDRB rscratch2 , [rpc], #1
1703 //Restore RegStatus = regDBank >> 24
1704 ORR regDBank, regDBank, rscratch, LSL #16
1705 MOV rscratch , regX, LSR #24
1706 ORR rscratch , rscratch, rscratch2, LSL #16
1708 MOV rscratch2, rscratch
1709 MOV rscratch , regY, LSR #24
1710 ORR rscratch , rscratch, regDBank, LSL #16
1711 S9xSetByteLow rscratch2
1713 LDRB rscratch,[regCPUvar,#RAH_ofs]
1714 MOV regA,regA,LSR #8
1715 ORR regA,regA,rscratch, LSL #24
1716 ADD regX, regX, #0x01000000
1717 SUB regA, regA, #0x00010000
1718 ADD regY, regY, #0x01000000
1719 CMP regA, #0xFFFF0000
1722 MOV rscratch, regA, LSR #24
1723 MOV regA,regA,LSL #8
1724 STRB rscratch,[regCPUvar,#RAH_ofs]
1728 //Save RegStatus = regDBank >> 24
1729 MOV rscratch, regDBank, LSR #16
1730 LDRB regDBank , [rpc], #1
1731 LDRB rscratch2 , [rpc], #1
1732 //Restore RegStatus = regDBank >> 24
1733 ORR regDBank, regDBank, rscratch, LSL #16
1734 MOV rscratch , regX, LSR #24
1735 ORR rscratch , rscratch, rscratch2, LSL #16
1737 MOV rscratch2, rscratch
1738 MOV rscratch , regY, LSR #24
1739 ORR rscratch , rscratch, regDBank, LSL #16
1740 S9xSetByteLow rscratch2
1741 ADD regX, regX, #0x01000000
1742 SUB regA, regA, #0x00010000
1743 ADD regY, regY, #0x01000000
1744 CMP regA, #0xFFFF0000
1749 //Save RegStatus = regDBank >> 24
1750 MOV rscratch, regDBank, LSR #16
1751 LDRB regDBank , [rpc], #1
1752 LDRB rscratch2 , [rpc], #1
1753 //Restore RegStatus = regDBank >> 24
1754 ORR regDBank, regDBank, rscratch, LSL #16
1755 MOV rscratch , regX, LSR #16
1756 ORR rscratch , rscratch, rscratch2, LSL #16
1758 MOV rscratch2, rscratch
1759 MOV rscratch , regY, LSR #16
1760 ORR rscratch , rscratch, regDBank, LSL #16
1761 S9xSetByteLow rscratch2
1763 LDRB rscratch,[regCPUvar,#RAH_ofs]
1764 MOV regA,regA,LSR #8
1765 ORR regA,regA,rscratch, LSL #24
1766 ADD regX, regX, #0x00010000
1767 SUB regA, regA, #0x00010000
1768 ADD regY, regY, #0x00010000
1769 CMP regA, #0xFFFF0000
1772 MOV rscratch, regA, LSR #24
1773 MOV regA,regA,LSL #8
1774 STRB rscratch,[regCPUvar,#RAH_ofs]
1778 //Save RegStatus = regDBank >> 24
1779 MOV rscratch, regDBank, LSR #16
1780 LDRB regDBank , [rpc], #1
1781 LDRB rscratch2 , [rpc], #1
1782 //Restore RegStatus = regDBank >> 24
1783 ORR regDBank, regDBank, rscratch, LSL #16
1784 MOV rscratch , regX, LSR #16
1785 ORR rscratch , rscratch, rscratch2, LSL #16
1787 MOV rscratch2, rscratch
1788 MOV rscratch , regY, LSR #16
1789 ORR rscratch , rscratch, regDBank, LSL #16
1790 S9xSetByteLow rscratch2
1791 ADD regX, regX, #0x00010000
1792 SUB regA, regA, #0x00010000
1793 ADD regY, regY, #0x00010000
1794 CMP regA, #0xFFFF0000
1800 //Save RegStatus = regDBank >> 24
1801 MOV rscratch, regDBank, LSR #16
1802 LDRB regDBank , [rpc], #1
1803 LDRB rscratch2 , [rpc], #1
1804 //Restore RegStatus = regDBank >> 24
1805 ORR regDBank, regDBank, rscratch, LSL #16
1806 MOV rscratch , regX, LSR #24
1807 ORR rscratch , rscratch, rscratch2, LSL #16
1809 MOV rscratch2, rscratch
1810 MOV rscratch , regY, LSR #24
1811 ORR rscratch , rscratch, regDBank, LSL #16
1812 S9xSetByteLow rscratch2
1814 LDRB rscratch,[regCPUvar,#RAH_ofs]
1815 MOV regA,regA,LSR #8
1816 ORR regA,regA,rscratch, LSL #24
1817 SUB regX, regX, #0x01000000
1818 SUB regA, regA, #0x00010000
1819 SUB regY, regY, #0x01000000
1820 CMP regA, #0xFFFF0000
1823 MOV rscratch, regA, LSR #24
1824 MOV regA,regA,LSL #8
1825 STRB rscratch,[regCPUvar,#RAH_ofs]
1829 //Save RegStatus = regDBank >> 24
1830 MOV rscratch, regDBank, LSR #16
1831 LDRB regDBank , [rpc], #1
1832 LDRB rscratch2 , [rpc], #1
1833 //Restore RegStatus = regDBank >> 24
1834 ORR regDBank, regDBank, rscratch, LSL #16
1835 MOV rscratch , regX, LSR #24
1836 ORR rscratch , rscratch, rscratch2, LSL #16
1838 MOV rscratch2, rscratch
1839 MOV rscratch , regY, LSR #24
1840 ORR rscratch , rscratch, regDBank, LSL #16
1841 S9xSetByteLow rscratch2
1842 SUB regX, regX, #0x01000000
1843 SUB regA, regA, #0x00010000
1844 SUB regY, regY, #0x01000000
1845 CMP regA, #0xFFFF0000
1850 //Save RegStatus = regDBank >> 24
1851 MOV rscratch, regDBank, LSR #16
1852 LDRB regDBank , [rpc], #1
1853 LDRB rscratch2 , [rpc], #1
1854 //Restore RegStatus = regDBank >> 24
1855 ORR regDBank, regDBank, rscratch, LSL #16
1856 MOV rscratch , regX, LSR #16
1857 ORR rscratch , rscratch, rscratch2, LSL #16
1859 MOV rscratch2, rscratch
1860 MOV rscratch , regY, LSR #16
1861 ORR rscratch , rscratch, regDBank, LSL #16
1862 S9xSetByteLow rscratch2
1864 LDRB rscratch,[regCPUvar,#RAH_ofs]
1865 MOV regA,regA,LSR #8
1866 ORR regA,regA,rscratch, LSL #24
1867 SUB regX, regX, #0x00010000
1868 SUB regA, regA, #0x00010000
1869 SUB regY, regY, #0x00010000
1870 CMP regA, #0xFFFF0000
1873 MOV rscratch, regA, LSR #24
1874 MOV regA,regA,LSL #8
1875 STRB rscratch,[regCPUvar,#RAH_ofs]
1879 //Save RegStatus = regDBank >> 24
1880 MOV rscratch, regDBank, LSR #16
1881 LDRB regDBank , [rpc], #1
1882 LDRB rscratch2 , [rpc], #1
1883 //Restore RegStatus = regDBank >> 24
1884 ORR regDBank, regDBank, rscratch, LSL #16
1885 MOV rscratch , regX, LSR #16
1886 ORR rscratch , rscratch, rscratch2, LSL #16
1888 MOV rscratch2, rscratch
1889 MOV rscratch , regY, LSR #16
1890 ORR rscratch , rscratch, regDBank, LSL #16
1891 S9xSetByteLow rscratch2
1892 SUB regX, regX, #0x00010000
1893 SUB regA, regA, #0x00010000
1894 SUB regY, regY, #0x00010000
1895 CMP regA, #0xFFFF0000
1900 /**********************************************************************************************/
1901 /* REP/SEP *********************************************************************************** */
1903 // status&=~(*rpc++);
1904 // so possible changes are :
1905 // INDEX = 1 -> 0 : X,Y 8bits -> 16bits
1906 // MEM = 1 -> 0 : A 8bits -> 16bits
1907 //SAVE OLD status for MASK_INDEX & MASK_MEM comparison
1908 MOV rscratch3, rstatus
1909 LDRB rscratch, [rpc], #1
1910 MVN rscratch, rscratch
1911 AND rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
1912 TST rstatus,#MASK_EMUL
1914 //emulation mode on : no changes since it was on before opcode
1915 //just be sure to reset MEM & INDEX accordingly
1916 ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
1919 //NOT in Emulation mode, check INDEX & MEMORY bits
1921 TST rscratch3,#MASK_INDEX
1923 // X & Y were 8bit before
1924 TST rstatus,#MASK_INDEX
1926 // X & Y are now 16bits
1927 MOV regX,regX,LSR #8
1928 MOV regY,regY,LSR #8
1929 1113: //X & Y still in 16bits
1931 TST rscratch3,#MASK_MEM
1933 // A was 8bit before
1934 TST rstatus,#MASK_MEM
1937 MOV regA,regA,LSR #8
1939 LDREQB rscratch,[regCPUvar,#RAH_ofs]
1940 ORREQ regA,regA,rscratch,LSL #24
1947 // so possible changes are :
1948 // INDEX = 0 -> 1 : X,Y 16bits -> 8bits
1949 // MEM = 0 -> 1 : A 16bits -> 8bits
1950 //SAVE OLD status for MASK_INDEX & MASK_MEM comparison
1951 MOV rscratch3, rstatus
1952 LDRB rscratch, [rpc], #1
1953 ORR rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
1954 TST rstatus,#MASK_EMUL
1956 //emulation mode on : no changes sinc eit was on before opcode
1957 //just be sure to have mem & index set accordingly
1958 ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
1961 //NOT in Emulation mode, check INDEX & MEMORY bits
1963 TST rscratch3,#MASK_INDEX
1965 // X & Y were 16bit before
1966 TST rstatus,#MASK_INDEX
1968 // X & Y are now 8bits
1969 MOV regX,regX,LSL #8
1970 MOV regY,regY,LSL #8
1971 10113: //X & Y still in 16bits
1973 TST rscratch3,#MASK_MEM
1975 // A was 16bit before
1976 TST rstatus,#MASK_MEM
1980 MOV rscratch,regA,LSR #24
1981 MOV regA,regA,LSL #8
1982 STRB rscratch,[regCPUvar,#RAH_ofs]
1988 /**********************************************************************************************/
1989 /* XBA *************************************************************************************** */
1992 ADD rscratch,regCPUvar,#RAH_ofs
1993 MOV regA,regA, LSR #24
1994 SWPB regA,regA,[rscratch]
1995 MOVS regA,regA, LSL #24
2001 MOV rscratch, regA, ROR #24 // ll0000hh
2002 ORR rscratch, rscratch, regA, LSR #8// ll0000hh + 00hhll00 -> llhhllhh
2003 MOV regA, rscratch, LSL #16// llhhllhh -> llhh0000
2004 MOVS rscratch,rscratch,LSL #24 //to set Z & N flags with AL
2010 /**********************************************************************************************/
2011 /* RTI *************************************************************************************** */
2013 //INDEX set, MEMORY set
2014 BIC rstatus,rstatus,#0xFF000000
2016 ORR rstatus,rscratch,rstatus
2018 TST rstatus, #MASK_EMUL
2019 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2022 BIC regPBank,regPBank,#0xFF
2023 ORR regPBank,regPBank,rscratch
2025 ADD rscratch, rpc, regPBank, LSL #16
2027 TST rstatus, #MASK_INDEX
2028 //INDEX cleared & was set : 8->16
2029 MOVEQ regX,regX,LSR #8
2030 MOVEQ regY,regY,LSR #8
2031 TST rstatus, #MASK_MEM
2032 //MEMORY cleared & was set : 8->16
2033 LDREQB rscratch,[regCPUvar,#RAH_ofs]
2034 MOVEQ regA,regA,LSR #8
2035 ORREQ regA,regA,rscratch, LSL #24
2040 //INDEX cleared, MEMORY set
2041 BIC rstatus,rstatus,#0xFF000000
2043 ORR rstatus,rscratch,rstatus
2045 TST rstatus, #MASK_EMUL
2046 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2049 BIC regPBank,regPBank,#0xFF
2050 ORR regPBank,regPBank,rscratch
2052 ADD rscratch, rpc, regPBank, LSL #16
2054 TST rstatus, #MASK_INDEX
2055 //INDEX set & was cleared : 16->8
2056 MOVNE regX,regX,LSL #8
2057 MOVNE regY,regY,LSL #8
2058 TST rstatus, #MASK_MEM
2059 //MEMORY cleared & was set : 8->16
2060 LDREQB rscratch,[regCPUvar,#RAH_ofs]
2061 MOVEQ regA,regA,LSR #8
2062 ORREQ regA,regA,rscratch, LSL #24
2067 //INDEX set, MEMORY cleared
2068 BIC rstatus,rstatus,#0xFF000000
2070 ORR rstatus,rscratch,rstatus
2072 TST rstatus, #MASK_EMUL
2073 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2076 BIC regPBank,regPBank,#0xFF
2077 ORR regPBank,regPBank,rscratch
2079 ADD rscratch, rpc, regPBank, LSL #16
2081 TST rstatus, #MASK_INDEX
2082 //INDEX cleared & was set : 8->16
2083 MOVEQ regX,regX,LSR #8
2084 MOVEQ regY,regY,LSR #8
2085 TST rstatus, #MASK_MEM
2086 //MEMORY set & was cleared : 16->8
2087 MOVNE rscratch,regA,LSR #24
2088 MOVNE regA,regA,LSL #8
2089 STRNEB rscratch,[regCPUvar,#RAH_ofs]
2094 //INDEX cleared, MEMORY cleared
2095 BIC rstatus,rstatus,#0xFF000000
2097 ORR rstatus,rscratch,rstatus
2099 TST rstatus, #MASK_EMUL
2100 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
2103 BIC regPBank,regPBank,#0xFF
2104 ORR regPBank,regPBank,rscratch
2106 ADD rscratch, rpc, regPBank, LSL #16
2108 TST rstatus, #MASK_INDEX
2109 //INDEX set & was cleared : 16->8
2110 MOVNE regX,regX,LSL #8
2111 MOVNE regY,regY,LSL #8
2112 TST rstatus, #MASK_MEM
2113 //MEMORY set & was cleared : 16->8
2114 //MEMORY set & was cleared : 16->8
2115 MOVNE rscratch,regA,LSR #24
2116 MOVNE regA,regA,LSL #8
2117 STRNEB rscratch,[regCPUvar,#RAH_ofs]
2123 /**********************************************************************************************/
2124 /* STP/WAI/DB ******************************************************************************** */
2127 LDRB rscratch,[regCPUvar,#IRQActive_ofs]
2128 MOVS rscratch,rscratch
2133 CPU.WaitingForInterrupt = TRUE;
2138 CPU.Cycles = CPU.NextEvent;
2140 STRB rscratch,[regCPUvar,#WaitingForInterrupt_ofs]
2141 LDR regCycles,[regCPUvar,#NextEvent_ofs]
2143 if (IAPU.APUExecuting)
2145 ICPU.CPUExecuting = FALSE;
2149 } while (APU.Cycles < CPU.NextEvent);
2150 ICPU.CPUExecuting = TRUE;
2153 LDRB rscratch,[regCPUvar,#APUExecuting_ofs]
2154 MOVS rscratch,rscratch
2162 //CPU.Flags |= DEBUG_MODE_FLAG;
2164 .macro Op42 /*Reserved Snes9X*/
2167 /**********************************************************************************************/
2168 /* AND ******************************************************************************** */
2170 LDRB rscratch , [rpc], #1
2171 ANDS regA , regA, rscratch, LSL #24
2176 LDRB rscratch2 , [rpc,#1]
2177 LDRB rscratch , [rpc], #2
2178 ORR rscratch, rscratch, rscratch2, LSL #8
2179 ANDS regA , regA, rscratch, LSL #16
2198 /**********************************************************************************************/
2199 /* EOR ******************************************************************************** */
2201 LDRB rscratch2 , [rpc, #1]
2202 LDRB rscratch , [rpc], #2
2203 ORR rscratch, rscratch, rscratch2,LSL #8
2204 EORS regA, regA, rscratch,LSL #16
2211 LDRB rscratch , [rpc], #1
2212 EORS regA, regA, rscratch,LSL #24
2218 /**********************************************************************************************/
2219 /* STA *************************************************************************************** */
2222 //TST rstatus, #MASK_INDEX
2227 //TST rstatus, #MASK_INDEX
2232 /**********************************************************************************************/
2233 /* BIT *************************************************************************************** */
2235 LDRB rscratch , [rpc], #1
2236 TST regA, rscratch, LSL #24
2241 LDRB rscratch2 , [rpc, #1]
2242 LDRB rscratch , [rpc], #2
2243 ORR rscratch, rscratch, rscratch2, LSL #8
2244 TST regA, rscratch, LSL #16
2254 /**********************************************************************************************/
2255 /* LDY *************************************************************************************** */
2257 LDRB rscratch , [rpc], #1
2258 MOVS regY, rscratch, LSL #24
2263 LDRB rscratch2 , [rpc, #1]
2264 LDRB rscratch , [rpc], #2
2265 ORR rscratch, rscratch, rscratch2, LSL #8
2266 MOVS regY, rscratch, LSL #16
2271 /**********************************************************************************************/
2272 /* LDX *************************************************************************************** */
2274 LDRB rscratch , [rpc], #1
2275 MOVS regX, rscratch, LSL #24
2280 LDRB rscratch2 , [rpc, #1]
2281 LDRB rscratch , [rpc], #2
2282 ORR rscratch, rscratch, rscratch2, LSL #8
2283 MOVS regX, rscratch, LSL #16
2288 /**********************************************************************************************/
2289 /* LDA *************************************************************************************** */
2291 LDRB rscratch , [rpc], #1
2292 MOVS regA, rscratch, LSL #24
2297 LDRB rscratch2 , [rpc, #1]
2298 LDRB rscratch , [rpc], #2
2299 ORR rscratch, rscratch, rscratch2, LSL #8
2300 MOVS regA, rscratch, LSL #16
2305 /**********************************************************************************************/
2306 /* CMY *************************************************************************************** */
2308 LDRB rscratch , [rpc], #1
2309 SUBS rscratch2 , regY , rscratch, LSL #24
2310 BICCC rstatus, rstatus, #MASK_CARRY
2311 ORRCS rstatus, rstatus, #MASK_CARRY
2316 LDRB rscratch2 , [rpc, #1]
2317 LDRB rscratch , [rpc], #2
2318 ORR rscratch, rscratch, rscratch2, LSL #8
2319 SUBS rscratch2 , regY, rscratch, LSL #16
2320 BICCC rstatus, rstatus, #MASK_CARRY
2321 ORRCS rstatus, rstatus, #MASK_CARRY
2330 /**********************************************************************************************/
2331 /* CMP *************************************************************************************** */
2333 LDRB rscratch , [rpc], #1
2334 SUBS rscratch2 , regA , rscratch, LSL #24
2335 BICCC rstatus, rstatus, #MASK_CARRY
2336 ORRCS rstatus, rstatus, #MASK_CARRY
2341 LDRB rscratch2 , [rpc,#1]
2342 LDRB rscratch , [rpc], #2
2343 ORR rscratch, rscratch, rscratch2, LSL #8
2344 SUBS rscratch2 , regA, rscratch, LSL #16
2345 BICCC rstatus, rstatus, #MASK_CARRY
2346 ORRCS rstatus, rstatus, #MASK_CARRY
2351 /**********************************************************************************************/
2352 /* CMX *************************************************************************************** */
2354 LDRB rscratch , [rpc], #1
2355 SUBS rscratch2 , regX , rscratch, LSL #24
2356 BICCC rstatus, rstatus, #MASK_CARRY
2357 ORRCS rstatus, rstatus, #MASK_CARRY
2362 LDRB rscratch2 , [rpc,#1]
2363 LDRB rscratch , [rpc], #2
2364 ORR rscratch, rscratch, rscratch2, LSL #8
2365 SUBS rscratch2 , regX, rscratch, LSL #16
2366 BICCC rstatus, rstatus, #MASK_CARRY
2367 ORRCS rstatus, rstatus, #MASK_CARRY
2375 CLI_OPE_REC_Nos_Layer0
2376 nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103)
2377 nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103)
2379 CLI_OPE_Nos_Ope_Layer0
2380 n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103)
2381 n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103)
2384 nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103)
2385 nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103)
2391 [GNV] : utilisation de la lard (laccdate) pour afficher les openings.
2392 +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate
2394 [Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée
2396 +données nécessaires : opening date tréso=date compta=laccdate=BD-1
2397 +données nécessaires : opening date tréso=date compta=laccdate-1
2398 +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate