vcs.maemo.org Git - drnoksnes/blob - os9x_65c816.s

   1
   2 /****************************************************************
   3 ****************************************************************/
   4 @ notaz
   5 .equiv ASM_SPC700,              1               ;@ 1 = use notaz's ASM_SPC700 core
   6
   7 /****************************************************************
   8         DEFINES
   9 ****************************************************************/
  10
  11 .equ MAP_LAST,  12
  12
  13 rstatus         .req R4  @ format : 0xff800000
  14 reg_d_bank      .req R4  @ format : 0x000000ll
  15 reg_a           .req R5  @ format : 0xhhll0000 or 0xll000000
  16 reg_d           .req R6  @ format : 0xhhll0000
  17 reg_p_bank      .req R6  @ format : 0x000000ll
  18 reg_x           .req R7  @ format : 0xhhll0000 or 0xll000000
  19 reg_s           .req R8  @ format : 0x0000hhll
  20 reg_y           .req R9  @ format : 0xhhll0000 or 0xll000000
  21
  22 rpc             .req R10 @ 32bits address
  23 reg_cycles      .req R11 @ 32bits counter
  24 regpcbase       .req R12 @ 32bits address
  25
  26 rscratch        .req R0  @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD
  27 regopcode       .req R0  @ format : 0x000000ll
  28 rscratch2       .req R1  @ format : 0xhhll for calculation and value
  29 rscratch3       .req R2  @
  30 rscratch4       .req R3  @ ??????
  31
  32 @ used for SBC opcode
  33 rscratch9       .req R10 @ ??????
  34
  35 reg_cpu_var .req R14
  36
  37
  38 @ not used
  39 @ R13   @ Pointer 32 bit on a struct.
  40
  41 @ R15 = pc (sic!)
  42
  43 .equ STATUS_SHIFTER,            24
  44 .equ MASK_EMUL,         (1<<(STATUS_SHIFTER-1))
  45 .equ MASK_SHIFTER_CARRY,        (STATUS_SHIFTER+1)
  46 .equ    MASK_CARRY,             (1<<(STATUS_SHIFTER))  @ 0
  47 .equ    MASK_ZERO,              (2<<(STATUS_SHIFTER))  @ 1
  48 .equ MASK_IRQ,          (4<<(STATUS_SHIFTER))  @ 2
  49 .equ MASK_DECIMAL,              (8<<(STATUS_SHIFTER))  @ 3
  50 .equ    MASK_INDEX,             (16<<(STATUS_SHIFTER)) @ 4  @ 1
  51 .equ    MASK_MEM,               (32<<(STATUS_SHIFTER)) @ 5  @ 2
  52 .equ    MASK_OVERFLOW,          (64<<(STATUS_SHIFTER)) @ 6  @ 4
  53 .equ    MASK_NEG,               (128<<(STATUS_SHIFTER))@ 7  @ 8
  54
  55 .equ ONE_CYCLE, 6
  56 .equ SLOW_ONE_CYCLE, 8
  57
  58 .equ    NMI_FLAG,           (1 << 7)
  59 .equ IRQ_PENDING_FLAG,    (1 << 11)
  60 .equ SCAN_KEYS_FLAG,        (1 << 4)
  61
  62
  63 .equ MEMMAP_BLOCK_SIZE, (0x1000)
  64 .equ MEMMAP_SHIFT, 12
  65 .equ MEMMAP_MASK, (0xFFF)
  66
  67 /****************************************************************
  68         MACROS
  69 ****************************************************************/
  70
  71 @ #include "os9x_65c816_mac_gen.h"
  72 /*****************************************************************/
  73 /*     Offset in SCPUState structure                             */
  74 /*****************************************************************/
  75 .equ Flags_ofs,             0
  76 .equ BranchSkip_ofs,    4
  77 .equ NMIActive_ofs,             5
  78 .equ IRQActive_ofs,             6
  79 .equ WaitingForInterrupt_ofs,   7
  80
  81 .equ    RPB_ofs,                8
  82 .equ    RDB_ofs,                9
  83 .equ    RP_ofs,             10
  84 .equ    RA_ofs,             12
  85 .equ    RAH_ofs,            13
  86 .equ    RD_ofs,             14
  87 .equ    RX_ofs,             16
  88 .equ    RS_ofs,             18
  89 .equ    RY_ofs,             20
  90 @.equ   RPC_ofs,                22
  91
  92 .equ PC_ofs,                    24
  93 .equ Cycles_ofs,                28
  94 .equ PCBase_ofs,                32
  95
  96 .equ PCAtOpcodeStart_ofs,       36
  97 .equ WaitAddress_ofs,           40
  98 .equ WaitCounter_ofs,           44
  99 .equ NextEvent_ofs,                 48
 100 .equ V_Counter_ofs,                 52
 101 .equ MemSpeed_ofs,                  56
 102 .equ MemSpeedx2_ofs,            60
 103 .equ FastROMSpeed_ofs,      64
 104 .equ AutoSaveTimer_ofs,     68
 105 .equ NMITriggerPoint_ofs,       72
 106 .equ NMICycleCount_ofs,     76
 107 .equ IRQCycleCount_ofs,     80
 108
 109 .equ InDMA_ofs,                 84
 110 .equ WhichEvent,                    85
 111 .equ SRAMModified_ofs,      86
 112 .equ BRKTriggered_ofs,      87
 113 .equ    asm_OPTABLE_ofs,                88
 114 .equ TriedInterleavedMode2_ofs, 92
 115
 116 .equ Map_ofs,               96
 117 .equ WriteMap_ofs,      100
 118 .equ MemorySpeed_ofs,   104
 119 .equ BlockIsRAM_ofs,    108
 120 .equ SRAM,                      112
 121 .equ BWRAM,             116
 122 .equ SRAMMask,          120
 123
 124 .equ    APUExecuting_ofs,   122
 125 @ notaz
 126 .equ    APU_Cycles,         124
 127
 128 /*****************************************************************/
 129
 130 /* prepare */
 131 .macro          PREPARE_C_CALL
 132         STMFD   R13!,{R12,R14}
 133 .endm
 134 .macro          PREPARE_C_CALL_R0
 135         STMFD   R13!,{R0,R12,R14}
 136 .endm
 137 .macro          PREPARE_C_CALL_R0R1
 138         STMFD   R13!,{R0,R1,R12,R14}
 139 .endm
 140 .macro          PREPARE_C_CALL_LIGHT
 141         STMFD   R13!,{R14}
 142 .endm
 143 .macro          PREPARE_C_CALL_LIGHTR12
 144         STMFD   R13!,{R12,R14}
 145 .endm
 146 /* restore */
 147 .macro          RESTORE_C_CALL
 148         LDMFD   R13!,{R12,R14}
 149 .endm
 150 .macro          RESTORE_C_CALL_R0
 151         LDMFD   R13!,{R0,R12,R14}
 152 .endm
 153 .macro          RESTORE_C_CALL_R1
 154         LDMFD   R13!,{R1,R12,R14}
 155 .endm
 156 .macro          RESTORE_C_CALL_LIGHT
 157         LDMFD   R13!,{R14}
 158 .endm
 159 .macro          RESTORE_C_CALL_LIGHTR12
 160         LDMFD   R13!,{R12,R14}
 161 .endm
 162
 163
 164 @ --------------
 165 .macro          LOAD_REGS
 166     @ notaz
 167     add     r0,reg_cpu_var,#8
 168     ldmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 169     @ rstatus (P) & reg_d_bank
 170     mov     reg_d_bank,r1,lsl #16
 171     mov     reg_d_bank,reg_d_bank,lsr #24
 172     mov     r0,r1,lsr #16
 173         orrs    rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24
 174         @ if Carry set, then EMULATION bit was set
 175         orrcs   rstatus,rstatus,#MASK_EMUL
 176     @ reg_d & reg_p_bank
 177     mov     reg_d,reg_a,lsr #16
 178     mov     reg_d,reg_d,lsl #8
 179     orr     reg_d,reg_d,r1,lsl #24
 180     mov     reg_d,reg_d,ror #24    @ 0xdddd00pb
 181     @ reg_x, reg_s
 182     mov     reg_s,reg_x,lsr #16
 183         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 184         tst             rstatus,#MASK_INDEX
 185         movne   reg_x,reg_x,lsl #24
 186         movne   reg_y,reg_y,lsl #24
 187         moveq   reg_x,reg_x,lsl #16
 188         moveq   reg_y,reg_y,lsl #16
 189         tst             rstatus,#MASK_MEM
 190         movne   reg_a,reg_a,lsl #24
 191         moveq   reg_a,reg_a,lsl #16
 192
 193 /*
 194     @ reg_d & reg_p_bank share the same register
 195         LDRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 196         LDRH            rscratch,[reg_cpu_var,#RD_ofs]
 197         ORR             reg_d,reg_d,rscratch, LSL #16
 198         @ rstatus & reg_d_bank share the same register
 199         LDRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 200         LDRH            rscratch,[reg_cpu_var,#RP_ofs]
 201         ORRS            rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24
 202         @ if Carry set, then EMULATION bit was set
 203         ORRCS           rstatus,rstatus,#MASK_EMUL
 204         @
 205         LDRH            reg_a,[reg_cpu_var,#RA_ofs]
 206         LDRH            reg_x,[reg_cpu_var,#RX_ofs]
 207         LDRH            reg_y,[reg_cpu_var,#RY_ofs]
 208         LDRH            reg_s,[reg_cpu_var,#RS_ofs]
 209         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 210         TST             rstatus,#MASK_INDEX
 211         MOVNE           reg_x,reg_x,LSL #24
 212         MOVNE           reg_y,reg_y,LSL #24
 213         MOVEQ           reg_x,reg_x,LSL #16
 214         MOVEQ           reg_y,reg_y,LSL #16
 215         TST             rstatus,#MASK_MEM
 216         MOVNE           reg_a,reg_a,LSL #24
 217         MOVEQ           reg_a,reg_a,LSL #16
 218
 219         LDR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 220         LDR             rpc,[reg_cpu_var,#PC_ofs]
 221         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 222 */
 223 .endm
 224
 225
 226 .macro          SAVE_REGS
 227     @ notaz
 228     @ reg_p_bank, reg_d_bank and rstatus
 229     mov         r1, rstatus, lsr #16
 230     orr     r1, r1, reg_p_bank, lsl #24
 231         movs    r1, r1, lsr #8
 232         orrcs   r1, r1, #0x100 @ EMULATION bit
 233     orr     r1, r1, reg_d_bank, lsl #24
 234     mov     r1, r1, ror #16
 235     @ reg_a, reg_d
 236         tst             rstatus,#MASK_MEM
 237         ldrneh  r0, [reg_cpu_var,#RA_ofs]
 238         bicne   r0, r0,#0xFF
 239         orrne   reg_a, r0, reg_a,lsr #24
 240         moveq   reg_a, reg_a, lsr #16
 241     mov     reg_d, reg_d, lsr #16
 242         orr     reg_a, reg_a, reg_d, lsl #16
 243         @ Shift X&Y according to the current mode (INDEX, MEMORY bits)
 244         tst             rstatus,#MASK_INDEX
 245         movne   reg_x,reg_x,LSR #24
 246         movne   reg_y,reg_y,LSR #24
 247         moveq   reg_x,reg_x,LSR #16
 248         moveq   reg_y,reg_y,LSR #16
 249     @ reg_x, reg_s
 250         orr     reg_x, reg_x, reg_s, lsl #16
 251     @ store
 252     add     r0,reg_cpu_var,#8
 253     stmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 254
 255 /*
 256     @ reg_d & reg_p_bank is same register
 257         STRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 258         MOV             rscratch,reg_d, LSR #16
 259         STRH            rscratch,[reg_cpu_var,#RD_ofs]
 260         @ rstatus & reg_d_bank is same register
 261         STRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 262         MOVS            rscratch, rstatus, LSR #STATUS_SHIFTER
 263         ORRCS           rscratch,rscratch,#0x100 @ EMULATION bit
 264         STRH            rscratch,[reg_cpu_var,#RP_ofs]
 265         @
 266         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 267         TST             rstatus,#MASK_INDEX
 268         MOVNE           rscratch,reg_x,LSR #24
 269         MOVNE           rscratch2,reg_y,LSR #24
 270         MOVEQ           rscratch,reg_x,LSR #16
 271         MOVEQ           rscratch2,reg_y,LSR #16
 272         STRH            rscratch,[reg_cpu_var,#RX_ofs]
 273         STRH            rscratch2,[reg_cpu_var,#RY_ofs]
 274         TST             rstatus,#MASK_MEM
 275         LDRNEH          rscratch,[reg_cpu_var,#RA_ofs]
 276         BICNE           rscratch,rscratch,#0xFF
 277         ORRNE           rscratch,rscratch,reg_a,LSR #24
 278         MOVEQ           rscratch,reg_a,LSR #16
 279         STRH            rscratch,[reg_cpu_var,#RA_ofs]
 280
 281         STRH            reg_s,[reg_cpu_var,#RS_ofs]
 282         STR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 283         STR             rpc,[reg_cpu_var,#PC_ofs]
 284
 285         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 286 */
 287 .endm
 288
 289 /*****************************************************************/
 290 .macro          ADD1CYCLE
 291                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 292 .endm
 293 .macro          ADD1CYCLENE
 294                 addne   reg_cycles,reg_cycles, #ONE_CYCLE
 295 .endm
 296 .macro          ADD1CYCLEEQ
 297                 addeq   reg_cycles,reg_cycles, #ONE_CYCLE
 298 .endm
 299
 300 .macro          ADD2CYCLE
 301                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 302 .endm
 303 .macro          ADD2CYCLENE
 304                 addne   reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 305 .endm
 306 .macro          ADD2CYCLE2MEM
 307                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 308                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 309                 add     reg_cycles, reg_cycles, rscratch, LSL #1
 310 .endm
 311 .macro          ADD2CYCLE1MEM
 312                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 313                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 314                 add     reg_cycles, reg_cycles, rscratch
 315 .endm
 316
 317 .macro          ADD3CYCLE
 318                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*3)
 319 .endm
 320
 321 .macro          ADD1CYCLE1MEM
 322                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 323                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 324                 add     reg_cycles, reg_cycles, rscratch
 325 .endm
 326
 327 .macro          ADD1CYCLE2MEM
 328                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 329                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 330                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 331 .endm
 332
 333 .macro          ADD1MEM
 334                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 335                 add     reg_cycles, reg_cycles, rscratch
 336 .endm
 337
 338 .macro          ADD2MEM
 339                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 340                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 341 .endm
 342
 343 .macro          ADD3MEM
 344                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 345                 add     reg_cycles, rscratch, reg_cycles
 346                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 347 .endm
 348
 349 /**************/
 350 .macro          ClearDecimal
 351                 BIC     rstatus,rstatus,#MASK_DECIMAL
 352 .endm
 353 .macro          SetDecimal
 354                 ORR     rstatus,rstatus,#MASK_DECIMAL
 355 .endm
 356 .macro          SetIRQ
 357                 ORR     rstatus,rstatus,#MASK_IRQ
 358 .endm
 359 .macro          ClearIRQ
 360                 BIC     rstatus,rstatus,#MASK_IRQ
 361 .endm
 362
 363 .macro          CPUShutdown
 364 @ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
 365                 LDR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 366                 CMP             rpc,rscratch
 367                 BNE             5431f
 368 @ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
 369                 LDR             rscratch,[reg_cpu_var,#Flags_ofs]
 370                 LDR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 371                 TST             rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
 372                 BNE             5432f
 373                 MOVS            rscratch2,rscratch2
 374                 BNE             5432f
 375 @ CPU.WaitAddress = NULL;
 376                 MOV             rscratch,#0
 377                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 378 @ if (Settings.SA1)
 379 @               S9xSA1ExecuteDuringSleep ();            : TODO
 380
 381 @           CPU.Cycles = CPU.NextEvent;
 382                 LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
 383                 LDRB            r0,[reg_cpu_var,#APUExecuting_ofs]
 384                 MOVS            r0,r0
 385                 BEQ             5431f
 386 @           if (IAPU.APUExecuting)
 387 /*          {
 388                 ICPU.CPUExecuting = FALSE;
 389                 do
 390                 {
 391                     APU_EXECUTE1();
 392                 } while (APU.Cycles < CPU.NextEvent);
 393                 ICPU.CPUExecuting = TRUE;
 394             }
 395         */
 396                 asmAPU_EXECUTE2
 397                 B               5431f
 398 @.pool
 399 5432:
 400 /*      else
 401         if (CPU.WaitCounter >= 2)
 402             CPU.WaitCounter = 1;
 403         else
 404             CPU.WaitCounter--;
 405 */
 406                 CMP             rscratch2,#1
 407                 MOVHI           rscratch2,#1
 408                 @ SUBLS         rscratch2,rscratch2,#1
 409                 MOVLS           rscratch2,#0
 410                 STR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 411 5431:
 412
 413 .endm
 414 .macro          BranchCheck0
 415                 /*in rsctach : OpAddress
 416                 /*destroy rscratch2*/
 417                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 418                 MOVS    rscratch2,rscratch2
 419                 BEQ     1110f
 420                 MOV     rscratch2,#0
 421                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 422                 SUB     rscratch2,rpc,regpcbase
 423                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 424                 CMP     rscratch2,rscratch
 425                 BHI     1111f
 426 1110:
 427 .endm
 428 .macro          BranchCheck1
 429                 /*in rsctach : OpAddress
 430                 /*destroy rscratch2*/
 431                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 432                 MOVS    rscratch2,rscratch2
 433                 BEQ     1110f
 434                 MOV     rscratch2,#0
 435                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 436                 SUB     rscratch2,rpc,regpcbase
 437                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 438                 CMP     rscratch2,rscratch
 439                 BHI     1111f
 440 1110:
 441 .endm
 442 .macro          BranchCheck2
 443                 /*in rsctach : OpAddress
 444                 /*destroy rscratch2*/
 445                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 446                 MOVS    rscratch2,rscratch2
 447                 BEQ     1110f
 448                 MOV     rscratch2,#0
 449                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 450                 SUB     rscratch2,rpc,regpcbase
 451                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 452                 CMP     rscratch2,rscratch
 453                 BHI     1111f
 454 1110:
 455 .endm
 456
 457 .macro          S9xSetPCBase
 458                 @  in  : rscratch (0x00hhmmll)
 459                 PREPARE_C_CALL
 460                 BL      asm_S9xSetPCBase
 461                 RESTORE_C_CALL
 462                 LDR     rpc,[reg_cpu_var,#PC_ofs]
 463                 LDR     regpcbase,[reg_cpu_var,#PCBase_ofs]
 464 .endm
 465
 466 .macro          S9xFixCycles
 467                 TST             rstatus,#MASK_EMUL
 468                 LDRNE           rscratch, = jumptable1     @ Mode 0 : M=1,X=1
 469                 BNE             991111f
 470                 @ EMULATION=0
 471                 TST             rstatus,#MASK_MEM
 472                 BEQ             991112f
 473                 @ MEMORY=1
 474                 TST             rstatus,#MASK_INDEX
 475                 @ INDEX=1  @ Mode 0 : M=1,X=1
 476                 LDRNE           rscratch, = jumptable1
 477                 @ INDEX=0  @ Mode 1 : M=1,X=0
 478                 LDREQ           rscratch, = jumptable2
 479                 B               991111f
 480 991112:         @ MEMORY=0
 481                 TST             rstatus,#MASK_INDEX
 482                 @ INDEX=1   @ Mode 3 : M=0,X=1
 483                 LDRNE           rscratch, = jumptable4
 484                 @ INDEX=0   @ Mode 2 : M=0,X=0
 485                 LDREQ           rscratch, = jumptable3
 486 991111:
 487                 STR             rscratch,[reg_cpu_var,#asm_OPTABLE_ofs]
 488 .endm
 489 /*
 490 .macro          S9xOpcode_NMI
 491                 SAVE_REGS
 492                 PREPARE_C_CALL_LIGHT
 493                 BL      asm_S9xOpcode_NMI
 494                 RESTORE_C_CALL_LIGHT
 495                 LOAD_REGS
 496 .endm
 497 .macro          S9xOpcode_IRQ
 498                 SAVE_REGS
 499                 PREPARE_C_CALL_LIGHT
 500                 BL      asm_S9xOpcode_IRQ
 501                 RESTORE_C_CALL_LIGHT
 502                 LOAD_REGS
 503 .endm
 504 */
 505 .macro          S9xDoHBlankProcessing
 506                 SAVE_REGS
 507                 PREPARE_C_CALL_LIGHT
 508 @               BL      asm_S9xDoHBlankProcessing
 509                 BL      S9xDoHBlankProcessing
 510                 RESTORE_C_CALL_LIGHT
 511                 LOAD_REGS
 512 .endm
 513
 514 /********************************/
 515 .macro          EXEC_OP
 516                 LDR             R1,[reg_cpu_var,#asm_OPTABLE_ofs]
 517                 STR             rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs]
 518                 ADD1MEM
 519                 LDRB            R0, [rpc], #1
 520
 521                 LDR             PC, [R1,R0, LSL #2]
 522 .endm
 523 .macro          NEXTOPCODE
 524                 LDR                     rscratch,[reg_cpu_var,#NextEvent_ofs]
 525                 CMP                     reg_cycles,rscratch
 526                 BLT                     mainLoop
 527                 S9xDoHBlankProcessing
 528                 B                       mainLoop
 529 .endm
 530
 531 .macro          asmAPU_EXECUTE
 532                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 533                 CMP             R0,#1   @ spc700 enabled, hack mode off
 534                 BNE                 43210f
 535                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 536         SUBS        R0,reg_cycles,R0
 537         BMI         43210f
 538 .if ASM_SPC700
 539                 PREPARE_C_CALL_LIGHTR12
 540                 BL              spc700_execute
 541                 RESTORE_C_CALL_LIGHTR12
 542         SUB     R0,reg_cycles,R0 @ sub cycles left
 543                 STR             R0,[reg_cpu_var,#APU_Cycles]
 544 .else
 545         @ SAVE_REGS
 546                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 547                 PREPARE_C_CALL_LIGHTR12
 548                 BL              asm_APU_EXECUTE
 549                 RESTORE_C_CALL_LIGHTR12
 550                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 551 .endif
 552         @ LOAD_REGS
 553                 @ S9xFixCycles
 554 43210:
 555 .endm
 556
 557 .macro          asmAPU_EXECUTE2
 558 .if ASM_SPC700
 559                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 560                 CMP             R0,#1   @ spc700 enabled, hack mode off
 561                 BNE                 43211f
 562                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 563         SUBS        R0,reg_cycles,R0 @ reg_cycles == NextEvent
 564         BLE         43211f
 565                 PREPARE_C_CALL_LIGHTR12
 566                 BL              spc700_execute
 567                 RESTORE_C_CALL_LIGHTR12
 568         SUB     R0,reg_cycles,R0 @ sub cycles left
 569                 STR             R0,[reg_cpu_var,#APU_Cycles]
 570 43211:
 571 .else
 572                 @ SAVE_REGS
 573                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 574                 PREPARE_C_CALL_LIGHTR12
 575                 BL              asm_APU_EXECUTE2
 576                 RESTORE_C_CALL_LIGHTR12
 577                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 578                 @ LOAD_REGS
 579 .endif
 580 .endm
 581
 582 @ #include "os9x_65c816_mac_mem.h"
 583 .macro          S9xGetWord
 584                 @  in  : rscratch (0x00hhmmll)
 585                 @  out : rscratch (0xhhll0000)
 586                 STMFD   R13!,{PC} @ Push return address
 587                 B       asmS9xGetWord
 588                 MOV     R0,R0
 589                 MOV     R0, R0, LSL #16
 590 .endm
 591 .macro          S9xGetWordLow
 592                 @  in  : rscratch (0x00hhmmll)
 593                 @  out : rscratch (0x0000hhll)
 594                 STMFD   R13!,{PC} @ Push return address
 595                 B       asmS9xGetWord
 596                 MOV     R0,R0
 597 .endm
 598 .macro          S9xGetWordRegStatus     reg
 599                 @  in  : rscratch (0x00hhmmll)
 600                 @  out : reg      (0xhhll0000)
 601                 @  flags have to be updated with read value
 602                 STMFD   R13!,{PC} @ Push return address
 603                 B       asmS9xGetWord
 604                 MOV     R0,R0
 605                 MOVS    \reg, R0, LSL #16
 606 .endm
 607 .macro          S9xGetWordRegNS reg
 608                 @  in  : rscratch (0x00hhmmll)
 609                 @  out : reg (0xhhll0000)
 610                 @  DOES NOT DESTROY rscratch (R0)
 611                 STMFD   R13!,{R0}
 612                 STMFD   R13!,{PC} @ Push return address
 613                 B       asmS9xGetWord
 614                 MOV     R0,R0
 615                 MOV     \reg, R0, LSL #16
 616                 LDMFD   R13!,{R0}
 617 .endm
 618 .macro          S9xGetWordLowRegNS      reg
 619                 @  in  : rscratch (0x00hhmmll)
 620                 @  out : reg (0xhhll0000)
 621                 @  DOES NOT DESTROY rscratch (R0)
 622                 STMFD   R13!,{R0}
 623                 STMFD   R13!,{PC} @ Push return address
 624                 B       asmS9xGetWord
 625                 MOV     R0,R0
 626                 MOV     \reg, R0
 627                 LDMFD   R13!,{R0}
 628 .endm
 629
 630 .macro          S9xGetByte
 631                 @  in  : rscratch (0x00hhmmll)
 632                 @  out : rscratch (0xll000000)
 633                 STMFD   R13!,{PC} @ Push return address
 634                 B       asmS9xGetByte
 635                 MOV     R0,R0
 636                 MOV     R0, R0, LSL #24
 637 .endm
 638 .macro          S9xGetByteLow
 639                 @  in  : rscratch (0x00hhmmll)
 640                 @  out : rscratch (0x000000ll)
 641                 STMFD   R13!,{PC}
 642                 B       asmS9xGetByte
 643                 MOV     R0,R0
 644 .endm
 645 .macro          S9xGetByteRegStatus     reg
 646                 @  in  : rscratch (0x00hhmmll)
 647                 @  out : reg      (0xll000000)
 648                 @  flags have to be updated with read value
 649                 STMFD   R13!,{PC} @ Push return address
 650                 B       asmS9xGetByte
 651                 MOV     R0,R0
 652                 MOVS    \reg, R0, LSL #24
 653 .endm
 654 .macro          S9xGetByteRegNS reg
 655                 @  in  : rscratch (0x00hhmmll)
 656                 @  out : reg      (0xll000000)
 657                 @  DOES NOT DESTROY rscratch (R0)
 658                 STMFD   R13!,{R0}
 659                 STMFD   R13!,{PC} @ Push return address
 660                 B       asmS9xGetByte
 661                 MOV     R0,R0
 662                 MOVS    \reg, R0, LSL #24
 663                 LDMFD   R13!,{R0}
 664 .endm
 665 .macro          S9xGetByteLowRegNS      reg
 666                 @  in  : rscratch (0x00hhmmll)
 667                 @  out : reg      (0x000000ll)
 668                 @  DOES NOT DESTROY rscratch (R0)
 669                 STMFD   R13!,{R0}
 670                 STMFD   R13!,{PC} @ Push return address
 671                 B       asmS9xGetByte
 672                 MOV     R0,R0
 673                 MOVS    \reg, R0
 674                 LDMFD   R13!,{R0}
 675 .endm
 676
 677 .macro          S9xSetWord      regValue
 678                 @  in  : regValue  (0xhhll0000)
 679                 @  in  : rscratch=address   (0x00hhmmll)
 680                 MOV     R1,\regValue, LSR #16
 681                 STMFD   R13!,{PC} @ Push return address
 682                 B       asmS9xSetWord
 683                 MOV     R0,R0
 684 .endm
 685 .macro          S9xSetWordZero
 686                 @  in  : rscratch=address   (0x00hhmmll)
 687                 MOV     R1,#0
 688                 STMFD   R13!,{PC} @ Push return address
 689                 B       asmS9xSetWord
 690                 MOV     R0,R0
 691 .endm
 692 .macro          S9xSetWordLow   regValue
 693                 @  in  : regValue  (0x0000hhll)
 694                 @  in  : rscratch=address   (0x00hhmmll)
 695                 MOV     R1,\regValue
 696                 STMFD   R13!,{PC} @ Push return address
 697                 B       asmS9xSetWord
 698                 MOV     R0,R0
 699 .endm
 700 .macro          S9xSetByte      regValue
 701                 @  in  : regValue  (0xll000000)
 702                 @  in  : rscratch=address   (0x00hhmmll)
 703                 MOV     R1,\regValue, LSR #24
 704                 STMFD   R13!,{PC} @ Push return address
 705                 B       asmS9xSetByte
 706                 MOV     R0,R0
 707 .endm
 708 .macro          S9xSetByteZero
 709                 @  in  : rscratch=address   (0x00hhmmll)
 710                 MOV     R1,#0
 711                 STMFD   R13!,{PC} @ Push return address
 712                 B       asmS9xSetByte
 713                 MOV     R0,R0
 714 .endm
 715 .macro          S9xSetByteLow   regValue
 716                 @  in  : regValue  (0x000000ll)
 717                 @  in  : rscratch=address   (0x00hhmmll)
 718                 MOV     R1,\regValue
 719                 STMFD   R13!,{PC} @ Push return address
 720                 B       asmS9xSetByte
 721                 MOV     R0,R0
 722 .endm
 723
 724
 725 @  ===========================================
 726 @  ===========================================
 727 @  Adressing mode
 728 @  ===========================================
 729 @  ===========================================
 730
 731
 732 .macro          Absolute
 733                 ADD2MEM
 734                 LDRB    rscratch2    , [rpc, #1]
 735                 LDRB    rscratch   , [rpc],#2
 736                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 737                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 738 .endm
 739 .macro          AbsoluteIndexedIndirectX0
 740                 ADD2MEM
 741                 LDRB    rscratch2    , [rpc, #1]
 742                 LDRB    rscratch   , [rpc], #2
 743                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 744                 ADD     rscratch    , reg_x, rscratch, LSL #16
 745                 MOV     rscratch , rscratch, LSR #16
 746                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 747                 S9xGetWordLow
 748
 749 .endm
 750 .macro          AbsoluteIndexedIndirectX1
 751                 ADD2MEM
 752                 LDRB    rscratch2    , [rpc, #1]
 753                 LDRB    rscratch   , [rpc], #2
 754                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 755                 ADD     rscratch    , rscratch, reg_x, LSR #24
 756                 BIC     rscratch , rscratch, #0x00FF0000
 757                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 758                 S9xGetWordLow
 759
 760 .endm
 761 .macro          AbsoluteIndirectLong
 762                 ADD2MEM
 763                 LDRB                    rscratch2    , [rpc, #1]
 764                 LDRB                    rscratch   , [rpc], #2
 765                 ORR                     rscratch    , rscratch, rscratch2, LSL #8
 766                 S9xGetWordLowRegNS      rscratch2
 767                 ADD                     rscratch   , rscratch,  #2
 768                 STMFD                   r13!,{rscratch2}
 769                 S9xGetByteLow
 770                 LDMFD                   r13!,{rscratch2}
 771                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 772 .endm
 773 .macro          AbsoluteIndirect
 774                 ADD2MEM
 775                 LDRB    rscratch2    , [rpc,#1]
 776                 LDRB    rscratch   , [rpc], #2
 777                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 778                 S9xGetWordLow
 779                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 780 .endm
 781 .macro          AbsoluteIndexedX0
 782                 ADD2MEM
 783                 LDRB    rscratch2    , [rpc, #1]
 784                 LDRB    rscratch   , [rpc], #2
 785                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 786                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 787                 ADD     rscratch    , rscratch, reg_x, LSR #16
 788 .endm
 789 .macro          AbsoluteIndexedX1
 790                 ADD2MEM
 791                 LDRB    rscratch2    , [rpc, #1]
 792                 LDRB    rscratch   , [rpc], #2
 793                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 794                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 795                 ADD     rscratch    , rscratch, reg_x, LSR #24
 796 .endm
 797
 798
 799 .macro          AbsoluteIndexedY0
 800                 ADD2MEM
 801                 LDRB    rscratch2    , [rpc, #1]
 802                 LDRB    rscratch   , [rpc], #2
 803                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 804                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 805                 ADD     rscratch    , rscratch, reg_y, LSR #16
 806 .endm
 807 .macro          AbsoluteIndexedY1
 808                 ADD2MEM
 809                 LDRB    rscratch2    , [rpc, #1]
 810                 LDRB    rscratch   , [rpc], #2
 811                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 812                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 813                 ADD     rscratch    , rscratch, reg_y, LSR #24
 814 .endm
 815 .macro          AbsoluteLong
 816                 ADD3MEM
 817                 LDRB    rscratch2    , [rpc, #1]
 818                 LDRB    rscratch   , [rpc], #2
 819                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 820                 LDRB    rscratch2   , [rpc], #1
 821                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 822 .endm
 823
 824
 825 .macro          AbsoluteLongIndexedX0
 826                 ADD3MEM
 827                 LDRB    rscratch2    , [rpc, #1]
 828                 LDRB    rscratch   , [rpc], #2
 829                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 830                 LDRB    rscratch2   , [rpc], #1
 831                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 832                 ADD     rscratch    , rscratch, reg_x, LSR #16
 833                 BIC     rscratch, rscratch, #0xFF000000
 834 .endm
 835 .macro          AbsoluteLongIndexedX1
 836                 ADD3MEM
 837                 LDRB    rscratch2    , [rpc, #1]
 838                 LDRB    rscratch   , [rpc], #2
 839                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 840                 LDRB    rscratch2   , [rpc], #1
 841                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 842                 ADD     rscratch    , rscratch, reg_x, LSR #24
 843                 BIC     rscratch, rscratch, #0xFF000000
 844 .endm
 845 .macro          Direct
 846                 ADD1MEM
 847                 LDRB    rscratch    , [rpc], #1
 848                 ADD     rscratch    , reg_d, rscratch, LSL #16
 849                 MOV     rscratch, rscratch, LSR #16
 850 .endm
 851 .macro          DirectIndirect
 852                 ADD1MEM
 853                 LDRB    rscratch    , [rpc], #1
 854                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 855                 MOV     rscratch, rscratch, LSR #16
 856                 S9xGetWordLow
 857                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 858 .endm
 859 .macro          DirectIndirectLong
 860                 ADD1MEM
 861                 LDRB                    rscratch    , [rpc], #1
 862                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 863                 MOV                     rscratch, rscratch, LSR #16
 864                 S9xGetWordLowRegNS      rscratch2
 865                 ADD                     rscratch    , rscratch,#2
 866                 STMFD                   r13!,{rscratch2}
 867                 S9xGetByteLow
 868                 LDMFD                   r13!,{rscratch2}
 869                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 870 .endm
 871 .macro          DirectIndirectIndexed0
 872                 ADD1MEM
 873                 LDRB    rscratch    , [rpc], #1
 874                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 875                 MOV     rscratch, rscratch, LSR #16
 876                 S9xGetWordLow
 877                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 878                 ADD     rscratch, rscratch,reg_y, LSR #16
 879 .endm
 880 .macro          DirectIndirectIndexed1
 881                 ADD1MEM
 882                 LDRB    rscratch    , [rpc], #1
 883                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 884                 MOV     rscratch, rscratch, LSR #16
 885                 S9xGetWordLow
 886                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 887                 ADD     rscratch, rscratch,reg_y, LSR #24
 888 .endm
 889 .macro          DirectIndirectIndexedLong0
 890                 ADD1MEM
 891                 LDRB                    rscratch    , [rpc], #1
 892                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 893                 MOV                     rscratch, rscratch, LSR #16
 894                 S9xGetWordLowRegNS      rscratch2
 895                 ADD                     rscratch    , rscratch,#2
 896                 STMFD                   r13!,{rscratch2}
 897                 S9xGetByteLow
 898                 LDMFD                   r13!,{rscratch2}
 899                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 900                 ADD                     rscratch, rscratch,reg_y, LSR #16
 901 .endm
 902 .macro          DirectIndirectIndexedLong1
 903                 ADD1MEM
 904                 LDRB                    rscratch    , [rpc], #1
 905                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 906                 MOV                     rscratch, rscratch, LSR #16
 907                 S9xGetWordLowRegNS      rscratch2
 908                 ADD                     rscratch    , rscratch,#2
 909                 STMFD                   r13!,{rscratch2}
 910                 S9xGetByteLow
 911                 LDMFD                   r13!,{rscratch2}
 912                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 913                 ADD                     rscratch, rscratch,reg_y, LSR #24
 914 .endm
 915 .macro          DirectIndexedIndirect0
 916                 ADD1CYCLE1MEM
 917                 LDRB    rscratch    , [rpc], #1
 918                 ADD     rscratch2   , reg_d , reg_x
 919                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 920                 MOV     rscratch, rscratch, LSR #16
 921                 S9xGetWordLow
 922                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 923 .endm
 924 .macro          DirectIndexedIndirect1
 925                 ADD1CYCLE1MEM
 926                 LDRB    rscratch    , [rpc], #1
 927                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 928                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 929                 MOV     rscratch, rscratch, LSR #16
 930                 S9xGetWordLow
 931                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 932 .endm
 933 .macro          DirectIndexedX0
 934                 ADD1CYCLE1MEM
 935                 LDRB    rscratch    , [rpc], #1
 936                 ADD     rscratch2   , reg_d , reg_x
 937                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 938                 MOV     rscratch, rscratch, LSR #16
 939 .endm
 940 .macro          DirectIndexedX1
 941                 ADD1CYCLE1MEM
 942                 LDRB    rscratch    , [rpc], #1
 943                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 944                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 945                 MOV     rscratch, rscratch, LSR #16
 946 .endm
 947 .macro          DirectIndexedY0
 948                 ADD1CYCLE1MEM
 949                 LDRB    rscratch    , [rpc], #1
 950                 ADD     rscratch2   , reg_d , reg_y
 951                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 952                 MOV     rscratch, rscratch, LSR #16
 953 .endm
 954 .macro          DirectIndexedY1
 955                 ADD1CYCLE1MEM
 956                 LDRB    rscratch    , [rpc], #1
 957                 ADD     rscratch2   , reg_d , reg_y, LSR #8
 958                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 959                 MOV     rscratch, rscratch, LSR #16
 960 .endm
 961 .macro          Immediate8
 962                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 963                 SUB     rscratch, rscratch, regpcbase
 964                 ADD     rpc, rpc, #1
 965 .endm
 966 .macro          Immediate16
 967                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 968                 SUB     rscratch, rscratch, regpcbase
 969                 ADD     rpc, rpc, #2
 970 .endm
 971 .macro          asmRelative
 972                 ADD1MEM
 973                 LDRSB   rscratch    , [rpc],#1
 974                 ADD     rscratch , rscratch , rpc
 975                 SUB     rscratch , rscratch, regpcbase
 976                 UXTH rscratch,rscratch
 977 .endm
 978 .macro          asmRelativeLong
 979                 ADD1CYCLE2MEM
 980                 LDRB    rscratch2    , [rpc, #1]
 981                 LDRB    rscratch   , [rpc], #2
 982                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 983                 SUB     rscratch2    , rpc, regpcbase
 984                 ADD     rscratch    , rscratch2, rscratch
 985                 BIC     rscratch,rscratch,#0x00FF0000
 986 .endm
 987
 988
 989 .macro          StackasmRelative
 990                 ADD1CYCLE1MEM
 991                 LDRB    rscratch    , [rpc], #1
 992                 ADD     rscratch    , rscratch, reg_s
 993                 BIC     rscratch,rscratch,#0x00FF0000
 994 .endm
 995 .macro          StackasmRelativeIndirectIndexed0
 996                 ADD2CYCLE1MEM
 997                 LDRB    rscratch    , [rpc], #1
 998                 ADD     rscratch    , rscratch, reg_s
 999                 BIC     rscratch,rscratch,#0x00FF0000
1000                 S9xGetWordLow
1001                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1002                 ADD     rscratch    , rscratch, reg_y, LSR #16
1003                 BIC     rscratch, rscratch, #0xFF000000
1004 .endm
1005 .macro          StackasmRelativeIndirectIndexed1
1006                 ADD2CYCLE1MEM
1007                 LDRB    rscratch    , [rpc], #1
1008                 ADD     rscratch    , rscratch, reg_s
1009                 BIC     rscratch,rscratch,#0x00FF0000
1010                 S9xGetWordLow
1011                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1012                 ADD     rscratch    , rscratch, reg_y, LSR #24
1013                 BIC     rscratch, rscratch, #0xFF000000
1014 .endm
1015
1016
1017 /****************************************/
1018 .macro          PushB           reg
1019                 MOV             rscratch,reg_s
1020                 S9xSetByte      \reg
1021                 SUB             reg_s,reg_s,#1
1022 .endm
1023 .macro          PushBLow        reg
1024                 MOV             rscratch,reg_s
1025                 S9xSetByteLow   \reg
1026                 SUB             reg_s,reg_s,#1
1027 .endm
1028 .macro          PushWLow        reg
1029                 SUB             rscratch,reg_s,#1
1030                 S9xSetWordLow   \reg
1031                 SUB             reg_s,reg_s,#2
1032 .endm
1033 .macro          PushWrLow
1034                 MOV             rscratch2,rscratch
1035                 SUB             rscratch,reg_s,#1
1036                 S9xSetWordLow   rscratch2
1037                 SUB             reg_s,reg_s,#2
1038 .endm
1039 .macro          PushW           reg
1040                 SUB             rscratch,reg_s,#1
1041                 S9xSetWord      \reg
1042                 SUB             reg_s,reg_s,#2
1043 .endm
1044
1045 /********/
1046
1047 .macro          PullB           reg
1048                 ADD             rscratch,reg_s,#1
1049                 S9xGetByteLow
1050                 ADD             reg_s,reg_s,#1
1051                 MOV             \reg,rscratch,LSL #24
1052 .endm
1053 .macro          PullBr
1054                 ADD             rscratch,reg_s,#1
1055                 S9xGetByte
1056                 ADD             reg_s,reg_s,#1
1057 .endm
1058 .macro          PullBLow        reg
1059                 ADD             rscratch,reg_s,#1
1060                 S9xGetByteLow
1061                 ADD             reg_s,reg_s,#1
1062                 MOV             \reg,rscratch
1063 .endm
1064 .macro          PullBrLow
1065                 ADD             rscratch,reg_s,#1
1066                 S9xGetByteLow
1067                 ADD             reg_s,reg_s,#1
1068 .endm
1069 .macro          PullW           reg
1070                 ADD             rscratch,reg_s,#1
1071                 S9xGetWordLow
1072                 ADD             reg_s,reg_s,#2
1073                 MOV             \reg,rscratch,LSL #16
1074 .endm
1075
1076 .macro          PullWLow        reg
1077                 ADD             rscratch,reg_s,#1
1078                 S9xGetWordLow
1079                 ADD             reg_s,reg_s,#2
1080                 MOV             \reg,rscratch
1081 .endm
1082
1083
1084 /*****************/
1085 .macro          PullBS          reg
1086                 ADD             rscratch,reg_s,#1
1087                 S9xGetByteLow
1088                 ADD             reg_s,reg_s,#1
1089                 MOVS            \reg,rscratch,LSL #24
1090 .endm
1091 .macro          PullBrS
1092                 ADD             rscratch,reg_s,#1
1093                 S9xGetByteLow
1094                 ADD             reg_s,reg_s,#1
1095                 MOVS            rscratch,rscratch,LSL #24
1096 .endm
1097 .macro          PullBLowS       reg
1098                 ADD             rscratch,reg_s,#1
1099                 S9xGetByteLow
1100                 ADD             reg_s,reg_s,#1
1101                 MOVS            \reg,rscratch
1102 .endm
1103 .macro          PullBrLowS
1104                 ADD             rscratch,reg_s,#1
1105                 S9xGetByteLow
1106                 ADD             reg_s,reg_s,#1
1107                 MOVS            rscratch,rscratch
1108 .endm
1109 .macro          PullWS          reg
1110                 ADD             rscratch,reg_s,#1
1111                 S9xGetWordLow
1112                 ADD             reg_s,reg_s,#2
1113                 MOVS            \reg,rscratch, LSL #16
1114 .endm
1115 .macro          PullWrS
1116                 ADD             rscratch,reg_s,#1
1117                 S9xGetWordLow
1118                 ADD             reg_s,reg_s,#2
1119                 MOVS            rscratch,rscratch, LSL #16
1120 .endm
1121 .macro          PullWLowS       reg
1122                 ADD             rscratch,reg_s,#1
1123                 S9xGetWordLow
1124                 ADD             reg_s,reg_s,#2
1125                 MOVS            \reg,rscratch
1126 .endm
1127 .macro          PullWrLowS
1128                 ADD             rscratch,reg_s,#1
1129                 S9xGetWordLow
1130                 ADD             reg_s,reg_s,#2
1131                 MOVS            rscratch,rscratch
1132 .endm
1133
1134 @ START OF PROGRAM CODE
1135
1136 .text
1137
1138 .align 4
1139
1140 .globl asmS9xGetByte
1141 .globl asmS9xGetWord
1142 .globl asmS9xSetByte
1143 .globl asmS9xSetWord
1144
1145 @ uint8 aaS9xGetByte(uint32 address);
1146 asmS9xGetByte:
1147         @  in : R0  = 0x00hhmmll
1148         @  out : R0 = 0x000000ll
1149         @  DESTROYED : R1,R2,R3
1150         @  UPDATE : reg_cycles
1151         @ R1 <= block
1152         MOV             R1,R0,LSR #MEMMAP_SHIFT
1153         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1154         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1155         @ so AND MEMMAP_MASK is BIC 0xFF000
1156         BIC             R1,R1,#0xFF000
1157         @ R2 <= Map[block] (GetAddress)
1158         LDR             R2,[reg_cpu_var,#Map_ofs]
1159         LDR             R2,[R2,R1,LSL #2]
1160         CMP             R2,#MAP_LAST
1161         BLO             GBSpecial  @ special
1162         @  Direct ROM/RAM acess
1163         @ R2 <= GetAddress + Address & 0xFFFF
1164         @ R3 <= MemorySpeed[block]
1165         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1166         MOV             R0,R0,LSL #16
1167         LDRB            R3,[R3,R1]
1168         ADD             R2,R2,R0,LSR #16
1169         @ Update CPU.Cycles
1170         ADD             reg_cycles,reg_cycles,R3
1171         @ R3 = BlockIsRAM[block]
1172         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1173         @ Get value to return
1174         LDRB            R0,[R2]
1175         LDRB            R3,[R3,R1]
1176         MOVS            R3,R3
1177         @  if BlockIsRAM => update for CPUShutdown
1178         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1179         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1180
1181         LDMFD           R13!,{PC} @ Return
1182 GBSpecial:
1183
1184         LDR             PC,[PC,R2,LSL #2]
1185         MOV             R0,R0           @ nop, for align
1186         .long GBPPU
1187         .long GBCPU
1188         .long GBDSP
1189         .long GBLSRAM
1190         .long GBHSRAM
1191         .long GBNONE
1192         .long GBDEBUG
1193         .long GBC4
1194         .long GBBWRAM
1195         .long GBNONE
1196         .long GBNONE
1197         .long GBNONE
1198         /*.long GB7ROM
1199         .long GB7RAM
1200         .long GB7SRM*/
1201 GBPPU:
1202         @ InDMA ?
1203         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1204         MOVS            R1,R1
1205         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1206         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1207         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1208         MOV             R0,R0,LSR #16
1209                 PREPARE_C_CALL
1210         BL              S9xGetPPU
1211                 RESTORE_C_CALL
1212         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1213         LDMFD           R13!,{PC} @ Return
1214 GBCPU:
1215         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1216         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1217         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1218         MOV             R0,R0,LSR #16
1219                 PREPARE_C_CALL
1220         BL              S9xGetCPU
1221                 RESTORE_C_CALL
1222         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1223         LDMFD           R13!,{PC} @ Return
1224 GBDSP:
1225         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1226         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1227         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1228         MOV             R0,R0,LSR #16
1229                 PREPARE_C_CALL
1230         BL              S9xGetDSP
1231                 RESTORE_C_CALL
1232         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1233         LDMFD           R13!,{PC} @ Return
1234 GBLSRAM:
1235         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1236         LDRH            R2,[reg_cpu_var,#SRAMMask]
1237         LDR             R1,[reg_cpu_var,#SRAM]
1238         AND             R0,R2,R0                @ Address&SRAMMask
1239         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1240         LDMFD           R13!,{PC}
1241 GB7SRM:
1242 GBHSRAM:
1243         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1244
1245         MOV             R1,R0,LSL #17
1246         AND             R2,R0,#0xF0000
1247         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1248         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1249         ADD             R0,R2,R1
1250         LDRH            R2,[reg_cpu_var,#SRAMMask]
1251         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1252         LDR             R1,[reg_cpu_var,#SRAM]
1253         AND             R0,R2,R0                @ Address&SRAMMask
1254         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1255         LDMFD           R13!,{PC}               @ return
1256 GB7ROM:
1257 GB7RAM:
1258 GBNONE:
1259         MOV             R0,R0,LSR #8
1260         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1261         AND             R0,R0,#0xFF
1262         LDMFD           R13!,{PC}
1263 @ GBDEBUG:
1264         /*ADD           reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1265         MOV             R0,#0
1266         LDMFD           R13!,{PC}*/
1267 GBC4:
1268         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1269         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1270         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1271         MOV             R0,R0,LSR #16
1272                 PREPARE_C_CALL
1273         BL              S9xGetC4
1274                 RESTORE_C_CALL
1275         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1276         LDMFD           R13!,{PC} @ Return
1277 GBDEBUG:
1278 GBBWRAM:
1279         MOV             R0,R0,LSL #17
1280         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1281         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1282         LDR             R1,[reg_cpu_var,#BWRAM]
1283         SUB             R0,R0,#0x6000   @ ((Address & 0x7fff) - 0x6000)
1284         LDRB            R0,[R0,R1]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1285         LDMFD           R13!,{PC}
1286
1287
1288 @ uint16 aaS9xGetWord(uint32 address);
1289 asmS9xGetWord:
1290         @  in : R0  = 0x00hhmmll
1291         @  out : R0 = 0x000000ll
1292         @  DESTROYED : R1,R2,R3
1293         @  UPDATE : reg_cycles
1294
1295
1296         MOV             R1,R0,LSL #19
1297         ADDS            R1,R1,#0x80000
1298         @ if = 0x1FFF => 0
1299         BNE             GW_NotBoundary
1300
1301         STMFD           R13!,{R0}
1302                 STMFD           R13!,{PC}
1303         B               asmS9xGetByte
1304                 MOV             R0,R0
1305         LDMFD           R13!,{R1}
1306         STMFD           R13!,{R0}
1307         ADD             R0,R1,#1
1308                 STMFD           R13!,{PC}
1309         B               asmS9xGetByte
1310                 MOV             R0,R0
1311         LDMFD           R13!,{R1}
1312         ORR             R0,R1,R0,LSL #8
1313         LDMFD           R13!,{PC}
1314
1315 GW_NotBoundary:
1316
1317         @ R1 <= block
1318         MOV             R1,R0,LSR #MEMMAP_SHIFT
1319         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1320         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1321         @ so AND MEMMAP_MASK is BIC 0xFF000
1322         BIC             R1,R1,#0xFF000
1323         @ R2 <= Map[block] (GetAddress)
1324         LDR             R2,[reg_cpu_var,#Map_ofs]
1325         LDR             R2,[R2,R1,LSL #2]
1326         CMP             R2,#MAP_LAST
1327         BLO             GWSpecial  @ special
1328         @  Direct ROM/RAM acess
1329
1330         TST             R0,#1
1331         BNE             GW_Not_Aligned1
1332         @ R2 <= GetAddress + Address & 0xFFFF
1333         @ R3 <= MemorySpeed[block]
1334         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1335         MOV             R0,R0,LSL #16
1336         LDRB            R3,[R3,R1]
1337         MOV             R0,R0,LSR #16
1338         @ Update CPU.Cycles
1339         ADD             reg_cycles,reg_cycles,R3, LSL #1
1340         @ R3 = BlockIsRAM[block]
1341         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1342         @ Get value to return
1343         LDRH            R0,[R2,R0]
1344         LDRB            R3,[R3,R1]
1345         MOVS            R3,R3
1346         @  if BlockIsRAM => update for CPUShutdown
1347         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1348         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1349
1350         LDMFD           R13!,{PC} @ Return
1351 GW_Not_Aligned1:
1352
1353         MOV             R0,R0,LSL #16
1354         ADD             R3,R0,#0x10000
1355         LDRB            R3,[R2,R3,LSR #16]      @ GetAddress+ (Address+1)&0xFFFF
1356         LDRB            R0,[R2,R0,LSR #16]      @ GetAddress+ Address&0xFFFF
1357         ORR             R0,R0,R3,LSL #8
1358
1359         @  if BlockIsRAM => update for CPUShutdown
1360         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1361         LDR             R2,[reg_cpu_var,#MemorySpeed_ofs]
1362         LDRB            R3,[R3,R1]   @ R3 = BlockIsRAM[block]
1363         LDRB            R2,[R2,R1]   @ R2 <= MemorySpeed[block]
1364         MOVS            R3,R3       @ IsRAM ? CPUShutdown stuff
1365         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1366         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1367         ADD             reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles
1368         LDMFD           R13!,{PC}  @ Return
1369 GWSpecial:
1370         LDR             PC,[PC,R2,LSL #2]
1371         MOV             R0,R0           @ nop, for align
1372         .long GWPPU
1373         .long GWCPU
1374         .long GWDSP
1375         .long GWLSRAM
1376         .long GWHSRAM
1377         .long GWNONE
1378         .long GWDEBUG
1379         .long GWC4
1380         .long GWBWRAM
1381         .long GWNONE
1382         .long GWNONE
1383         .long GWNONE
1384         /*.long GW7ROM
1385         .long GW7RAM
1386         .long GW7SRM*/
1387 /*      MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
1388         MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
1389         MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
1390
1391 GWPPU:
1392         @ InDMA ?
1393         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1394         MOVS            R1,R1
1395         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1396         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1397         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1398         MOV             R0,R0,LSR #16
1399                 PREPARE_C_CALL_R0
1400         BL              S9xGetPPU
1401         LDMFD           R13!,{R1}
1402         STMFD           R13!,{R0}
1403         ADD             R0,R1,#1
1404         @ BIC           R0,R0,#0x10000
1405         BL              S9xGetPPU
1406                 RESTORE_C_CALL_R1
1407         ORR             R0,R1,R0,LSL #8
1408         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1409         LDMFD           R13!,{PC} @ Return
1410 GWCPU:
1411         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1412         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1413         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1414         MOV             R0,R0,LSR #16
1415                 PREPARE_C_CALL_R0
1416         BL              S9xGetCPU
1417         LDMFD           R13!,{R1}
1418         STMFD           R13!,{R0}
1419         ADD             R0,R1,#1
1420         @ BIC           R0,R0,#0x10000
1421         BL              S9xGetCPU
1422                 RESTORE_C_CALL_R1
1423         ORR             R0,R1,R0,LSL #8
1424         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1425         LDMFD           R13!,{PC} @ Return
1426 GWDSP:
1427         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1428         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1429         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1430         MOV             R0,R0,LSR #16
1431                 PREPARE_C_CALL_R0
1432         BL              S9xGetDSP
1433         LDMFD           R13!,{R1}
1434         STMFD           R13!,{R0}
1435         ADD             R0,R1,#1
1436         @ BIC           R0,R0,#0x10000
1437         BL              S9xGetDSP
1438                 RESTORE_C_CALL_R1
1439         ORR             R0,R1,R0,LSL #8
1440         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1441         LDMFD           R13!,{PC} @ Return
1442 GWLSRAM:
1443         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1444
1445         TST             R0,#1
1446         BNE             GW_Not_Aligned2
1447         LDRH            R2,[reg_cpu_var,#SRAMMask]
1448         LDR             R1,[reg_cpu_var,#SRAM]
1449         AND             R3,R2,R0                @ Address&SRAMMask
1450         LDRH            R0,[R3,R1]              @ *Memory.SRAM + Address&SRAMMask
1451         LDMFD           R13!,{PC}       @ return
1452 GW_Not_Aligned2:
1453         LDRH            R2,[reg_cpu_var,#SRAMMask]
1454         LDR             R1,[reg_cpu_var,#SRAM]
1455         AND             R3,R2,R0                @ Address&SRAMMask
1456         ADD             R0,R0,#1
1457         AND             R2,R0,R2                @ Address&SRAMMask
1458         LDRB            R3,[R1,R3]              @ *Memory.SRAM + Address&SRAMMask
1459         LDRB            R2,[R1,R2]              @ *Memory.SRAM + Address&SRAMMask
1460         ORR             R0,R3,R2,LSL #8
1461         LDMFD           R13!,{PC}       @ return
1462 GW7SRM:
1463 GWHSRAM:
1464         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1465
1466         TST             R0,#1
1467         BNE             GW_Not_Aligned3
1468
1469         MOV             R1,R0,LSL #17
1470         AND             R2,R0,#0xF0000
1471         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1472         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1473         ADD             R0,R2,R1
1474         LDRH            R2,[reg_cpu_var,#SRAMMask]
1475         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1476         LDR             R1,[reg_cpu_var,#SRAM]
1477         AND             R0,R2,R0                @ Address&SRAMMask
1478         LDRH            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1479         LDMFD           R13!,{PC}               @ return
1480
1481 GW_Not_Aligned3:
1482         MOV             R3,R0,LSL #17
1483         AND             R2,R0,#0xF0000
1484         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1485         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1486         ADD             R2,R2,R3
1487         ADD             R0,R0,#1
1488         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1489         MOV             R3,R0,LSL #17
1490         AND             R0,R0,#0xF0000
1491         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1492         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1493         ADD             R0,R0,R3
1494         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1495         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1496         AND             R2,R3,R2                @ Address...&SRAMMask
1497         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1498
1499         LDR             R3,[reg_cpu_var,#SRAM]
1500         LDRB            R0,[R0,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1501         LDRB            R2,[R2,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1502         ORR             R0,R2,R0,LSL #8
1503
1504         LDMFD           R13!,{PC}               @ return
1505 GW7ROM:
1506 GW7RAM:
1507 GWNONE:
1508         MOV             R0,R0,LSL #16
1509         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1510         MOV             R0,R0,LSR #24
1511         ORR             R0,R0,R0,LSL #8
1512         LDMFD           R13!,{PC}
1513 GWDEBUG:
1514         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1515         MOV             R0,#0
1516         LDMFD           R13!,{PC}
1517 GWC4:
1518         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1519         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1520         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1521         MOV             R0,R0,LSR #16
1522                 PREPARE_C_CALL_R0
1523         BL              S9xGetC4
1524         LDMFD           R13!,{R1}
1525         STMFD           R13!,{R0}
1526         ADD             R0,R1,#1
1527         @ BIC           R0,R0,#0x10000
1528         BL              S9xGetC4
1529                 RESTORE_C_CALL_R1
1530         ORR             R0,R1,R0,LSL #8
1531         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1532         LDMFD           R13!,{PC} @ Return
1533 GWBWRAM:
1534         TST             R0,#1
1535         BNE             GW_Not_Aligned4
1536         MOV             R0,R0,LSL #17
1537         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1538         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1539         LDR             R1,[reg_cpu_var,#BWRAM]
1540         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1541         LDRH            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1542         LDMFD           R13!,{PC}               @ return
1543 GW_Not_Aligned4:
1544         MOV             R0,R0,LSL #17
1545         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1546         ADD             R3,R0,#0x20000
1547         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1548         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1549         LDR             R1,[reg_cpu_var,#BWRAM]
1550         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1551         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
1552         LDRB            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1553         LDRB            R3,[R1,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1554         ORR             R0,R0,R3,LSL #8
1555         LDMFD           R13!,{PC}               @ return
1556
1557
1558
1559
1560 @ void aaS9xSetByte(uint32 address,uint8 val);
1561 asmS9xSetByte:
1562         @  in : R0=0x00hhmmll  R1=0x000000ll
1563         @  DESTROYED : R0,R1,R2,R3
1564         @  UPDATE : reg_cycles
1565         @ cpu shutdown
1566         MOV             R2,#0
1567         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1568         @
1569
1570         @ R3 <= block
1571         MOV             R3,R0,LSR #MEMMAP_SHIFT
1572         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1573         @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1574         @ so AND MEMMAP_MASK is BIC 0xFF000
1575         BIC             R3,R3,#0xFF000
1576         @ R2 <= Map[block] (SetAddress)
1577         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1578         LDR             R2,[R2,R3,LSL #2]
1579         CMP             R2,#MAP_LAST
1580         BLO             SBSpecial  @ special
1581         @  Direct ROM/RAM acess
1582
1583         @ R2 <= SetAddress + Address & 0xFFFF
1584         MOV             R0,R0,LSL #16
1585         ADD             R2,R2,R0,LSR #16
1586         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1587         @ Set byte
1588         STRB            R1,[R2]
1589         @ R0 <= MemorySpeed[block]
1590         LDRB            R0,[R0,R3]
1591         @ Update CPU.Cycles
1592         ADD             reg_cycles,reg_cycles,R0
1593         @ CPUShutdown
1594         @ only SA1 here : TODO
1595         @ Return
1596         LDMFD           R13!,{PC}
1597 SBSpecial:
1598         LDR             PC,[PC,R2,LSL #2]
1599         MOV             R0,R0           @ nop, for align
1600         .long SBPPU
1601         .long SBCPU
1602         .long SBDSP
1603         .long SBLSRAM
1604         .long SBHSRAM
1605         .long SBNONE
1606         .long SBDEBUG
1607         .long SBC4
1608         .long SBBWRAM
1609         .long SBNONE
1610         .long SBNONE
1611         .long SBNONE
1612         /*.long SB7ROM
1613         .long SB7RAM
1614         .long SB7SRM*/
1615 SBPPU:
1616         @ InDMA ?
1617         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1618         MOVS            R2,R2
1619         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1620         MOV             R0,R0,LSL #16
1621         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1622         MOV             R0,R0,LSR #16
1623                 PREPARE_C_CALL
1624         MOV             R12,R0
1625         UXTB    R0,R1
1626         MOV             R1,R12
1627         BL              S9xSetPPU
1628                 RESTORE_C_CALL
1629         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1630         LDMFD           R13!,{PC} @ Return
1631 SBCPU:
1632         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1633         MOV             R0,R0,LSL #16
1634         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1635         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1636                 PREPARE_C_CALL
1637         MOV             R12,R0
1638         UXTB    R0,R1
1639         MOV             R1,R12
1640         BL              S9xSetCPU
1641                 RESTORE_C_CALL
1642         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1643         LDMFD           R13!,{PC} @ Return
1644 SBDSP:
1645         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1646         MOV             R0,R0,LSL #16
1647         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1648         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1649                 PREPARE_C_CALL
1650         MOV             R12,R0
1651         UXTB    R0,R1
1652         MOV             R1,R12
1653         BL              S9xSetDSP
1654                 RESTORE_C_CALL
1655         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1656         LDMFD           R13!,{PC} @ Return
1657 SBLSRAM:
1658         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1659         LDRH            R2,[reg_cpu_var,#SRAMMask]
1660         MOVS            R2,R2
1661         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1662         LDR             R3,[reg_cpu_var,#SRAM]
1663         AND             R0,R2,R0                @ Address&SRAMMask
1664         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1665
1666         MOV             R0,#1
1667         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1668         LDMFD           R13!,{PC}  @ return
1669 SB7SRM:
1670 SBHSRAM:
1671         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1672
1673         MOV             R3,R0,LSL #17
1674         AND             R2,R0,#0xF0000
1675         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1676         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1677         ADD             R0,R2,R3
1678
1679         LDRH            R2,[reg_cpu_var,#SRAMMask]
1680         MOVS            R2,R2
1681         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1682
1683         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1684         LDR             R3,[reg_cpu_var,#SRAM]
1685         AND             R0,R2,R0                @ Address&SRAMMask
1686         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1687
1688         MOV             R0,#1
1689         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1690         LDMFD           R13!,{PC}       @ return
1691 SB7ROM:
1692 SB7RAM:
1693 SBNONE:
1694 SBDEBUG:
1695         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1696         LDMFD           R13!,{PC}
1697 SBC4:
1698         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1699         MOV             R0,R0,LSL #16
1700         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1701         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1702                 PREPARE_C_CALL
1703         MOV             R12,R0
1704         UXTB    R0,R1
1705         MOV             R1,R12
1706         BL              S9xSetC4
1707                 RESTORE_C_CALL
1708         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1709         LDMFD           R13!,{PC} @ Return
1710 SBBWRAM:
1711         MOV             R0,R0,LSL #17
1712         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1713         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1714         LDR             R2,[reg_cpu_var,#BWRAM]
1715         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1716         STRB            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1717
1718         MOV             R0,#1
1719         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1720
1721         LDMFD           R13!,{PC}
1722
1723
1724
1725 @ void aaS9xSetWord(uint32 address,uint16 val);
1726 asmS9xSetWord:
1727         @  in : R0  = 0x00hhmmll R1=0x0000hhll
1728         @  DESTROYED : R0,R1,R2,R3
1729         @  UPDATE : reg_cycles
1730         @ R1 <= block
1731
1732         MOV             R2,R0,LSL #19
1733         ADDS            R2,R2,#0x80000
1734         @ if = 0x1FFF => 0
1735         BNE             SW_NotBoundary
1736
1737         STMFD           R13!,{R0,R1}
1738                 STMFD           R13!,{PC}
1739         B               asmS9xSetByte
1740                 MOV             R0,R0
1741         LDMFD           R13!,{R0,R1}
1742         ADD             R0,R0,#1
1743         MOV             R1,R1,LSR #8
1744                 STMFD           R13!,{PC}
1745         B               asmS9xSetByte
1746                 MOV             R0,R0
1747
1748         LDMFD           R13!,{PC}
1749
1750 SW_NotBoundary:
1751
1752         MOV             R2,#0
1753         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1754         @
1755         @ R3 <= block
1756         MOV             R3,R0,LSR #MEMMAP_SHIFT
1757         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1758         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1759         @ so AND MEMMAP_MASK is BIC 0xFF000
1760         BIC             R3,R3,#0xFF000
1761         @ R2 <= Map[block] (SetAddress)
1762         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1763         LDR             R2,[R2,R3,LSL #2]
1764         CMP             R2,#MAP_LAST
1765         BLO             SWSpecial  @ special
1766         @  Direct ROM/RAM acess
1767
1768
1769         @ check if address is 16bits aligned or not
1770         TST             R0,#1
1771         BNE             SW_not_aligned1
1772         @ aligned
1773         MOV             R0,R0,LSL #16
1774         ADD             R2,R2,R0,LSR #16        @ address & 0xFFFF + SetAddress
1775         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1776         @ Set word
1777         STRH            R1,[R2]
1778         @ R1 <= MemorySpeed[block]
1779         LDRB            R0,[R0,R3]
1780         @ Update CPU.Cycles
1781         ADD             reg_cycles,reg_cycles,R0, LSL #1
1782         @ CPUShutdown
1783         @ only SA1 here : TODO
1784         @ Return
1785         LDMFD           R13!,{PC}
1786
1787 SW_not_aligned1:
1788         @ R1 = (Address&0xFFFF)<<16
1789         MOV             R0,R0,LSL #16
1790         @ First write @address
1791         STRB            R1,[R2,R0,LSR #16]
1792         ADD             R0,R0,#0x10000
1793         MOV             R1,R1,LSR #8
1794         @ Second write @address+1
1795         STRB            R1,[R2,R0,LSR #16]
1796         @ R1 <= MemorySpeed[block]
1797         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1798         LDRB            R0,[R0,R3]
1799         @ Update CPU.Cycles
1800         ADD             reg_cycles,reg_cycles,R0,LSL #1
1801         @ CPUShutdown
1802         @ only SA1 here : TODO
1803         @ Return
1804         LDMFD           R13!,{PC}
1805 SWSpecial:
1806         LDR             PC,[PC,R2,LSL #2]
1807         MOV             R0,R0           @ nop, for align
1808         .long SWPPU
1809         .long SWCPU
1810         .long SWDSP
1811         .long SWLSRAM
1812         .long SWHSRAM
1813         .long SWNONE
1814         .long SWDEBUG
1815         .long SWC4
1816         .long SWBWRAM
1817         .long SWNONE
1818         .long SWNONE
1819         .long SWNONE
1820         /*.long SW7ROM
1821         .long SW7RAM
1822         .long SW7SRM*/
1823 SWPPU:
1824         @ InDMA ?
1825         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1826         MOVS            R2,R2
1827         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1828         MOV             R0,R0,LSL #16
1829         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1830         MOV             R0,R0,LSR #16
1831         MOV             R2,R1
1832         MOV             R1,R0
1833         MOV             R0,R2
1834                 PREPARE_C_CALL_R0R1
1835         UXTB    R0,R0
1836         BL              S9xSetPPU
1837         LDMFD           R13!,{R0,R1}
1838         ADD             R1,R1,#1
1839         UXTB    R0,R0,ROR #8
1840         BIC             R1,R1,#0x10000
1841         BL              S9xSetPPU
1842                 RESTORE_C_CALL
1843         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1844         LDMFD           R13!,{PC} @ Return
1845 SWCPU:
1846         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1847         MOV             R0,R0,LSL #16
1848         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1849         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1850         MOV             R2,R1
1851         MOV             R1,R0
1852         MOV             R0,R2
1853                 PREPARE_C_CALL_R0R1
1854         UXTB    R0,R0
1855         BL              S9xSetCPU
1856         LDMFD           R13!,{R0,R1}
1857         ADD             R1,R1,#1
1858         UXTB    R0,R0,ROR #8    @ ((R0 >> 8) & 0xFF)
1859         BIC             R1,R1,#0x10000
1860         BL              S9xSetCPU
1861                 RESTORE_C_CALL
1862         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1863         LDMFD           R13!,{PC} @ Return
1864 SWDSP:
1865         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1866         MOV             R0,R0,LSL #16
1867         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1868         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1869         MOV             R2,R1
1870         MOV             R1,R0
1871         MOV             R0,R2
1872                 PREPARE_C_CALL_R0R1
1873         UXTB    R0,R0
1874         BL              S9xSetDSP
1875         LDMFD           R13!,{R0,R1}
1876         ADD             R1,R1,#1
1877         UXTB    R0,R0,ROR #8
1878         BIC             R1,R1,#0x10000
1879         BL              S9xSetDSP
1880                 RESTORE_C_CALL
1881         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1882         LDMFD           R13!,{PC} @ Return
1883 SWLSRAM:
1884         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1885         LDRH            R2,[reg_cpu_var,#SRAMMask]
1886         MOVS            R2,R2
1887         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1888
1889         AND             R3,R2,R0                @ Address&SRAMMask
1890         TST             R0,#1
1891         BNE             SW_not_aligned2
1892         @ aligned
1893         LDR             R0,[reg_cpu_var,#SRAM]
1894         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1895         MOV             R0,#1
1896         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1897         LDMFD           R13!,{PC}  @ return
1898 SW_not_aligned2:
1899
1900         ADD             R0,R0,#1
1901         AND             R2,R2,R0                @ (Address+1)&SRAMMask
1902         LDR             R0,[reg_cpu_var,#SRAM]
1903         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1904         MOV             R1,R1,LSR #8
1905         STRB            R1,[R0,R2]              @ *Memory.SRAM + (Address+1)&SRAMMask
1906         MOV             R0,#1
1907         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1908         LDMFD           R13!,{PC}  @ return
1909 SW7SRM:
1910 SWHSRAM:
1911         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1912
1913         LDRH            R2,[reg_cpu_var,#SRAMMask]
1914         MOVS            R2,R2
1915         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1916
1917         TST             R0,#1
1918         BNE             SW_not_aligned3
1919         @ aligned
1920         MOV             R3,R0,LSL #17
1921         AND             R2,R0,#0xF0000
1922         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1923         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1924         ADD             R0,R2,R3
1925         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1926         LDRH            R2,[reg_cpu_var,#SRAMMask]
1927         LDR             R3,[reg_cpu_var,#SRAM]
1928         AND             R0,R2,R0                @ Address&SRAMMask
1929         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1930         MOV             R0,#1
1931         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1932         LDMFD           R13!,{PC}       @ return
1933 SW_not_aligned3:
1934         MOV             R3,R0,LSL #17
1935         AND             R2,R0,#0xF0000
1936         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1937         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1938         ADD             R2,R2,R3
1939         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1940
1941         ADD             R0,R0,#1
1942         MOV             R3,R0,LSL #17
1943         AND             R0,R0,#0xF0000
1944         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1945         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1946         ADD             R0,R0,R3
1947         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1948         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1949         AND             R2,R3,R2                @ Address...&SRAMMask
1950         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1951
1952         LDR             R3,[reg_cpu_var,#SRAM]
1953         STRB            R1,[R2,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1954         MOV             R1,R1,LSR #8
1955         STRB            R1,[R0,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1956
1957         MOV             R0,#1
1958         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1959         LDMFD           R13!,{PC}       @ return
1960 SW7ROM:
1961 SW7RAM:
1962 SWNONE:
1963 SWDEBUG:
1964         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1965         LDMFD           R13!,{PC}       @ return
1966 SWC4:
1967         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1968         MOV             R0,R0,LSL #16
1969         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1970         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1971         MOV             R2,R1
1972         MOV             R1,R0
1973         MOV             R0,R2
1974                 PREPARE_C_CALL_R0R1
1975         UXTB    R0,R0
1976         BL              S9xSetC4
1977         LDMFD           R13!,{R0,R1}
1978         ADD             R1,R1,#1
1979         UXTB    R0,R0,ROR #8
1980         BIC             R1,R1,#0x10000
1981         BL              S9xSetC4
1982                 RESTORE_C_CALL
1983         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1984         LDMFD           R13!,{PC} @ Return
1985 SWBWRAM:
1986         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1987         TST             R0,#1
1988         BNE             SW_not_aligned4
1989         @ aligned
1990         MOV             R0,R0,LSL #17
1991         LDR             R2,[reg_cpu_var,#BWRAM]
1992         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1993         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1994         MOV             R3,#1
1995         STRH            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1996         STRB            R3,[reg_cpu_var,#SRAMModified_ofs]
1997         LDMFD           R13!,{PC}       @ return
1998 SW_not_aligned4:
1999         MOV             R0,R0,LSL #17
2000         ADD             R3,R0,#0x20000
2001         MOV             R0,R0,LSR #17   @ Address&0x7FFF
2002         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
2003         LDR             R2,[reg_cpu_var,#BWRAM]
2004         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2005         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
2006         STRB            R1,[R2,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2007         MOV             R1,R1,LSR #8
2008         STRB            R1,[R2,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
2009         MOV             R0,#1
2010         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
2011         LDMFD           R13!,{PC}               @ return
2012
2013
2014
2015
2016
2017 /*****************************************************************
2018         FLAGS
2019 *****************************************************************/
2020
2021 .macro          UPDATE_C
2022                 @  CC : ARM Carry Clear
2023                 BICCC   rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2024                 @  CS : ARM Carry Set
2025                 ORRCS   rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2026 .endm
2027 .macro          UPDATE_Z
2028                 @  NE : ARM Zero Clear
2029                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2030                 @  EQ : ARM Zero Set
2031                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2032 .endm
2033 .macro          UPDATE_ZN
2034                 @  NE : ARM Zero Clear
2035                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2036                 @  EQ : ARM Zero Set
2037                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2038                 @  PL : ARM Neg Clear
2039                 BICPL   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2040                 @  MI : ARM Neg Set
2041                 ORRMI   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2042 .endm
2043
2044 /*****************************************************************
2045         OPCODES_MAC
2046 *****************************************************************/
2047
2048
2049
2050
2051 .macro ADC8
2052                 TST rstatus, #MASK_DECIMAL
2053                 BEQ 1111f
2054                 S9xGetByte
2055
2056
2057                 STMFD   R13!,{rscratch}
2058                 MOV     rscratch4,#0x0F000000
2059                 @ rscratch2=xxW1xxxxxxxxxxxx
2060                 AND     rscratch2, rscratch, rscratch4
2061                 @ rscratch=xxW2xxxxxxxxxxxx
2062                 AND     rscratch, rscratch4, rscratch, LSR #4
2063                 @ rscratch3=xxA2xxxxxxxxxxxx
2064                 AND     rscratch3, rscratch4, reg_a, LSR #4
2065                 @ rscratch4=xxA1xxxxxxxxxxxx
2066                 AND     rscratch4,reg_a,rscratch4
2067                 @ R1=A1+W1+CARRY
2068                 TST     rstatus, #MASK_CARRY
2069                 ADDNE   rscratch2, rscratch2, #0x01000000
2070                 ADD     rscratch2,rscratch2,rscratch4
2071                 @  if R1 > 9
2072                 CMP     rscratch2, #0x09000000
2073                 @  then R1 -= 10
2074                 SUBGT   rscratch2, rscratch2, #0x0A000000
2075                 @  then A2++
2076                 ADDGT   rscratch3, rscratch3, #0x01000000
2077                 @  R2 = A2+W2
2078                 ADD     rscratch3, rscratch3, rscratch
2079                 @  if R2 > 9
2080                 CMP     rscratch3, #0x09000000
2081                 @  then R2 -= 10@
2082                 SUBGT   rscratch3, rscratch3, #0x0A000000
2083                 @  then SetCarry()
2084                 ORRGT   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2085                 @  else ClearCarry()
2086                 BICLE   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2087                 @  gather rscratch3 and rscratch2 into ans8
2088                 @  rscratch3 : 0R2000000
2089                 @  rscratch2 : 0R1000000
2090                 @  -> 0xR2R1000000
2091                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2092                 LDMFD   R13!,{rscratch}
2093                 @ only last bit
2094                 AND     rscratch,rscratch,#0x80000000
2095                 @  (register.AL ^ Work8)
2096                 EORS    rscratch3, reg_a, rscratch
2097                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2098                 BNE     1112f
2099                 @  (Work8 ^ Ans8)
2100                 EORS    rscratch3, rscratch2, rscratch
2101                 @  & 0x80
2102                 TSTNE   rscratch3,#0x80000000
2103                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2104                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2105 1112:
2106                 MOVS reg_a, rscratch2
2107                 UPDATE_ZN
2108                 B 1113f
2109 1111:
2110                 S9xGetByteLow
2111                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2112                 SUBCS rscratch, rscratch, #0x100
2113                 ADCS reg_a, reg_a, rscratch, ROR #8
2114                 @ OverFlow
2115                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2116                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2117                 @ Carry
2118                 UPDATE_C
2119                 @ clear lower part
2120                 ANDS reg_a, reg_a, #0xFF000000
2121                 @ Update flag
2122                 UPDATE_ZN
2123 1113:
2124 .endm
2125 /* TO TEST */
2126 .macro ADC16
2127                 TST rstatus, #MASK_DECIMAL
2128                 BEQ 1111f
2129                 S9xGetWord
2130
2131                 @ rscratch = W3W2W1W0........
2132                 LDR     rscratch4, = 0x0F0F0000
2133                 @  rscratch2 = xxW2xxW0xxxxxx
2134                 @  rscratch3 = xxW3xxW1xxxxxx
2135                 AND     rscratch2, rscratch4, rscratch
2136                 AND     rscratch3, rscratch4, rscratch, LSR #4
2137                 @  rscratch2 = xxW3xxW1xxW2xxW0
2138                 ORR     rscratch2, rscratch3, rscratch2, LSR #16
2139                 @  rscratch3 = xxA2xxA0xxxxxx
2140                 @  rscratch4 = xxA3xxA1xxxxxx
2141                 @  rscratch2 = xxA3xxA1xxA2xxA0
2142                 AND     rscratch3, rscratch4, reg_a
2143                 AND     rscratch4, rscratch4, reg_a, LSR #4
2144                 ORR     rscratch3, rscratch4, rscratch3, LSR #16
2145                 ADD     rscratch2, rscratch3, rscratch2
2146                 LDR     rscratch4, = 0x0F0F0000
2147                 @  rscratch2 = A + W
2148                 TST     rstatus, #MASK_CARRY
2149                 ADDNE   rscratch2, rscratch2, #0x1
2150                 @  rscratch2 = A + W + C
2151                 @ A0
2152                 AND     rscratch3, rscratch2, #0x0000001F
2153                 CMP     rscratch3, #0x00000009
2154                 ADDHI   rscratch2, rscratch2, #0x00010000
2155                 SUBHI   rscratch2, rscratch2, #0x0000000A
2156                 @ A1
2157                 AND     rscratch3, rscratch2, #0x001F0000
2158                 CMP     rscratch3, #0x00090000
2159                 ADDHI   rscratch2, rscratch2, #0x00000100
2160                 SUBHI   rscratch2, rscratch2, #0x000A0000
2161                 @ A2
2162                 AND     rscratch3, rscratch2, #0x00001F00
2163                 CMP     rscratch3, #0x00000900
2164                 SUBHI   rscratch2, rscratch2, #0x00000A00
2165                 ADDHI   rscratch2, rscratch2, #0x01000000
2166                 @ A3
2167                 AND     rscratch3, rscratch2, #0x1F000000
2168                 CMP     rscratch3, #0x09000000
2169                 SUBHI   rscratch2, rscratch2, #0x0A000000
2170                 @ SetCarry
2171                 ORRHI   rstatus, rstatus, #MASK_CARRY
2172                 @ ClearCarry
2173                 BICLS   rstatus, rstatus, #MASK_CARRY
2174                 @ rscratch2 = xxR3xxR1xxR2xxR0
2175                 @ Pack result
2176                 @ rscratch3 = xxR3xxR1xxxxxxxx
2177                 AND     rscratch3, rscratch4, rscratch2
2178                 @ rscratch2 = xxR2xxR0xxxxxxxx
2179                 AND     rscratch2, rscratch4, rscratch2,LSL #16
2180                 @ rscratch2 = R3R2R1R0xxxxxxxx
2181                 ORR     rscratch2, rscratch2,rscratch3,LSL #4
2182 @ only last bit
2183                 AND     rscratch,rscratch,#0x80000000
2184                 @  (register.AL ^ Work8)
2185                 EORS    rscratch3, reg_a, rscratch
2186                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2187                 BNE     1112f
2188                 @  (Work8 ^ Ans8)
2189                 EORS    rscratch3, rscratch2, rscratch
2190                 TSTNE   rscratch3,#0x80000000
2191                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2192                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2193 1112:
2194                 MOVS    reg_a, rscratch2
2195                 UPDATE_ZN
2196                 B       1113f
2197 1111:
2198                 S9xGetWordLow
2199                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2200                 SUBCS rscratch, rscratch, #0x10000
2201                 ADCS reg_a, reg_a,rscratch, ROR #16
2202                 @ OverFlow
2203                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2204                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2205                 MOV reg_a, reg_a, LSR #16
2206                 @ Carry
2207                 UPDATE_C
2208                 @ clear lower parts
2209                 MOVS reg_a, reg_a, LSL #16
2210                 @ Update flag
2211                 UPDATE_ZN
2212 1113:
2213 .endm
2214
2215
2216 .macro          AND16
2217                 S9xGetWord
2218                 ANDS            reg_a, reg_a, rscratch
2219                 UPDATE_ZN
2220 .endm
2221 .macro          AND8
2222                 S9xGetByte
2223                 ANDS            reg_a, reg_a, rscratch
2224                 UPDATE_ZN
2225 .endm
2226 .macro          A_ASL8
2227                 @  7    instr
2228                 MOVS    reg_a, reg_a, LSL #1
2229                 UPDATE_C
2230                 UPDATE_ZN
2231                 ADD1CYCLE
2232 .endm
2233 .macro          A_ASL16
2234                 @  7    instr
2235                 MOVS    reg_a, reg_a, LSL #1
2236                 UPDATE_C
2237                 UPDATE_ZN
2238                 ADD1CYCLE
2239 .endm
2240 .macro          ASL16
2241                 S9xGetWordRegNS rscratch2             @         do not destroy Opadress in rscratch
2242                 MOVS            rscratch2, rscratch2, LSL #1
2243                 UPDATE_C
2244                 UPDATE_ZN
2245                 S9xSetWord      rscratch2
2246                 ADD1CYCLE
2247 .endm
2248 .macro          ASL8
2249                 S9xGetByteRegNS rscratch2             @         do not destroy Opadress in rscratch
2250                 MOVS            rscratch2, rscratch2, LSL #1
2251                 UPDATE_C
2252                 UPDATE_ZN
2253                 S9xSetByte      rscratch2
2254                 ADD1CYCLE
2255 .endm
2256 .macro          BIT8
2257                 S9xGetByte
2258                 MOVS    rscratch2, rscratch, LSL #1
2259                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2260                 @                                         ARM N = Snes V
2261                 @  If Carry Set, then Set Neg in SNES
2262                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set C to zero
2263                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set C to one
2264                 @  If Neg Set, then Set Overflow in SNES
2265                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set N to zero
2266                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set N to one
2267
2268                 @  Now do a real AND    with A register
2269                 @  Set Zero Flag, bit test
2270                 ANDS    rscratch2, reg_a, rscratch
2271                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2272                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2273 .endm
2274
2275 .macro          BIT16
2276                 S9xGetWord
2277                 MOVS    rscratch2, rscratch, LSL #1
2278                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2279                 @                                         ARM N = Snes V
2280                 @  If Carry Set, then Set Neg in SNES
2281                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2282                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2283                 @  If Neg Set, then Set Overflow in SNES
2284                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set V to zero
2285                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set V to one
2286                 @  Now do a real AND    with A register
2287                 @  Set Zero Flag, bit test
2288                 ANDS    rscratch2, reg_a, rscratch
2289                 @  Bit set  ->Z=0->xxxNE Clear flag
2290                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2291                 @  Bit clear->Z=1->xxxEQ Set flag
2292                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2293 .endm
2294 .macro          CMP8
2295                 S9xGetByte
2296                 SUBS    rscratch2,reg_a,rscratch
2297                 BICCC   rstatus, rstatus, #MASK_CARRY
2298                 ORRCS   rstatus, rstatus, #MASK_CARRY
2299                 UPDATE_ZN
2300
2301 .endm
2302 .macro          CMP16
2303                 S9xGetWord
2304                 SUBS    rscratch2,reg_a,rscratch
2305                 BICCC   rstatus, rstatus, #MASK_CARRY
2306                 ORRCS   rstatus, rstatus, #MASK_CARRY
2307                 UPDATE_ZN
2308
2309 .endm
2310 .macro          CMX16
2311                 S9xGetWord
2312                 SUBS    rscratch2,reg_x,rscratch
2313                 BICCC   rstatus, rstatus, #MASK_CARRY
2314                 ORRCS   rstatus, rstatus, #MASK_CARRY
2315                 UPDATE_ZN
2316 .endm
2317 .macro          CMX8
2318                 S9xGetByte
2319                 SUBS    rscratch2,reg_x,rscratch
2320                 BICCC   rstatus, rstatus, #MASK_CARRY
2321                 ORRCS   rstatus, rstatus, #MASK_CARRY
2322                 UPDATE_ZN
2323 .endm
2324 .macro          CMY16
2325                 S9xGetWord
2326                 SUBS    rscratch2,reg_y,rscratch
2327                 BICCC   rstatus, rstatus, #MASK_CARRY
2328                 ORRCS   rstatus, rstatus, #MASK_CARRY
2329                 UPDATE_ZN
2330 .endm
2331 .macro          CMY8
2332                 S9xGetByte
2333                 SUBS    rscratch2,reg_y,rscratch
2334                 BICCC   rstatus, rstatus, #MASK_CARRY
2335                 ORRCS   rstatus, rstatus, #MASK_CARRY
2336                 UPDATE_ZN
2337 .endm
2338 .macro          A_DEC8
2339                 MOV             rscratch,#0
2340                 SUBS            reg_a, reg_a, #0x01000000
2341                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2342                 UPDATE_ZN
2343                 ADD1CYCLE
2344 .endm
2345 .macro          A_DEC16
2346                 MOV             rscratch,#0
2347                 SUBS            reg_a, reg_a, #0x00010000
2348                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2349                 UPDATE_ZN
2350                 ADD1CYCLE
2351 .endm
2352 .macro          DEC16
2353                 S9xGetWordRegNS rscratch2              @  do not        destroy Opadress in rscratch
2354                 MOV             rscratch3,#0
2355                 SUBS            rscratch2, rscratch2, #0x00010000
2356                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2357                 UPDATE_ZN
2358                 S9xSetWord      rscratch2
2359                 ADD1CYCLE
2360 .endm
2361 .macro          DEC8
2362                 S9xGetByteRegNS rscratch2              @  do not        destroy Opadress in rscratch
2363                 MOV             rscratch3,#0
2364                 SUBS            rscratch2, rscratch2, #0x01000000
2365                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2366                 UPDATE_ZN
2367                 S9xSetByte      rscratch2
2368                 ADD1CYCLE
2369 .endm
2370 .macro          EOR16
2371                 S9xGetWord
2372                 EORS            reg_a, reg_a, rscratch
2373                 UPDATE_ZN
2374 .endm
2375 .macro          EOR8
2376                 S9xGetByte
2377                 EORS            reg_a, reg_a, rscratch
2378                 UPDATE_ZN
2379 .endm
2380 .macro          A_INC8
2381                 MOV             rscratch3,#0
2382                 ADDS            reg_a, reg_a, #0x01000000
2383                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2384                 UPDATE_ZN
2385                 ADD1CYCLE
2386 .endm
2387 .macro          A_INC16
2388                 MOV             rscratch3,#0
2389                 ADDS            reg_a, reg_a, #0x00010000
2390                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2391                 UPDATE_ZN
2392                 ADD1CYCLE
2393 .endm
2394 .macro          INC16
2395                 S9xGetWordRegNS rscratch2
2396                 MOV             rscratch3,#0
2397                 ADDS            rscratch2, rscratch2, #0x00010000
2398                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2399                 UPDATE_ZN
2400                 S9xSetWord      rscratch2
2401                 ADD1CYCLE
2402 .endm
2403 .macro          INC8
2404                 S9xGetByteRegNS rscratch2
2405                 MOV             rscratch3,#0
2406                 ADDS            rscratch2, rscratch2, #0x01000000
2407                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2408                 UPDATE_ZN
2409                 S9xSetByte      rscratch2
2410                 ADD1CYCLE
2411 .endm
2412 .macro          LDA16
2413                 S9xGetWordRegStatus reg_a
2414                 UPDATE_ZN
2415 .endm
2416 .macro          LDA8
2417                 S9xGetByteRegStatus reg_a
2418                 UPDATE_ZN
2419 .endm
2420 .macro          LDX16
2421                 S9xGetWordRegStatus reg_x
2422                 UPDATE_ZN
2423 .endm
2424 .macro          LDX8
2425                 S9xGetByteRegStatus reg_x
2426                 UPDATE_ZN
2427 .endm
2428 .macro          LDY16
2429                 S9xGetWordRegStatus reg_y
2430                 UPDATE_ZN
2431 .endm
2432 .macro          LDY8
2433                 S9xGetByteRegStatus reg_y
2434                 UPDATE_ZN
2435 .endm
2436 .macro          A_LSR16
2437                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2438                 MOVS    reg_a, reg_a, LSR #17            @  hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
2439                 @  Update Zero
2440                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2441                 MOV     reg_a, reg_a, LSL #16                   @  -> 0lllllll 00000000 00000000        00000000
2442                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2443                 @  Note : the two MOV are included between instruction, to optimize
2444                 @  the pipeline.
2445                 UPDATE_C
2446                 ADD1CYCLE
2447 .endm
2448 .macro          A_LSR8
2449                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2450                 MOVS    reg_a, reg_a, LSR #25            @  llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2451                 @  Update Zero
2452                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2453                 MOV     reg_a, reg_a, LSL #24                   @  -> 00000000 00000000 00000000        0lllllll
2454                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2455                 @  Note : the two MOV are included between instruction, to optimize
2456                 @  the pipeline.
2457                 UPDATE_C
2458                 ADD1CYCLE
2459 .endm
2460 .macro          LSR16
2461                 S9xGetWordRegNS rscratch2
2462                 @  N set to zero by >> 1 LSR
2463                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2464                 MOVS            rscratch2, rscratch2, LSR #17              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2465                 @  Update Carry
2466                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2467                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2468                 @  Update Zero
2469                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2470                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2471                 S9xSetWordLow   rscratch2
2472                 ADD1CYCLE
2473 .endm
2474 .macro          LSR8
2475                 S9xGetByteRegNS rscratch2
2476                 @  N set to zero by >> 1 LSR
2477                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2478                 MOVS            rscratch2, rscratch2, LSR #25              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2479                 @  Update Carry
2480                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2481                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2482                 @  Update Zero
2483                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2484                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2485                 S9xSetByteLow   rscratch2
2486                 ADD1CYCLE
2487 .endm
2488 .macro          ORA8
2489                 S9xGetByte
2490                 ORRS            reg_a, reg_a, rscratch
2491                 UPDATE_ZN
2492 .endm
2493 .macro          ORA16
2494                 S9xGetWord
2495                 ORRS            reg_a, reg_a, rscratch
2496                 UPDATE_ZN
2497 .endm
2498 .macro          A_ROL16
2499                 TST             rstatus, #MASK_CARRY
2500                 ORRNE           reg_a, reg_a, #0x00008000
2501                 MOVS            reg_a, reg_a, LSL #1
2502                 UPDATE_ZN
2503                 UPDATE_C
2504                 ADD1CYCLE
2505 .endm
2506 .macro          A_ROL8
2507                 TST             rstatus, #MASK_CARRY
2508                 ORRNE           reg_a, reg_a, #0x00800000
2509                 MOVS            reg_a, reg_a, LSL #1
2510                 UPDATE_ZN
2511                 UPDATE_C
2512                 ADD1CYCLE
2513 .endm
2514 .macro          ROL16
2515                 S9xGetWordRegNS rscratch2
2516                 TST             rstatus, #MASK_CARRY
2517                 ORRNE           rscratch2, rscratch2, #0x00008000
2518                 MOVS            rscratch2, rscratch2, LSL #1
2519                 UPDATE_ZN
2520                 UPDATE_C
2521                 S9xSetWord      rscratch2
2522                 ADD1CYCLE
2523 .endm
2524 .macro          ROL8
2525                 S9xGetByteRegNS rscratch2
2526                 TST             rstatus, #MASK_CARRY
2527                 ORRNE           rscratch2, rscratch2, #0x00800000
2528                 MOVS            rscratch2, rscratch2, LSL #1
2529                 UPDATE_ZN
2530                 UPDATE_C
2531                 S9xSetByte      rscratch2
2532                 ADD1CYCLE
2533 .endm
2534 .macro          A_ROR16
2535                 MOV                     reg_a,reg_a, LSR #16
2536                 TST                     rstatus, #MASK_CARRY
2537                 ORRNE                   reg_a, reg_a, #0x00010000
2538                 ORRNE                   rstatus,rstatus,#MASK_NEG
2539                 BICEQ                   rstatus,rstatus,#MASK_NEG
2540                 MOVS                    reg_a,reg_a,LSR #1
2541                 UPDATE_C
2542                 UPDATE_Z
2543                 MOV                     reg_a,reg_a, LSL #16
2544                 ADD1CYCLE
2545 .endm
2546 .macro          A_ROR8
2547                 MOV                     reg_a,reg_a, LSR #24
2548                 TST                     rstatus, #MASK_CARRY
2549                 ORRNE                   reg_a, reg_a, #0x00000100
2550                 ORRNE                   rstatus,rstatus,#MASK_NEG
2551                 BICEQ                   rstatus,rstatus,#MASK_NEG
2552                 MOVS                    reg_a,reg_a,LSR #1
2553                 UPDATE_C
2554                 UPDATE_Z
2555                 MOV                     reg_a,reg_a, LSL #24
2556                 ADD1CYCLE
2557 .endm
2558 .macro          ROR16
2559                 S9xGetWordLowRegNS      rscratch2
2560                 TST                     rstatus, #MASK_CARRY
2561                 ORRNE                   rscratch2, rscratch2, #0x00010000
2562                 ORRNE                   rstatus,rstatus,#MASK_NEG
2563                 BICEQ                   rstatus,rstatus,#MASK_NEG
2564                 MOVS                    rscratch2,rscratch2,LSR #1
2565                 UPDATE_C
2566                 UPDATE_Z
2567                 S9xSetWordLow   rscratch2
2568                 ADD1CYCLE
2569
2570 .endm
2571 .macro          ROR8
2572                 S9xGetByteLowRegNS      rscratch2
2573                 TST                     rstatus, #MASK_CARRY
2574                 ORRNE                   rscratch2, rscratch2, #0x00000100
2575                 ORRNE                   rstatus,rstatus,#MASK_NEG
2576                 BICEQ                   rstatus,rstatus,#MASK_NEG
2577                 MOVS                    rscratch2,rscratch2,LSR #1
2578                 UPDATE_C
2579                 UPDATE_Z
2580                 S9xSetByteLow   rscratch2
2581                 ADD1CYCLE
2582 .endm
2583
2584 .macro SBC16
2585         TST rstatus, #MASK_DECIMAL
2586                 BEQ 1111f
2587                 @ TODO
2588                 S9xGetWord
2589
2590                 STMFD   R13!,{rscratch9}
2591                 MOV     rscratch9,#0x000F0000
2592         @ rscratch2 - result
2593         @ rscratch3 - scratch
2594         @ rscratch4 - scratch
2595         @ rscratch9 - pattern
2596
2597                 AND     rscratch2, rscratch, #0x000F0000
2598                 TST     rstatus, #MASK_CARRY
2599                 ADDEQ   rscratch2, rscratch2, #0x00010000  @ W1=W1+!Carry
2600                 AND     rscratch4, reg_a, #0x000F0000
2601         SUB     rscratch2, rscratch4,rscratch2          @ R1=A1-W1-!Carry
2602                 CMP     rscratch2, #0x00090000  @  if R1 > 9
2603                 ADDHI   rscratch2, rscratch2, #0x000A0000 @  then R1 += 10
2604                 AND         rscratch2, rscratch2, #0x000F0000
2605
2606                 AND     rscratch3, rscratch9, rscratch, LSR #4
2607         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W2++)
2608
2609                 AND     rscratch4, rscratch9, reg_a, LSR #4
2610         SUB     rscratch3, rscratch4, rscratch3         @ R2=A2-W2
2611                 CMP     rscratch3, #0x00090000  @  if R2 > 9
2612                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R2 += 10
2613                 AND         rscratch3, rscratch3, #0x000F0000
2614                 ORR         rscratch2, rscratch2, rscratch3,LSL #4
2615
2616                 AND     rscratch3, rscratch9, rscratch, LSR #8
2617         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2618
2619                 AND     rscratch4, rscratch9, reg_a, LSR #8
2620         SUB     rscratch3, rscratch4, rscratch3         @ R3=A3-W3
2621                 CMP     rscratch3, #0x00090000  @  if R3 > 9
2622                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R3 += 10
2623                 AND         rscratch3, rscratch3, #0x000F0000
2624                 ORR         rscratch2, rscratch2, rscratch3,LSL #8
2625
2626                 AND     rscratch3, rscratch9, rscratch, LSR #12
2627         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2628
2629                 AND     rscratch4, rscratch9, reg_a, LSR #12
2630         SUB     rscratch3, rscratch4, rscratch3         @ R4=A4-W4
2631                 CMP     rscratch3, #0x00090000  @  if R4 > 9
2632                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R4 += 10
2633                 BICHI   rstatus, rstatus, #MASK_CARRY   @  then ClearCarry
2634                 ORRLS   rstatus, rstatus, #MASK_CARRY   @  else SetCarry
2635
2636                 AND         rscratch3,rscratch3,#0x000F0000
2637                 ORR         rscratch2,rscratch2,rscratch3,LSL #12
2638
2639                 LDMFD   R13!,{rscratch9}
2640                 @ only last bit
2641                 AND     reg_a,reg_a,#0x80000000
2642                 @  (register.A.W ^ Work8)
2643                 EORS    rscratch3, reg_a, rscratch
2644                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2645                 BEQ     1112f
2646                 @  (register.A.W ^ Ans8)
2647                 EORS    rscratch3, reg_a, rscratch2
2648                 @  & 0x80
2649                 TSTNE   rscratch3,#0x80000000
2650                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2651                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2652 1112:
2653                 MOVS    reg_a, rscratch2
2654                 UPDATE_ZN
2655                 B 1113f
2656 1111:
2657                 S9xGetWordLow
2658                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2659                 SBCS reg_a, reg_a, rscratch, LSL #16
2660                 @ OverFlow
2661                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2662                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2663                 MOV reg_a, reg_a, LSR #16
2664                 @ Carry
2665                 UPDATE_C
2666                 MOVS reg_a, reg_a, LSL #16
2667                 @ Update flag
2668                 UPDATE_ZN
2669 1113:
2670 .endm
2671
2672 .macro SBC8
2673                 TST rstatus, #MASK_DECIMAL
2674                 BEQ 1111f
2675                 S9xGetByte
2676                 STMFD   R13!,{rscratch}
2677                 MOV     rscratch4,#0x0F000000
2678                 @ rscratch2=xxW1xxxxxxxxxxxx
2679                 AND     rscratch2, rscratch, rscratch4
2680                 @ rscratch=xxW2xxxxxxxxxxxx
2681                 AND     rscratch, rscratch4, rscratch, LSR #4
2682                 @ rscratch3=xxA2xxxxxxxxxxxx
2683                 AND     rscratch3, rscratch4, reg_a, LSR #4
2684                 @ rscratch4=xxA1xxxxxxxxxxxx
2685                 AND     rscratch4,reg_a,rscratch4
2686                 @ R1=A1-W1-!CARRY
2687                 TST     rstatus, #MASK_CARRY
2688                 ADDEQ   rscratch2, rscratch2, #0x01000000
2689                 SUB     rscratch2,rscratch4,rscratch2
2690                 @  if R1 > 9
2691                 CMP     rscratch2, #0x09000000
2692                 @  then R1 += 10
2693                 ADDHI   rscratch2, rscratch2, #0x0A000000
2694                 @  then A2-- (W2++)
2695                 ADDHI   rscratch, rscratch, #0x01000000
2696                 @  R2=A2-W2
2697                 SUB     rscratch3, rscratch3, rscratch
2698                 @  if R2 > 9
2699                 CMP     rscratch3, #0x09000000
2700                 @  then R2 -= 10@
2701                 ADDHI   rscratch3, rscratch3, #0x0A000000
2702                 @  then SetCarry()
2703                 BICHI   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2704                 @  else ClearCarry()
2705                 ORRLS   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2706                 @  gather rscratch3 and rscratch2 into ans8
2707                 AND     rscratch3,rscratch3,#0x0F000000
2708                 AND     rscratch2,rscratch2,#0x0F000000
2709                 @  rscratch3 : 0R2000000
2710                 @  rscratch2 : 0R1000000
2711                 @  -> 0xR2R1000000
2712                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2713                 LDMFD   R13!,{rscratch}
2714                 @ only last bit
2715                 AND     reg_a,reg_a,#0x80000000
2716                 @  (register.AL ^ Work8)
2717                 EORS    rscratch3, reg_a, rscratch
2718                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2719                 BEQ     1112f
2720                 @  (register.AL ^ Ans8)
2721                 EORS    rscratch3, reg_a, rscratch2
2722                 @  & 0x80
2723                 TSTNE   rscratch3,#0x80000000
2724                 BICEQ rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2725                 ORRNE rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2726 1112:
2727                 MOVS reg_a, rscratch2
2728                 UPDATE_ZN
2729                 B 1113f
2730 1111:
2731                 S9xGetByteLow
2732                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2733                 SBCS reg_a, reg_a, rscratch, LSL #24
2734                 @ OverFlow
2735                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2736                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2737                 @ Carry
2738                 UPDATE_C
2739                 @ Update flag
2740                 ANDS reg_a, reg_a, #0xFF000000
2741                 UPDATE_ZN
2742 1113:
2743 .endm
2744
2745 .macro          STA16
2746                 S9xSetWord      reg_a
2747 .endm
2748 .macro          STA8
2749                 S9xSetByte      reg_a
2750 .endm
2751 .macro          STX16
2752                 S9xSetWord      reg_x
2753 .endm
2754 .macro          STX8
2755                 S9xSetByte      reg_x
2756 .endm
2757 .macro          STY16
2758                 S9xSetWord      reg_y
2759 .endm
2760 .macro          STY8
2761                 S9xSetByte      reg_y
2762 .endm
2763 .macro          STZ16
2764                 S9xSetWordZero
2765 .endm
2766 .macro          STZ8
2767                 S9xSetByteZero
2768 .endm
2769 .macro          TSB16
2770                 S9xGetWordRegNS rscratch2
2771                 TST             reg_a, rscratch2
2772                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2773                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2774                 ORR             rscratch2, reg_a, rscratch2
2775                 S9xSetWord      rscratch2
2776                 ADD1CYCLE
2777 .endm
2778 .macro          TSB8
2779                 S9xGetByteRegNS rscratch2
2780                 TST             reg_a, rscratch2
2781                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2782                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2783                 ORR             rscratch2, reg_a, rscratch2
2784                 S9xSetByte      rscratch2
2785                 ADD1CYCLE
2786 .endm
2787 .macro          TRB16
2788                 S9xGetWordRegNS rscratch2
2789                 TST             reg_a, rscratch2
2790                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2791                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2792                 MVN             rscratch3, reg_a
2793                 AND             rscratch2, rscratch3, rscratch2
2794                 S9xSetWord      rscratch2
2795                 ADD1CYCLE
2796 .endm
2797 .macro          TRB8
2798                 S9xGetByteRegNS rscratch2
2799                 TST             reg_a, rscratch2
2800                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2801                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2802                 MVN             rscratch3, reg_a
2803                 AND             rscratch2, rscratch3, rscratch2
2804                 S9xSetByte      rscratch2
2805                 ADD1CYCLE
2806 .endm
2807 /**************************************************************************/
2808
2809
2810 /**************************************************************************/
2811
2812 .macro          Op09M0          /*ORA*/
2813                 LDRB            rscratch2, [rpc,#1]
2814                 LDRB            rscratch, [rpc], #2
2815                 ORR             rscratch2,rscratch,rscratch2,LSL #8
2816                 ORRS            reg_a,reg_a,rscratch2,LSL #16
2817                 UPDATE_ZN
2818                 ADD2MEM
2819 .endm
2820 .macro          Op09M1          /*ORA*/
2821                 LDRB            rscratch, [rpc], #1
2822                 ORRS            reg_a,reg_a,rscratch,LSL #24
2823                 UPDATE_ZN
2824                 ADD1MEM
2825 .endm
2826 /***********************************************************************/
2827 .macro          Op90    /*BCC*/
2828                 asmRelative
2829                 BranchCheck0
2830                 TST             rstatus, #MASK_CARRY
2831                 BNE             1111f
2832                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2833                 ADD1CYCLE
2834                 CPUShutdown
2835 1111:
2836 .endm
2837 .macro          OpB0    /*BCS*/
2838                 asmRelative
2839                 BranchCheck0
2840                 TST             rstatus, #MASK_CARRY
2841                 BEQ             1111f
2842                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2843                 ADD1CYCLE
2844                 CPUShutdown
2845 1111:
2846 .endm
2847 .macro          OpF0    /*BEQ*/
2848                 asmRelative
2849                 BranchCheck2
2850                 TST             rstatus, #MASK_ZERO
2851                 BEQ             1111f
2852                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2853                 ADD1CYCLE
2854                 CPUShutdown
2855 1111:
2856 .endm
2857 .macro          OpD0    /*BNE*/
2858                 asmRelative
2859                 BranchCheck1
2860                 TST             rstatus, #MASK_ZERO
2861                 BNE             1111f
2862                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2863                 ADD1CYCLE
2864                 CPUShutdown
2865 1111:
2866 .endm
2867 .macro          Op30    /*BMI*/
2868                 asmRelative
2869                 BranchCheck0
2870                 TST             rstatus, #MASK_NEG
2871                 BEQ             1111f
2872                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2873                 ADD1CYCLE
2874                 CPUShutdown
2875 1111:
2876 .endm
2877 .macro          Op10   /*BPL*/
2878                 asmRelative
2879                 BranchCheck1
2880                 TST             rstatus, #MASK_NEG @  neg, z!=0, NE
2881                 BNE             1111f
2882                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2883                 ADD1CYCLE
2884                 CPUShutdown
2885 1111:
2886 .endm
2887 .macro          Op50   /*BVC*/
2888                 asmRelative
2889                 BranchCheck0
2890                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2891                 BNE             1111f
2892                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2893                 ADD1CYCLE
2894                 CPUShutdown
2895 1111:
2896 .endm
2897 .macro          Op70   /*BVS*/
2898                 asmRelative
2899                 BranchCheck0
2900                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2901                 BEQ             1111f
2902                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2903                 ADD1CYCLE
2904                 CPUShutdown
2905 1111:
2906 .endm
2907 .macro          Op80   /*BRA*/
2908                 asmRelative
2909                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2910                 ADD1CYCLE
2911                 CPUShutdown
2912 1111:
2913 .endm
2914 /*******************************************************************************************/
2915 /************************************************************/
2916 /* SetFlag Instructions ********************************************************************** */
2917 .macro          Op38 /*SEC*/
2918                 ORR             rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2919                 ADD1CYCLE
2920 .endm
2921 .macro          OpF8 /*SED*/
2922                 SetDecimal
2923                 ADD1CYCLE
2924 .endm
2925 .macro          Op78 /*SEI*/
2926                 SetIRQ
2927                 ADD1CYCLE
2928 .endm
2929
2930
2931 /****************************************************************************************/
2932 /* ClearFlag Instructions ******************************************************************** */
2933 .macro          Op18  /*CLC*/
2934                 BIC             rstatus, rstatus, #MASK_CARRY
2935                 ADD1CYCLE
2936 .endm
2937 .macro          OpD8 /*CLD*/
2938                 ClearDecimal
2939                 ADD1CYCLE
2940 .endm
2941 .macro          Op58  /*CLI*/
2942                 ClearIRQ
2943                 ADD1CYCLE
2944                 @ CHECK_FOR_IRQ
2945 .endm
2946 .macro          OpB8 /*CLV*/
2947                 BIC             rstatus, rstatus, #MASK_OVERFLOW
2948                 ADD1CYCLE
2949 .endm
2950
2951 /******************************************************************************************/
2952 /* DEX/DEY *********************************************************************************** */
2953
2954 .macro          OpCAX1  /*DEX*/
2955                 MOV             rscratch3,#0
2956                 SUBS            reg_x, reg_x, #0x01000000
2957                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2958                 UPDATE_ZN
2959                 ADD1CYCLE
2960 .endm
2961 .macro          OpCAX0  /*DEX*/
2962                 MOV             rscratch3,#0
2963                 SUBS            reg_x, reg_x, #0x00010000
2964                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2965                 UPDATE_ZN
2966                 ADD1CYCLE
2967 .endm
2968 .macro          Op88X1 /*DEY*/
2969                 MOV             rscratch3,#0
2970                 SUBS            reg_y, reg_y, #0x01000000
2971                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2972                 UPDATE_ZN
2973                 ADD1CYCLE
2974 .endm
2975 .macro          Op88X0 /*DEY*/
2976                 MOV             rscratch3,#0
2977                 SUBS            reg_y, reg_y, #0x00010000
2978                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2979                 UPDATE_ZN
2980                 ADD1CYCLE
2981 .endm
2982
2983 /******************************************************************************************/
2984 /* INX/INY *********************************************************************************** */
2985 .macro          OpE8X1
2986                 MOV             rscratch3,#0
2987                 ADDS            reg_x, reg_x, #0x01000000
2988                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2989                 UPDATE_ZN
2990                 ADD1CYCLE
2991 .endm
2992 .macro          OpE8X0
2993                 MOV             rscratch3,#0
2994                 ADDS            reg_x, reg_x, #0x00010000
2995                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2996                 UPDATE_ZN
2997                 ADD1CYCLE
2998 .endm
2999 .macro          OpC8X1
3000                 MOV             rscratch3,#0
3001                 ADDS            reg_y, reg_y, #0x01000000
3002                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3003                 UPDATE_ZN
3004                 ADD1CYCLE
3005 .endm
3006 .macro          OpC8X0
3007                 MOV             rscratch3,#0
3008                 ADDS            reg_y, reg_y, #0x00010000
3009                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3010                 UPDATE_ZN
3011                 ADD1CYCLE
3012 .endm
3013
3014 /**********************************************************************************************/
3015
3016 /* NOP *************************************************************************************** */
3017 .macro          OpEA
3018                 ADD1CYCLE
3019 .endm
3020
3021 /**************************************************************************/
3022 /* PUSH Instructions **************************************************** */
3023 .macro          OpF4
3024                 Absolute
3025                 PushWrLow
3026 .endm
3027 .macro          OpD4
3028                 DirectIndirect
3029                 PushWrLow
3030 .endm
3031 .macro          Op62
3032                 asmRelativeLong
3033                 PushWrLow
3034 .endm
3035 .macro          Op48M0
3036                 PushW           reg_a
3037                 ADD1CYCLE
3038 .endm
3039 .macro          Op48M1
3040                 PushB           reg_a
3041                 ADD1CYCLE
3042 .endm
3043 .macro          Op8B
3044                 AND             rscratch2, reg_d_bank, #0xFF
3045                 PushBLow        rscratch2
3046                 ADD1CYCLE
3047 .endm
3048 .macro          Op0B
3049                 PushW           reg_d
3050                 ADD1CYCLE
3051 .endm
3052 .macro          Op4B
3053                 PushBlow        reg_p_bank
3054                 ADD1CYCLE
3055 .endm
3056 .macro          Op08
3057                 PushB           rstatus
3058                 ADD1CYCLE
3059 .endm
3060 .macro          OpDAX1
3061                 PushB           reg_x
3062                 ADD1CYCLE
3063 .endm
3064 .macro          OpDAX0
3065                 PushW           reg_x
3066                 ADD1CYCLE
3067 .endm
3068 .macro          Op5AX1
3069                 PushB           reg_y
3070                 ADD1CYCLE
3071 .endm
3072 .macro          Op5AX0
3073                 PushW           reg_y
3074                 ADD1CYCLE
3075 .endm
3076 /**************************************************************************/
3077 /* PULL Instructions **************************************************** */
3078 .macro          Op68M1
3079                 PullBS          reg_a
3080                 UPDATE_ZN
3081                 ADD2CYCLE
3082 .endm
3083 .macro          Op68M0
3084                 PullWS          reg_a
3085                 UPDATE_ZN
3086                 ADD2CYCLE
3087 .endm
3088 .macro          OpAB
3089                 BIC             reg_d_bank,reg_d_bank, #0xFF
3090                 PullBrS
3091                 ORR             reg_d_bank,reg_d_bank,rscratch, LSR #24
3092                 UPDATE_ZN
3093                 ADD2CYCLE
3094 .endm
3095 .macro          Op2B
3096                 BIC             reg_d,reg_d, #0xFF000000
3097                 BIC             reg_d,reg_d, #0x00FF0000
3098                 PullWrS
3099                 ORR             reg_d,rscratch,reg_d
3100                 UPDATE_ZN
3101                 ADD2CYCLE
3102 .endm
3103 .macro          Op28X1M1        /*PLP*/
3104                 @ INDEX set, MEMORY set
3105                 BIC             rstatus,rstatus,#0xFF000000
3106                 PullBr
3107                 ORR             rstatus,rscratch,rstatus
3108                 TST             rstatus, #MASK_INDEX
3109                 @ INDEX clear & was set : 8->16
3110                 MOVEQ           reg_x,reg_x,LSR #8
3111                 MOVEQ           reg_y,reg_y,LSR #8
3112                 TST             rstatus, #MASK_MEM
3113                 @ MEMORY cleared & was set : 8->16
3114                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3115                 MOVEQ           reg_a,reg_a,LSR #8
3116                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3117                 S9xFixCycles
3118                 ADD2CYCLE
3119 .endm
3120 .macro          Op28X0M1        /*PLP*/
3121                 @ INDEX cleared, MEMORY set
3122                 BIC             rstatus,rstatus,#0xFF000000
3123                 PullBr
3124                 ORR             rstatus,rscratch,rstatus
3125                 TST             rstatus, #MASK_INDEX
3126                 @ INDEX set & was cleared : 16->8
3127                 MOVNE           reg_x,reg_x,LSL #8
3128                 MOVNE           reg_y,reg_y,LSL #8
3129                 TST             rstatus, #MASK_MEM
3130                 @ MEMORY cleared & was set : 8->16
3131                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3132                 MOVEQ           reg_a,reg_a,LSR #8
3133                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3134                 S9xFixCycles
3135                 ADD2CYCLE
3136 .endm
3137 .macro          Op28X1M0        /*PLP*/
3138                 @ INDEX set, MEMORY set
3139                 BIC             rstatus,rstatus,#0xFF000000
3140                 PullBr
3141                 ORR             rstatus,rscratch,rstatus
3142                 TST             rstatus, #MASK_INDEX
3143                 @ INDEX clear & was set : 8->16
3144                 MOVEQ           reg_x,reg_x,LSR #8
3145                 MOVEQ           reg_y,reg_y,LSR #8
3146                 TST             rstatus, #MASK_MEM
3147                 @ MEMORY set & was cleared : 16->8
3148                 MOVNE           rscratch,reg_a,LSR #24
3149                 MOVNE           reg_a,reg_a,LSL #8
3150                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3151                 S9xFixCycles
3152                 ADD2CYCLE
3153 .endm
3154 .macro          Op28X0M0        /*PLP*/
3155                 @ INDEX set, MEMORY set
3156                 BIC             rstatus,rstatus,#0xFF000000
3157                 PullBr
3158                 ORR             rstatus,rscratch,rstatus
3159                 TST             rstatus, #MASK_INDEX
3160                 @ INDEX set & was cleared : 16->8
3161                 MOVNE           reg_x,reg_x,LSL #8
3162                 MOVNE           reg_y,reg_y,LSL #8
3163                 TST             rstatus, #MASK_MEM
3164                 @ MEMORY set & was cleared : 16->8
3165                 MOVNE           rscratch,reg_a,LSR #24
3166                 MOVNE           reg_a,reg_a,LSL #8
3167                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3168                 S9xFixCycles
3169                 ADD2CYCLE
3170 .endm
3171 .macro          OpFAX1
3172                 PullBS          reg_x
3173                 UPDATE_ZN
3174                 ADD2CYCLE
3175 .endm
3176 .macro          OpFAX0
3177                 PullWS          reg_x
3178                 UPDATE_ZN
3179                 ADD2CYCLE
3180 .endm
3181 .macro          Op7AX1
3182                 PullBS          reg_y
3183                 UPDATE_ZN
3184                 ADD2CYCLE
3185 .endm
3186 .macro          Op7AX0
3187                 PullWS          reg_y
3188                 UPDATE_ZN
3189                 ADD2CYCLE
3190 .endm
3191
3192 /**********************************************************************************************/
3193 /* Transfer Instructions ********************************************************************* */
3194 .macro          OpAAX1M1 /*TAX8*/
3195                 MOVS            reg_x, reg_a
3196                 UPDATE_ZN
3197                 ADD1CYCLE
3198 .endm
3199 .macro          OpAAX0M1 /*TAX16*/
3200                 LDRB            reg_x, [reg_cpu_var,#RAH_ofs]
3201                 MOV             reg_x, reg_x,LSL #24
3202                 ORRS            reg_x, reg_x,reg_a, LSR #8
3203                 UPDATE_ZN
3204                 ADD1CYCLE
3205 .endm
3206 .macro          OpAAX1M0 /*TAX8*/
3207                 MOVS            reg_x, reg_a, LSL #8
3208                 UPDATE_ZN
3209                 ADD1CYCLE
3210 .endm
3211 .macro          OpAAX0M0 /*TAX16*/
3212                 MOVS            reg_x, reg_a
3213                 UPDATE_ZN
3214                 ADD1CYCLE
3215 .endm
3216 .macro          OpA8X1M1 /*TAY8*/
3217                 MOVS            reg_y, reg_a
3218                 UPDATE_ZN
3219                 ADD1CYCLE
3220 .endm
3221 .macro          OpA8X0M1 /*TAY16*/
3222                 LDRB            reg_y, [reg_cpu_var,#RAH_ofs]
3223                 MOV             reg_y, reg_y,LSL #24
3224                 ORRS            reg_y, reg_y,reg_a, LSR #8
3225                 UPDATE_ZN
3226                 ADD1CYCLE
3227 .endm
3228 .macro          OpA8X1M0 /*TAY8*/
3229                 MOVS            reg_y, reg_a, LSL #8
3230                 UPDATE_ZN
3231                 ADD1CYCLE
3232 .endm
3233 .macro          OpA8X0M0 /*TAY16*/
3234                 MOVS            reg_y, reg_a
3235                 UPDATE_ZN
3236                 ADD1CYCLE
3237 .endm
3238 .macro          Op5BM1
3239                 LDRB            rscratch, [reg_cpu_var,#RAH_ofs]
3240                 MOV             reg_d,reg_d,LSL #16
3241                 MOV             rscratch,rscratch,LSL #24
3242                 ORRS            rscratch,rscratch,reg_a, LSR #8
3243                 UPDATE_ZN
3244                 ORR             reg_d,rscratch,reg_d,LSR #16
3245                 ADD1CYCLE
3246 .endm
3247 .macro          Op5BM0
3248                 MOV             reg_d,reg_d,LSL #16
3249                 MOVS            reg_a,reg_a
3250                 UPDATE_ZN
3251                 ORR             reg_d,reg_a,reg_d,LSR #16
3252                 ADD1CYCLE
3253 .endm
3254 .macro          Op1BM1
3255                 TST             rstatus, #MASK_EMUL
3256                 MOVNE           reg_s, reg_a, LSR #24
3257                 ORRNE           reg_s, reg_s, #0x100
3258                 LDREQB          reg_s, [reg_cpu_var,#RAH_ofs]
3259                 ORREQ           reg_s, reg_s, reg_a
3260                 MOVEQ           reg_s, reg_s, ROR #24
3261                 ADD1CYCLE
3262 .endm
3263 .macro          Op1BM0
3264                 MOV             reg_s, reg_a, LSR #16
3265                 ADD1CYCLE
3266 .endm
3267 .macro          Op7BM1
3268                 MOVS            reg_a, reg_d, ASR #16
3269                 UPDATE_ZN
3270                 MOV             rscratch,reg_a,LSR #8
3271                 MOV             reg_a,reg_a, LSL #24
3272                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3273                 ADD1CYCLE
3274 .endm
3275 .macro          Op7BM0
3276                 MOVS            reg_a, reg_d, ASR #16
3277                 UPDATE_ZN
3278                 MOV             reg_a,reg_a, LSL #16
3279                 ADD1CYCLE
3280 .endm
3281 .macro          Op3BM1
3282                 MOV             rscratch,reg_s, LSR #8
3283                 MOVS            reg_a, reg_s, LSL #16
3284                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3285                 UPDATE_ZN
3286                 MOV             reg_a,reg_a, LSL #8
3287                 ADD1CYCLE
3288 .endm
3289 .macro          Op3BM0
3290                 MOVS            reg_a, reg_s, LSL #16
3291                 UPDATE_ZN
3292                 ADD1CYCLE
3293 .endm
3294 .macro          OpBAX1
3295                 MOVS            reg_x, reg_s, LSL #24
3296                 UPDATE_ZN
3297                 ADD1CYCLE
3298 .endm
3299 .macro          OpBAX0
3300                 MOVS            reg_x, reg_s, LSL #16
3301                 UPDATE_ZN
3302                 ADD1CYCLE
3303 .endm
3304 .macro          Op8AM1X1
3305                 MOVS            reg_a, reg_x
3306                 UPDATE_ZN
3307                 ADD1CYCLE
3308 .endm
3309 .macro          Op8AM1X0
3310                 MOVS            reg_a, reg_x, LSL #8
3311                 UPDATE_ZN
3312                 ADD1CYCLE
3313 .endm
3314 .macro          Op8AM0X1
3315                 MOVS            reg_a, reg_x, LSR #8
3316                 UPDATE_ZN
3317                 ADD1CYCLE
3318 .endm
3319 .macro          Op8AM0X0
3320                 MOVS            reg_a, reg_x
3321                 UPDATE_ZN
3322                 ADD1CYCLE
3323 .endm
3324 .macro          Op9AX1
3325                 MOV             reg_s, reg_x, LSR #24
3326                 TST             rstatus, #MASK_EMUL
3327                 ORRNE           reg_s, reg_s, #0x100
3328                 ADD1CYCLE
3329 .endm
3330 .macro          Op9AX0
3331                 MOV             reg_s, reg_x, LSR #16
3332                 ADD1CYCLE
3333 .endm
3334 .macro          Op9BX1
3335                 MOVS            reg_y, reg_x
3336                 UPDATE_ZN
3337                 ADD1CYCLE
3338 .endm
3339 .macro          Op9BX0
3340                 MOVS            reg_y, reg_x
3341                 UPDATE_ZN
3342                 ADD1CYCLE
3343 .endm
3344 .macro          Op98M1X1
3345                 MOVS            reg_a, reg_y
3346                 UPDATE_ZN
3347                 ADD1CYCLE
3348 .endm
3349 .macro          Op98M1X0
3350                 MOVS            reg_a, reg_y, LSL #8
3351                 UPDATE_ZN
3352                 ADD1CYCLE
3353 .endm
3354 .macro          Op98M0X1
3355                 MOVS            reg_a, reg_y, LSR #8
3356                 UPDATE_ZN
3357                 ADD1CYCLE
3358 .endm
3359 .macro          Op98M0X0
3360                 MOVS            reg_a, reg_y
3361                 UPDATE_ZN
3362                 ADD1CYCLE
3363 .endm
3364 .macro          OpBBX1
3365                 MOVS            reg_x, reg_y
3366                 UPDATE_ZN
3367                 ADD1CYCLE
3368 .endm
3369 .macro          OpBBX0
3370                 MOVS            reg_x, reg_y
3371                 UPDATE_ZN
3372                 ADD1CYCLE
3373 .endm
3374
3375 /**********************************************************************************************/
3376 /* XCE *************************************************************************************** */
3377
3378 .macro          OpFB
3379     TST         rstatus,#MASK_CARRY
3380     BEQ         1111f
3381     @ CARRY is set
3382     TST         rstatus,#MASK_EMUL
3383     BNE         1112f
3384     @ EMUL is cleared
3385     BIC         rstatus,rstatus,#(MASK_CARRY)
3386     TST         rstatus,#MASK_INDEX
3387     @ X & Y were 16bits before
3388     MOVEQ       reg_x,reg_x,LSL #8
3389     MOVEQ       reg_y,reg_y,LSL #8
3390     TST         rstatus,#MASK_MEM
3391     @ A was 16bits before
3392     @ save AH
3393     MOVEQ       rscratch,reg_a,LSR #24
3394     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3395     MOVEQ       reg_a,reg_a,LSL #8
3396     ORR         rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
3397     AND         reg_s,reg_s,#0xFF
3398     ORR         reg_s,reg_s,#0x100
3399     B           1113f
3400 1112:
3401     @ EMUL is set
3402     TST         rstatus,#MASK_INDEX
3403     @ X & Y were 16bits before
3404     MOVEQ       reg_x,reg_x,LSL #8
3405     MOVEQ       reg_y,reg_y,LSL #8
3406     TST         rstatus,#MASK_MEM
3407     @ A was 16bits before
3408     @ save AH
3409     MOVEQ       rscratch,reg_a,LSR #24
3410     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3411     MOVEQ       reg_a,reg_a,LSL #8
3412     ORR         rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
3413     AND         reg_s,reg_s,#0xFF
3414     ORR         reg_s,reg_s,#0x100
3415     B           1113f
3416 1111:
3417     @ CARRY is cleared
3418     TST         rstatus,#MASK_EMUL
3419     BEQ         1115f
3420     @ EMUL was set : X,Y & A were 8bits
3421     @ Now have to check MEMORY & INDEX for potential conversions to 16bits
3422     TST         rstatus,#MASK_INDEX
3423     @  X & Y are now 16bits
3424     MOVEQ       reg_x,reg_x,LSR #8
3425     MOVEQ       reg_y,reg_y,LSR #8
3426     TST         rstatus,#MASK_MEM
3427     @  A is now 16bits
3428     MOVEQ       reg_a,reg_a,LSR #8
3429     @ restore AH
3430     LDREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3431     ORREQ       reg_a,reg_a,rscratch,LSL #24
3432 1115:
3433     BIC         rstatus,rstatus,#(MASK_EMUL)
3434     ORR         rstatus,rstatus,#(MASK_CARRY)
3435 1113:
3436     ADD1CYCLE
3437     S9xFixCycles
3438 .endm
3439
3440 /*******************************************************************************/
3441 /* BRK *************************************************************************/
3442 .macro          Op00            /*BRK*/
3443                 MOV             rscratch,#1
3444                 STRB            rscratch,[reg_cpu_var,#BRKTriggered_ofs]
3445
3446                 TST             rstatus, #MASK_EMUL
3447                 @  EQ is flag to zero (!CheckEmu)
3448                 BNE             2001f@ elseOp00
3449                 PushBLow        reg_p_bank
3450                 SUB             rscratch, rpc, regpcbase
3451                 ADD             rscratch2, rscratch, #1
3452                 PushWLow        rscratch2
3453                 @  PackStatus
3454                 PushB           rstatus
3455                 ClearDecimal
3456                 SetIRQ
3457                 BIC             reg_p_bank, reg_p_bank, #0xFF
3458                 MOV             rscratch, #0xE6
3459                 ORR             rscratch, rscratch, #0xFF00
3460                 S9xGetWordLow
3461                 S9xSetPCBase
3462                 ADD2CYCLE
3463                 B               2002f@ endOp00
3464 2001:@ elseOp00
3465                 SUB             rscratch2, rpc, regpcbase
3466                 PushWLow        rscratch2
3467                 @  PackStatus
3468                 PushB           rstatus
3469                 ClearDecimal
3470                 SetIRQ
3471                 BIC             reg_p_bank,reg_p_bank, #0xFF
3472                 MOV             rscratch, #0xFE
3473                 ORR             rscratch, rscratch, #0xFF00
3474                 S9xGetWordLow
3475                 S9xSetPCBase
3476                 ADD1CYCLE
3477 2002:@ endOp00
3478 .endm
3479
3480
3481 /**********************************************************************************************/
3482 /* BRL ************************************************************************************** */
3483 .macro          Op82    /*BRL*/
3484                 asmRelativeLong
3485                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3486                 S9xSetPCBase
3487 .endm
3488 /**********************************************************************************************/
3489 /* IRQ *************************************************************************************** */
3490 @ void S9xOpcode_IRQ (void)
3491 .macro          S9xOpcode_IRQ   @ IRQ
3492                 TST             rstatus, #MASK_EMUL
3493                 @  EQ is flag to zero (!CheckEmu)
3494                 BNE             2121f@ elseOp02
3495                 PushBLow        reg_p_bank
3496                 SUB             rscratch2, rpc, regpcbase
3497                 PushWLow        rscratch2
3498                 @  PackStatus
3499                 PushB           rstatus
3500                 ClearDecimal
3501                 SetIRQ
3502                 BIC             reg_p_bank, reg_p_bank,#0xFF
3503                 MOV             rscratch, #0xEE
3504                 ORR             rscratch, rscratch, #0xFF00
3505                 S9xGetWordLow
3506                 S9xSetPCBase
3507                 ADD2CYCLE
3508                 B 2122f
3509 2121:@ else
3510                 SUB             rscratch2, rpc, regpcbase
3511                 PushWLow        rscratch2
3512                 @  PackStatus
3513                 PushB           rstatus
3514                 ClearDecimal
3515                 SetIRQ
3516                 BIC             reg_p_bank,reg_p_bank, #0xFF
3517                 MOV             rscratch, #0xFE
3518                 ORR             rscratch, rscratch, #0xFF00
3519                 S9xGetWordLow
3520                 S9xSetPCBase
3521                 ADD1CYCLE
3522 2122:
3523 .endm
3524
3525 /*
3526 void asm_S9xOpcode_IRQ(void)
3527 {
3528     if (!CheckEmulation())
3529     {
3530         PushB (Registers.PB);
3531         PushW (CPU.PC - CPU.PCBase);
3532         PushB (Registers.PL);
3533         ClearDecimal ();
3534         SetIRQ ();
3535
3536         Registers.PB = 0;
3537                 S9xSetPCBase (S9xGetWord (0xFFEE));
3538         CPU.Cycles += TWO_CYCLES;
3539     }
3540     else
3541     {
3542         PushW (CPU.PC - CPU.PCBase);
3543         PushB (Registers.PL);
3544         ClearDecimal ();
3545         SetIRQ ();
3546
3547         Registers.PB = 0;
3548         S9xSetPCBase (S9xGetWord (0xFFFE));
3549         CPU.Cycles += ONE_CYCLE;
3550     }
3551 }
3552 */
3553
3554 /**********************************************************************************************/
3555 /* NMI *************************************************************************************** */
3556 @ void S9xOpcode_NMI (void)
3557 .macro          S9xOpcode_NMI   @ NMI
3558                 TST             rstatus, #MASK_EMUL
3559                 @  EQ is flag to zero (!CheckEmu)
3560                 BNE             2123f@ elseOp02
3561                 PushBLow        reg_p_bank
3562                 SUB             rscratch2, rpc, regpcbase
3563                 PushWLow        rscratch2
3564                 @  PackStatus
3565                 PushB           rstatus
3566                 ClearDecimal
3567                 SetIRQ
3568                 BIC             reg_p_bank, reg_p_bank,#0xFF
3569                 MOV             rscratch, #0xEA
3570                 ORR             rscratch, rscratch, #0xFF00
3571                 S9xGetWordLow
3572                 S9xSetPCBase
3573                 ADD2CYCLE
3574                 B 2124f
3575 2123:@ else
3576                 SUB             rscratch2, rpc, regpcbase
3577                 PushWLow        rscratch2
3578                 @  PackStatus
3579                 PushB           rstatus
3580                 ClearDecimal
3581                 SetIRQ
3582                 BIC             reg_p_bank,reg_p_bank, #0xFF
3583                 MOV             rscratch, #0xFA
3584                 ORR             rscratch, rscratch, #0xFF00
3585                 S9xGetWordLow
3586                 S9xSetPCBase
3587                 ADD1CYCLE
3588 2124:
3589 .endm
3590 /*
3591 void asm_S9xOpcode_NMI(void)
3592 {
3593         if (!CheckEmulation())
3594     {
3595         PushB (Registers.PB);
3596         PushW (CPU.PC - CPU.PCBase);
3597         PushB (Registers.PL);
3598         ClearDecimal ();
3599         SetIRQ ();
3600
3601         Registers.PB = 0;
3602         S9xSetPCBase (S9xGetWord (0xFFEA));
3603         CPU.Cycles += TWO_CYCLES;
3604     }
3605     else
3606     {
3607         PushW (CPU.PC - CPU.PCBase);
3608         PushB (Registers.PL);
3609         ClearDecimal ();
3610         SetIRQ ();
3611
3612         Registers.PB = 0;
3613         S9xSetPCBase (S9xGetWord (0xFFFA));
3614         CPU.Cycles += ONE_CYCLE;
3615     }
3616 }
3617 */
3618
3619 /**********************************************************************************************/
3620 /* COP *************************************************************************************** */
3621 .macro          Op02            /*COP*/
3622                 TST             rstatus, #MASK_EMUL
3623                 @  EQ is flag to zero (!CheckEmu)
3624                 BNE             2021f@ elseOp02
3625                 PushBLow        reg_p_bank
3626                 SUB             rscratch, rpc, regpcbase
3627                 ADD             rscratch2, rscratch, #1
3628                 PushWLow        rscratch2
3629                 @  PackStatus
3630                 PushB           rstatus
3631                 ClearDecimal
3632                 SetIRQ
3633                 BIC             reg_p_bank, reg_p_bank,#0xFF
3634                 MOV             rscratch, #0xE4
3635                 ORR             rscratch, rscratch, #0xFF00
3636                 S9xGetWordLow
3637                 S9xSetPCBase
3638                 ADD2CYCLE
3639                 B 2022f@ endOp02
3640 2021:@ elseOp02
3641                 SUB             rscratch2, rpc, regpcbase
3642                 PushWLow        rscratch2
3643                 @  PackStatus
3644                 PushB           rstatus
3645                 ClearDecimal
3646                 SetIRQ
3647                 BIC             reg_p_bank,reg_p_bank, #0xFF
3648                 MOV             rscratch, #0xF4
3649                 ORR             rscratch, rscratch, #0xFF00
3650                 S9xGetWordLow
3651                 S9xSetPCBase
3652                 ADD1CYCLE
3653 2022:@ endOp02
3654 .endm
3655
3656 /**********************************************************************************************/
3657 /* JML *************************************************************************************** */
3658 .macro          OpDC
3659                 AbsoluteIndirectLong
3660                 BIC             reg_p_bank,reg_p_bank,#0xFF
3661                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3662                 S9xSetPCBase
3663                 ADD2CYCLE
3664 .endm
3665 .macro          Op5C
3666                 AbsoluteLong
3667                 BIC             reg_p_bank,reg_p_bank,#0xFF
3668                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3669                 S9xSetPCBase
3670 .endm
3671
3672 /**********************************************************************************************/
3673 /* JMP *************************************************************************************** */
3674 .macro          Op4C
3675                 Absolute
3676                 BIC             rscratch, rscratch, #0xFF0000
3677                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3678                 S9xSetPCBase
3679                 CPUShutdown
3680 .endm
3681 .macro          Op6C
3682                 AbsoluteIndirect
3683                 BIC             rscratch, rscratch, #0xFF0000
3684                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3685                 S9xSetPCBase
3686 .endm
3687 .macro          Op7C
3688                 ADD             rscratch, rscratch, reg_p_bank, LSL #16
3689                 S9xSetPCBase
3690                 ADD1CYCLE
3691 .endm
3692
3693 /**********************************************************************************************/
3694 /* JSL/RTL *********************************************************************************** */
3695 .macro          Op22
3696                 PushBlow        reg_p_bank
3697                 SUB             rscratch, rpc, regpcbase
3698                 @ SUB           rscratch2, rscratch2, #1
3699                 ADD             rscratch2, rscratch, #2
3700                 PushWlow        rscratch2
3701                 AbsoluteLong
3702                 BIC             reg_p_bank,reg_p_bank,#0xFF
3703                 ORR             reg_p_bank, reg_p_bank, rscratch, LSR #16
3704                 S9xSetPCBase
3705 .endm
3706 .macro          Op6B
3707                 PullWLow        rpc
3708                 BIC             reg_p_bank,reg_p_bank,#0xFF
3709                 PullBrLow
3710                 ORR             reg_p_bank, reg_p_bank, rscratch
3711                 ADD             rscratch, rpc, #1
3712                 BIC             rscratch, rscratch,#0xFF0000
3713                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3714                 S9xSetPCBase
3715                 ADD2CYCLE
3716 .endm
3717 /**********************************************************************************************/
3718 /* JSR/RTS *********************************************************************************** */
3719 .macro          Op20
3720                 SUB             rscratch, rpc, regpcbase
3721                 @ SUB           rscratch2, rscratch2, #1
3722                 ADD             rscratch2, rscratch, #1
3723                 PushWlow        rscratch2
3724                 Absolute
3725                 BIC             rscratch, rscratch, #0xFF0000
3726                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3727                 S9xSetPCBase
3728                 ADD1CYCLE
3729 .endm
3730 .macro          OpFCX0
3731                 SUB             rscratch, rpc, regpcbase
3732                 @ SUB           rscratch2, rscratch2, #1
3733                 ADD             rscratch2, rscratch, #1
3734                 PushWlow        rscratch2
3735                 AbsoluteIndexedIndirectX0
3736                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3737                 S9xSetPCBase
3738                 ADD1CYCLE
3739 .endm
3740 .macro          OpFCX1
3741                 SUB             rscratch, rpc, regpcbase
3742                 @ SUB           rscratch2, rscratch2, #1
3743                 ADD             rscratch2, rscratch, #1
3744                 PushWlow        rscratch2
3745                 AbsoluteIndexedIndirectX1
3746                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3747                 S9xSetPCBase
3748                 ADD1CYCLE
3749 .endm
3750 .macro          Op60
3751                 PullWLow        rpc
3752                 ADD             rscratch, rpc, #1
3753                 BIC             rscratch, rscratch,#0x10000
3754                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3755                 S9xSetPCBase
3756                 ADD3CYCLE
3757 .endm
3758
3759 /**********************************************************************************************/
3760 /* MVN/MVP *********************************************************************************** */
3761 .macro          Op54X1M1
3762                 @ Save RegStatus = reg_d_bank >> 24
3763                 MOV             rscratch, reg_d_bank, LSR #16
3764                 LDRB            reg_d_bank    , [rpc], #1
3765                 LDRB            rscratch2    , [rpc], #1
3766                 @ Restore RegStatus = reg_d_bank >> 24
3767                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3768                 MOV             rscratch    , reg_x, LSR #24
3769                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3770                 S9xGetByteLow
3771                 MOV             rscratch2, rscratch
3772                 MOV             rscratch   , reg_y, LSR #24
3773                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3774                 S9xSetByteLow   rscratch2
3775                 @ load 16bits A
3776                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3777                 MOV             reg_a,reg_a,LSR #8
3778                 ORR             reg_a,reg_a,rscratch, LSL #24
3779                 ADD             reg_x, reg_x, #0x01000000
3780                 SUB             reg_a, reg_a, #0x00010000
3781                 ADD             reg_y, reg_y, #0x01000000
3782                 CMP             reg_a, #0xFFFF0000
3783                 SUBNE           rpc, rpc, #3
3784                 @ update AH
3785                 MOV             rscratch, reg_a, LSR #24
3786                 MOV             reg_a,reg_a,LSL #8
3787                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3788                 ADD2CYCLE2MEM
3789 .endm
3790 .macro          Op54X1M0
3791                 @ Save RegStatus = reg_d_bank >> 24
3792                 MOV             rscratch, reg_d_bank, LSR #16
3793                 LDRB            reg_d_bank    , [rpc], #1
3794                 LDRB            rscratch2    , [rpc], #1
3795                 @ Restore RegStatus = reg_d_bank >> 24
3796                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3797                 MOV             rscratch    , reg_x, LSR #24
3798                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3799                 S9xGetByteLow
3800                 MOV             rscratch2, rscratch
3801                 MOV             rscratch   , reg_y, LSR #24
3802                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3803                 S9xSetByteLow   rscratch2
3804                 ADD             reg_x, reg_x, #0x01000000
3805                 SUB             reg_a, reg_a, #0x00010000
3806                 ADD             reg_y, reg_y, #0x01000000
3807                 CMP             reg_a, #0xFFFF0000
3808                 SUBNE           rpc, rpc, #3
3809                 ADD2CYCLE2MEM
3810 .endm
3811 .macro          Op54X0M1
3812                 @ Save RegStatus = reg_d_bank >> 24
3813                 MOV             rscratch, reg_d_bank, LSR #16
3814                 LDRB            reg_d_bank    , [rpc], #1
3815                 LDRB            rscratch2    , [rpc], #1
3816                 @ Restore RegStatus = reg_d_bank >> 24
3817                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3818                 MOV             rscratch    , reg_x, LSR #16
3819                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3820                 S9xGetByteLow
3821                 MOV             rscratch2, rscratch
3822                 MOV             rscratch   , reg_y, LSR #16
3823                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3824                 S9xSetByteLow   rscratch2
3825                 @ load 16bits A
3826                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3827                 MOV             reg_a,reg_a,LSR #8
3828                 ORR             reg_a,reg_a,rscratch, LSL #24
3829                 ADD             reg_x, reg_x, #0x00010000
3830                 SUB             reg_a, reg_a, #0x00010000
3831                 ADD             reg_y, reg_y, #0x00010000
3832                 CMP             reg_a, #0xFFFF0000
3833                 SUBNE           rpc, rpc, #3
3834                 @ update AH
3835                 MOV             rscratch, reg_a, LSR #24
3836                 MOV             reg_a,reg_a,LSL #8
3837                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3838                 ADD2CYCLE2MEM
3839 .endm
3840 .macro          Op54X0M0
3841                 @ Save RegStatus = reg_d_bank >> 24
3842                 MOV             rscratch, reg_d_bank, LSR #16
3843                 LDRB            reg_d_bank    , [rpc], #1
3844                 LDRB            rscratch2    , [rpc], #1
3845                 @ Restore RegStatus = reg_d_bank >> 24
3846                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3847                 MOV             rscratch    , reg_x, LSR #16
3848                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3849                 S9xGetByteLow
3850                 MOV             rscratch2, rscratch
3851                 MOV             rscratch   , reg_y, LSR #16
3852                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3853                 S9xSetByteLow   rscratch2
3854                 ADD             reg_x, reg_x, #0x00010000
3855                 SUB             reg_a, reg_a, #0x00010000
3856                 ADD             reg_y, reg_y, #0x00010000
3857                 CMP             reg_a, #0xFFFF0000
3858                 SUBNE           rpc, rpc, #3
3859                 ADD2CYCLE2MEM
3860 .endm
3861
3862 .macro          Op44X1M1
3863                 @ Save RegStatus = reg_d_bank >> 24
3864                 MOV             rscratch, reg_d_bank, LSR #16
3865                 LDRB            reg_d_bank    , [rpc], #1
3866                 LDRB            rscratch2    , [rpc], #1
3867                 @ Restore RegStatus = reg_d_bank >> 24
3868                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3869                 MOV             rscratch    , reg_x, LSR #24
3870                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3871                 S9xGetByteLow
3872                 MOV             rscratch2, rscratch
3873                 MOV             rscratch   , reg_y, LSR #24
3874                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3875                 S9xSetByteLow   rscratch2
3876                 @ load 16bits A
3877                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3878                 MOV             reg_a,reg_a,LSR #8
3879                 ORR             reg_a,reg_a,rscratch, LSL #24
3880                 SUB             reg_x, reg_x, #0x01000000
3881                 SUB             reg_a, reg_a, #0x00010000
3882                 SUB             reg_y, reg_y, #0x01000000
3883                 CMP             reg_a, #0xFFFF0000
3884                 SUBNE           rpc, rpc, #3
3885                 @ update AH
3886                 MOV             rscratch, reg_a, LSR #24
3887                 MOV             reg_a,reg_a,LSL #8
3888                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3889                 ADD2CYCLE2MEM
3890 .endm
3891 .macro          Op44X1M0
3892                 @ Save RegStatus = reg_d_bank >> 24
3893                 MOV             rscratch, reg_d_bank, LSR #16
3894                 LDRB            reg_d_bank    , [rpc], #1
3895                 LDRB            rscratch2    , [rpc], #1
3896                 @ Restore RegStatus = reg_d_bank >> 24
3897                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3898                 MOV             rscratch    , reg_x, LSR #24
3899                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3900                 S9xGetByteLow
3901                 MOV             rscratch2, rscratch
3902                 MOV             rscratch   , reg_y, LSR #24
3903                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3904                 S9xSetByteLow   rscratch2
3905                 SUB             reg_x, reg_x, #0x01000000
3906                 SUB             reg_a, reg_a, #0x00010000
3907                 SUB             reg_y, reg_y, #0x01000000
3908                 CMP             reg_a, #0xFFFF0000
3909                 SUBNE           rpc, rpc, #3
3910                 ADD2CYCLE2MEM
3911 .endm
3912 .macro          Op44X0M1
3913                 @ Save RegStatus = reg_d_bank >> 24
3914                 MOV             rscratch, reg_d_bank, LSR #16
3915                 LDRB            reg_d_bank    , [rpc], #1
3916                 LDRB            rscratch2    , [rpc], #1
3917                 @ Restore RegStatus = reg_d_bank >> 24
3918                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3919                 MOV             rscratch    , reg_x, LSR #16
3920                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3921                 S9xGetByteLow
3922                 MOV             rscratch2, rscratch
3923                 MOV             rscratch   , reg_y, LSR #16
3924                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3925                 S9xSetByteLow   rscratch2
3926                 @ load 16bits A
3927                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3928                 MOV             reg_a,reg_a,LSR #8
3929                 ORR             reg_a,reg_a,rscratch, LSL #24
3930                 SUB             reg_x, reg_x, #0x00010000
3931                 SUB             reg_a, reg_a, #0x00010000
3932                 SUB             reg_y, reg_y, #0x00010000
3933                 CMP             reg_a, #0xFFFF0000
3934                 SUBNE           rpc, rpc, #3
3935                 @ update AH
3936                 MOV             rscratch, reg_a, LSR #24
3937                 MOV             reg_a,reg_a,LSL #8
3938                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3939                 ADD2CYCLE2MEM
3940 .endm
3941 .macro          Op44X0M0
3942                 @ Save RegStatus = reg_d_bank >> 24
3943                 MOV             rscratch, reg_d_bank, LSR #16
3944                 LDRB            reg_d_bank    , [rpc], #1
3945                 LDRB            rscratch2    , [rpc], #1
3946                 @ Restore RegStatus = reg_d_bank >> 24
3947                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3948                 MOV             rscratch    , reg_x, LSR #16
3949                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3950                 S9xGetByteLow
3951                 MOV             rscratch2, rscratch
3952                 MOV             rscratch   , reg_y, LSR #16
3953                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3954                 S9xSetByteLow   rscratch2
3955                 SUB             reg_x, reg_x, #0x00010000
3956                 SUB             reg_a, reg_a, #0x00010000
3957                 SUB             reg_y, reg_y, #0x00010000
3958                 CMP             reg_a, #0xFFFF0000
3959                 SUBNE           rpc, rpc, #3
3960                 ADD2CYCLE2MEM
3961 .endm
3962
3963 /**********************************************************************************************/
3964 /* REP/SEP *********************************************************************************** */
3965 .macro          OpC2
3966                 @  status&=~(*rpc++);
3967                 @  so possible changes are :
3968                 @  INDEX = 1 -> 0  : X,Y 8bits -> 16bits
3969                 @  MEM = 1 -> 0 : A 8bits -> 16bits
3970                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
3971                 MOV             rscratch3, rstatus
3972                 LDRB            rscratch, [rpc], #1
3973                 MVN             rscratch, rscratch
3974                 AND             rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
3975                 TST             rstatus,#MASK_EMUL
3976                 BEQ             1111f
3977                 @ emulation mode on : no changes since it was on before opcode
3978                 @ just be sure to reset MEM & INDEX accordingly
3979                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
3980                 B               1112f
3981 1111:
3982                 @ NOT in Emulation mode, check INDEX & MEMORY bits
3983                 @ Now check INDEX
3984                 TST             rscratch3,#MASK_INDEX
3985                 BEQ             1113f
3986                 @  X & Y were 8bit before
3987                 TST             rstatus,#MASK_INDEX
3988                 BNE             1113f
3989                 @  X & Y are now 16bits
3990                 MOV             reg_x,reg_x,LSR #8
3991                 MOV             reg_y,reg_y,LSR #8
3992 1113:           @ X & Y still in 16bits
3993                 @ Now check MEMORY
3994                 TST             rscratch3,#MASK_MEM
3995                 BEQ             1112f
3996                 @  A was 8bit before
3997                 TST             rstatus,#MASK_MEM
3998                 BNE             1112f
3999                 @  A is now 16bits
4000                 MOV             reg_a,reg_a,LSR #8
4001                 @ restore AH
4002                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4003                 ORREQ           reg_a,reg_a,rscratch,LSL #24
4004 1112:
4005                 S9xFixCycles
4006                 ADD1CYCLE1MEM
4007 .endm
4008 .macro          OpE2
4009                 @  status|=*rpc++;
4010                 @  so possible changes are :
4011                 @  INDEX = 0 -> 1  : X,Y 16bits -> 8bits
4012                 @  MEM = 0 -> 1 : A 16bits -> 8bits
4013                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
4014                 MOV             rscratch3, rstatus
4015                 LDRB            rscratch, [rpc], #1
4016                 ORR             rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
4017                 TST             rstatus,#MASK_EMUL
4018                 BEQ             10111f
4019                 @ emulation mode on : no changes sinc eit was on before opcode
4020                 @ just be sure to have mem & index set accordingly
4021                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
4022                 B               10112f
4023 10111:
4024                 @ NOT in Emulation mode, check INDEX & MEMORY bits
4025                 @ Now check INDEX
4026                 TST             rscratch3,#MASK_INDEX
4027                 BNE             10113f
4028                 @  X & Y were 16bit before
4029                 TST             rstatus,#MASK_INDEX
4030                 BEQ             10113f
4031                 @  X & Y are now 8bits
4032                 MOV             reg_x,reg_x,LSL #8
4033                 MOV             reg_y,reg_y,LSL #8
4034 10113:          @ X & Y still in 16bits
4035                 @ Now check MEMORY
4036                 TST             rscratch3,#MASK_MEM
4037                 BNE             10112f
4038                 @  A was 16bit before
4039                 TST             rstatus,#MASK_MEM
4040                 BEQ             10112f
4041                 @  A is now 8bits
4042                 @  save AH
4043                 MOV             rscratch,reg_a,LSR #24
4044                 MOV             reg_a,reg_a,LSL #8
4045                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
4046 10112:
4047                 S9xFixCycles
4048                 ADD1CYCLE1MEM
4049 .endm
4050
4051 /**********************************************************************************************/
4052 /* XBA *************************************************************************************** */
4053 .macro          OpEBM1
4054                 @ A is 8bits
4055                 ADD             rscratch,reg_cpu_var,#RAH_ofs
4056                 MOV             reg_a,reg_a, LSR #24
4057                 SWPB            reg_a,reg_a,[rscratch]
4058                 MOVS            reg_a,reg_a, LSL #24
4059                 UPDATE_ZN
4060                 ADD2CYCLE
4061 .endm
4062 .macro          OpEBM0
4063                 @ A is 16bits
4064                 MOV             rscratch, reg_a, ROR #24 @  ll0000hh
4065                 ORR             rscratch, rscratch, reg_a, LSR #8@  ll0000hh + 00hhll00 -> llhhllhh
4066                 MOV             reg_a, rscratch, LSL #16@  llhhllhh -> llhh0000
4067                 MOVS            rscratch,rscratch,LSL #24 @ to set Z & N flags with AL
4068                 UPDATE_ZN
4069                 ADD2CYCLE
4070 .endm
4071
4072
4073 /**********************************************************************************************/
4074 /* RTI *************************************************************************************** */
4075 .macro          Op40X1M1
4076                 @ INDEX set, MEMORY set
4077                 BIC             rstatus,rstatus,#0xFF000000
4078                 PullBr
4079                 ORR             rstatus,rscratch,rstatus
4080                 PullWlow        rpc
4081                 TST             rstatus, #MASK_EMUL
4082                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4083                 BNE             2401f
4084                 PullBrLow
4085                 BIC             reg_p_bank,reg_p_bank,#0xFF
4086                 ORR             reg_p_bank,reg_p_bank,rscratch
4087 2401:
4088                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4089                 S9xSetPCBase
4090                 TST             rstatus, #MASK_INDEX
4091                 @ INDEX cleared & was set : 8->16
4092                 MOVEQ           reg_x,reg_x,LSR #8
4093                 MOVEQ           reg_y,reg_y,LSR #8
4094                 TST             rstatus, #MASK_MEM
4095                 @ MEMORY cleared & was set : 8->16
4096                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4097                 MOVEQ           reg_a,reg_a,LSR #8
4098                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4099                 ADD2CYCLE
4100                 S9xFixCycles
4101 .endm
4102 .macro          Op40X0M1
4103                 @ INDEX cleared, MEMORY set
4104                 BIC             rstatus,rstatus,#0xFF000000
4105                 PullBr
4106                 ORR             rstatus,rscratch,rstatus
4107                 PullWlow        rpc
4108                 TST             rstatus, #MASK_EMUL
4109                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4110                 BNE             2401f
4111                 PullBrLow
4112                 BIC             reg_p_bank,reg_p_bank,#0xFF
4113                 ORR             reg_p_bank,reg_p_bank,rscratch
4114 2401:
4115                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4116                 S9xSetPCBase
4117                 TST             rstatus, #MASK_INDEX
4118                 @ INDEX set & was cleared : 16->8
4119                 MOVNE           reg_x,reg_x,LSL #8
4120                 MOVNE           reg_y,reg_y,LSL #8
4121                 TST             rstatus, #MASK_MEM
4122                 @ MEMORY cleared & was set : 8->16
4123                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4124                 MOVEQ           reg_a,reg_a,LSR #8
4125                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4126                 ADD2CYCLE
4127                 S9xFixCycles
4128 .endm
4129 .macro          Op40X1M0
4130                 @ INDEX set, MEMORY cleared
4131                 BIC             rstatus,rstatus,#0xFF000000
4132                 PullBr
4133                 ORR             rstatus,rscratch,rstatus
4134                 PullWlow        rpc
4135                 TST             rstatus, #MASK_EMUL
4136                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4137                 BNE             2401f
4138                 PullBrLow
4139                 BIC             reg_p_bank,reg_p_bank,#0xFF
4140                 ORR             reg_p_bank,reg_p_bank,rscratch
4141 2401:
4142                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4143                 S9xSetPCBase
4144                 TST             rstatus, #MASK_INDEX
4145                 @ INDEX cleared & was set : 8->16
4146                 MOVEQ           reg_x,reg_x,LSR #8
4147                 MOVEQ           reg_y,reg_y,LSR #8
4148                 TST             rstatus, #MASK_MEM
4149                 @ MEMORY set & was cleared : 16->8
4150                 MOVNE           rscratch,reg_a,LSR #24
4151                 MOVNE           reg_a,reg_a,LSL #8
4152                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4153                 ADD2CYCLE
4154                 S9xFixCycles
4155 .endm
4156 .macro          Op40X0M0
4157                 @ INDEX cleared, MEMORY cleared
4158                 BIC             rstatus,rstatus,#0xFF000000
4159                 PullBr
4160                 ORR             rstatus,rscratch,rstatus
4161                 PullWlow        rpc
4162                 TST             rstatus, #MASK_EMUL
4163                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4164                 BNE             2401f
4165                 PullBrLow
4166                 BIC             reg_p_bank,reg_p_bank,#0xFF
4167                 ORR             reg_p_bank,reg_p_bank,rscratch
4168 2401:
4169                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4170                 S9xSetPCBase
4171                 TST             rstatus, #MASK_INDEX
4172                 @ INDEX set & was cleared : 16->8
4173                 MOVNE           reg_x,reg_x,LSL #8
4174                 MOVNE           reg_y,reg_y,LSL #8
4175                 TST             rstatus, #MASK_MEM
4176                 @ MEMORY set & was cleared : 16->8
4177                 @ MEMORY set & was cleared : 16->8
4178                 MOVNE           rscratch,reg_a,LSR #24
4179                 MOVNE           reg_a,reg_a,LSL #8
4180                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4181                 ADD2CYCLE
4182                 S9xFixCycles
4183 .endm
4184
4185
4186 /**********************************************************************************************/
4187 /* STP/WAI/DB ******************************************************************************** */
4188 @  WAI
4189 .macro          OpCB    /*WAI*/
4190         LDRB            rscratch,[reg_cpu_var,#IRQActive_ofs]
4191         MOVS            rscratch,rscratch
4192         @ (CPU.IRQActive)
4193         ADD2CYCLENE
4194         BNE             1234f
4195 /*
4196         CPU.WaitingForInterrupt = TRUE;
4197         CPU.PC--;
4198 */
4199         MOV             rscratch,#1
4200         SUB             rpc,rpc,#1
4201 /*
4202             CPU.Cycles = CPU.NextEvent;
4203 */
4204         STRB            rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs]
4205         LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
4206 /*
4207         if (IAPU.APUExecuting)
4208             {
4209                 ICPU.CPUExecuting = FALSE;
4210                 do
4211                 {
4212                     APU_EXECUTE1 ();
4213                 } while (APU.Cycles < CPU.NextEvent);
4214                 ICPU.CPUExecuting = TRUE;
4215             }
4216 */
4217         LDRB            rscratch,[reg_cpu_var,#APUExecuting_ofs]
4218         MOVS            rscratch,rscratch
4219         BEQ             1234f
4220         asmAPU_EXECUTE2
4221
4222 1234:
4223 .endm
4224 .macro          OpDB    /*STP*/
4225                 SUB     rpc,rpc,#1
4226                 @ CPU.Flags |= DEBUG_MODE_FLAG;
4227 .endm
4228 .macro          Op42   /*Reserved Snes9X: SNESAdvance SpeedHack */
4229 @ Explanation: this is a reserved opcode turned into special "idle"/hlt opcode.
4230 @ This means we should do an hblank now.
4231 /*-
4232         CPU.Cycles = CPU.NextEvent;
4233 */      ldr reg_cycles, [reg_cpu_var,#NextEvent_ofs]
4234 @ Now execute the shadowed branch
4235 @ Equivalent to "asmRelative":
4236         ADD1MEM
4237         ldrb rscratch, [rpc], #1
4238         and rscratch2, rscratch, #0xf0  @branch type
4239         orr rscratch, rscratch, #0xf0   @branch dest (always negative, so sign ext)
4240         sxtb rscratch, rscratch
4241         add rscratch, rscratch, rpc
4242         sub rscratch, rscratch, regpcbase
4243         uxth rscratch, rscratch
4244 @ TODO: Do something with rscratch2 before BranchCheck clobbers it.
4245 @ Currently hardcoded to BEQ
4246         BranchCheck2
4247                 TST             rstatus, #MASK_ZERO
4248                 BEQ             1111f
4249                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
4250                 ADD1CYCLE
4251                 CPUShutdown
4252 .endm
4253
4254 /**********************************************************************************************/
4255 /* AND ******************************************************************************** */
4256 .macro          Op29M1
4257                 LDRB    rscratch    , [rpc], #1
4258                 ANDS    reg_a    , reg_a,       rscratch, LSL #24
4259                 UPDATE_ZN
4260                 ADD1MEM
4261 .endm
4262 .macro          Op29M0
4263                 LDRB    rscratch2  , [rpc,#1]
4264                 LDRB    rscratch   , [rpc], #2
4265                 ORR     rscratch, rscratch, rscratch2, LSL #8
4266                 ANDS    reg_a    , reg_a,       rscratch, LSL #16
4267                 UPDATE_ZN
4268                 ADD2MEM
4269 .endm
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285 /**********************************************************************************************/
4286 /* EOR ******************************************************************************** */
4287 .macro          Op49M0
4288                 LDRB    rscratch2 , [rpc, #1]
4289                 LDRB    rscratch , [rpc], #2
4290                 ORR     rscratch, rscratch, rscratch2,LSL #8
4291                 EORS    reg_a, reg_a, rscratch,LSL #16
4292                 UPDATE_ZN
4293                 ADD2MEM
4294 .endm
4295
4296
4297 .macro          Op49M1
4298                 LDRB    rscratch , [rpc], #1
4299                 EORS    reg_a, reg_a, rscratch,LSL #24
4300                 UPDATE_ZN
4301                 ADD1MEM
4302 .endm
4303
4304
4305 /**********************************************************************************************/
4306 /* STA *************************************************************************************** */
4307 .macro          Op81M1
4308                 STA8
4309                 @ TST           rstatus, #MASK_INDEX
4310                 @ ADD1CYCLENE
4311 .endm
4312 .macro          Op81M0
4313                 STA16
4314                 @ TST rstatus, #MASK_INDEX
4315                 @ ADD1CYCLENE
4316 .endm
4317
4318
4319 /**********************************************************************************************/
4320 /* BIT *************************************************************************************** */
4321 .macro          Op89M1
4322                 LDRB    rscratch , [rpc], #1
4323                 TST     reg_a, rscratch, LSL #24
4324                 UPDATE_Z
4325                 ADD1MEM
4326 .endm
4327 .macro          Op89M0
4328                 LDRB    rscratch2 , [rpc, #1]
4329                 LDRB    rscratch , [rpc], #2
4330                 ORR     rscratch, rscratch, rscratch2, LSL #8
4331                 TST     reg_a, rscratch, LSL #16
4332                 UPDATE_Z
4333                 ADD2MEM
4334 .endm
4335
4336
4337
4338
4339
4340
4341 /**********************************************************************************************/
4342 /* LDY *************************************************************************************** */
4343 .macro          OpA0X1
4344                 LDRB    rscratch , [rpc], #1
4345                 MOVS    reg_y, rscratch, LSL #24
4346                 UPDATE_ZN
4347                 ADD1MEM
4348 .endm
4349 .macro          OpA0X0
4350                 LDRB    rscratch2 , [rpc, #1]
4351                 LDRB    rscratch , [rpc], #2
4352                 ORR     rscratch, rscratch, rscratch2, LSL #8
4353                 MOVS    reg_y, rscratch, LSL #16
4354                 UPDATE_ZN
4355                 ADD2MEM
4356 .endm
4357
4358 /**********************************************************************************************/
4359 /* LDX *************************************************************************************** */
4360 .macro          OpA2X1
4361                 LDRB    rscratch , [rpc], #1
4362                 MOVS    reg_x, rscratch, LSL #24
4363                 UPDATE_ZN
4364                 ADD1MEM
4365 .endm
4366 .macro          OpA2X0
4367                 LDRB    rscratch2 , [rpc, #1]
4368                 LDRB    rscratch , [rpc], #2
4369                 ORR     rscratch, rscratch, rscratch2, LSL #8
4370                 MOVS    reg_x, rscratch, LSL #16
4371                 UPDATE_ZN
4372                 ADD2MEM
4373 .endm
4374
4375 /**********************************************************************************************/
4376 /* LDA *************************************************************************************** */
4377 .macro          OpA9M1
4378                 LDRB    rscratch , [rpc], #1
4379                 MOVS    reg_a, rscratch, LSL #24
4380                 UPDATE_ZN
4381                 ADD1MEM
4382 .endm
4383 .macro          OpA9M0
4384                 LDRB    rscratch2 , [rpc, #1]
4385                 LDRB    rscratch , [rpc], #2
4386                 ORR     rscratch, rscratch, rscratch2, LSL #8
4387                 MOVS    reg_a, rscratch, LSL #16
4388                 UPDATE_ZN
4389                 ADD2MEM
4390 .endm
4391
4392 /**********************************************************************************************/
4393 /* CMY *************************************************************************************** */
4394 .macro          OpC0X1
4395                 LDRB    rscratch    , [rpc], #1
4396                 SUBS    rscratch2   , reg_y , rscratch, LSL #24
4397                 BICCC   rstatus, rstatus, #MASK_CARRY
4398                 ORRCS   rstatus, rstatus, #MASK_CARRY
4399                 UPDATE_ZN
4400                 ADD1MEM
4401 .endm
4402 .macro          OpC0X0
4403                 LDRB    rscratch2   , [rpc, #1]
4404                 LDRB    rscratch   , [rpc], #2
4405                 ORR     rscratch, rscratch, rscratch2, LSL #8
4406                 SUBS    rscratch2   , reg_y, rscratch, LSL #16
4407                 BICCC   rstatus, rstatus, #MASK_CARRY
4408                 ORRCS   rstatus, rstatus, #MASK_CARRY
4409                 UPDATE_ZN
4410                 ADD2MEM
4411 .endm
4412
4413
4414
4415
4416
4417 /**********************************************************************************************/
4418 /* CMP *************************************************************************************** */
4419 .macro          OpC9M1
4420                 LDRB    rscratch    , [rpc], #1
4421                 SUBS    rscratch2   , reg_a , rscratch, LSL #24
4422                 BICCC   rstatus, rstatus, #MASK_CARRY
4423                 ORRCS   rstatus, rstatus, #MASK_CARRY
4424                 UPDATE_ZN
4425                 ADD1MEM
4426 .endm
4427 .macro          OpC9M0
4428                 LDRB    rscratch2   , [rpc,#1]
4429                 LDRB    rscratch   , [rpc], #2
4430                 ORR     rscratch, rscratch, rscratch2, LSL #8
4431                 SUBS    rscratch2   , reg_a, rscratch, LSL #16
4432                 BICCC   rstatus, rstatus, #MASK_CARRY
4433                 ORRCS   rstatus, rstatus, #MASK_CARRY
4434                 UPDATE_ZN
4435                 ADD2MEM
4436 .endm
4437
4438 /**********************************************************************************************/
4439 /* CMX *************************************************************************************** */
4440 .macro          OpE0X1
4441                 LDRB    rscratch    , [rpc], #1
4442                 SUBS    rscratch2   , reg_x , rscratch, LSL #24
4443                 BICCC   rstatus, rstatus, #MASK_CARRY
4444                 ORRCS   rstatus, rstatus, #MASK_CARRY
4445                 UPDATE_ZN
4446                 ADD1MEM
4447 .endm
4448 .macro          OpE0X0
4449                 LDRB    rscratch2   , [rpc,#1]
4450                 LDRB    rscratch   , [rpc], #2
4451                 ORR     rscratch, rscratch, rscratch2, LSL #8
4452                 SUBS    rscratch2   , reg_x, rscratch, LSL #16
4453                 BICCC   rstatus, rstatus, #MASK_CARRY
4454                 ORRCS   rstatus, rstatus, #MASK_CARRY
4455                 UPDATE_ZN
4456                 ADD2MEM
4457 .endm
4458
4459
4460 /****************************************************************
4461         GLOBAL
4462 ****************************************************************/
4463 .global asmMainLoop
4464 .type   asmMainLoop, function
4465
4466 @ void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
4467 asmMainLoop:
4468         @ save registers
4469         STMFD           R13!,{R4-R11, LR}
4470         @ init pointer to CPUvar structure
4471         MOV             reg_cpu_var,R0
4472         @ init registers
4473         LOAD_REGS
4474         @ get cpu mode from flag and init jump table
4475         S9xFixCycles
4476
4477 mainLoop:
4478         @ APU Execute
4479         asmAPU_EXECUTE
4480
4481         @ Test Flags
4482         LDR             rscratch,[reg_cpu_var,#Flags_ofs]
4483         MOVS            rscratch,rscratch
4484         BNE             CPUFlags_set    @ If flags => check for irq/nmi/scan_keys...
4485
4486         EXEC_OP                                         @ Execute next opcode
4487
4488 CPUFlags_set:   @ Check flags (!=0)
4489                 TST     rscratch,#NMI_FLAG              @ Check NMI
4490                 BEQ     CPUFlagsNMI_FLAG_cleared
4491                 LDR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4492                 SUBS    rscratch2,rscratch2,#1
4493                 STR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4494                 BNE     CPUFlagsNMI_FLAG_cleared
4495                 BIC     rscratch,rscratch,#NMI_FLAG
4496                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4497                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4498                 MOVS    rscratch2,rscratch2
4499                 BEQ     NotCPUaitingForInterruptNMI
4500                 MOV     rscratch2,#0
4501                 ADD     rpc,rpc,#1
4502                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4503 NotCPUaitingForInterruptNMI:
4504                 S9xOpcode_NMI
4505                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4506 CPUFlagsNMI_FLAG_cleared:
4507                 TST     rscratch,#IRQ_PENDING_FLAG   @ Check IRQ_PENDING_FLAG
4508                 BEQ     CPUFlagsIRQ_PENDING_FLAG_cleared
4509                 LDR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4510                 MOVS    rscratch2,rscratch2
4511                 BNE     CPUIRQCycleCount_NotZero
4512                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4513                 MOVS    rscratch2,rscratch2
4514                 BEQ     NotCPUaitingForInterruptIRQ
4515                 MOV     rscratch2,#0
4516                 ADD     rpc,rpc,#1
4517                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4518 NotCPUaitingForInterruptIRQ:
4519                 LDRB    rscratch2,[reg_cpu_var,#IRQActive_ofs]
4520                 MOVS    rscratch2,rscratch2
4521                 BEQ     CPUIRQActive_cleared
4522                 TST     rstatus,#MASK_IRQ
4523                 BNE     CPUFlagsIRQ_PENDING_FLAG_cleared
4524                 S9xOpcode_IRQ
4525                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4526                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4527 CPUIRQActive_cleared:
4528                 BIC     rscratch,rscratch,#IRQ_PENDING_FLAG
4529                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4530                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4531 CPUIRQCycleCount_NotZero:
4532                 SUB     rscratch2,rscratch2,#1
4533                 STR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4534 CPUFlagsIRQ_PENDING_FLAG_cleared:
4535
4536                 TST     rscratch,#SCAN_KEYS_FLAG   @ Check SCAN_KEYS_FLAG
4537                 BNE     endmainLoop
4538
4539         EXEC_OP @ Execute next opcode
4540
4541 endmainLoop:
4542     /*Registers.PC = CPU.PC - CPU.PCBase;
4543     S9xPackStatus ();
4544     APURegisters.PC = IAPU.PC - IAPU.RAM;
4545     S9xAPUPackStatus ();
4546
4547     if (CPU.Flags & SCAN_KEYS_FLAG)
4548     {
4549             S9xSyncSpeed ();
4550         CPU.Flags &= ~SCAN_KEYS_FLAG;
4551     }   */
4552 /********end*/
4553         SAVE_REGS
4554         LDMFD           R13!,{R4-R11, LR}
4555         BX LR
4556 .pool
4557 .size asmMainLoop, asmMainLoop-.
4558
4559 @ void test_opcode(struct asm_cpu_var *asm_var);
4560 test_opcode:
4561         @ save registers
4562         STMFD           R13!,{R4-R11,LR}
4563         @ init pointer to CPUvar structure
4564         MOV             reg_cpu_var,R0
4565         @ init registers
4566         LOAD_REGS
4567         @ get cpu mode from flag and init jump table
4568         S9xFixCycles
4569
4570         EXEC_OP
4571 .pool
4572
4573 /*****************************************************************
4574        ASM CODE
4575 *****************************************************************/
4576
4577
4578 jumptable1:             .long   Op00mod1
4579                         .long   Op01M1mod1
4580                         .long   Op02mod1
4581                         .long   Op03M1mod1
4582                         .long   Op04M1mod1
4583                         .long   Op05M1mod1
4584                         .long   Op06M1mod1
4585                         .long   Op07M1mod1
4586                         .long   Op08mod1
4587                         .long   Op09M1mod1
4588                         .long   Op0AM1mod1
4589                         .long   Op0Bmod1
4590                         .long   Op0CM1mod1
4591                         .long   Op0DM1mod1
4592                         .long   Op0EM1mod1
4593                         .long   Op0FM1mod1
4594                         .long   Op10mod1
4595                         .long   Op11M1mod1
4596                         .long   Op12M1mod1
4597                         .long   Op13M1mod1
4598                         .long   Op14M1mod1
4599                         .long   Op15M1mod1
4600                         .long   Op16M1mod1
4601                         .long   Op17M1mod1
4602                         .long   Op18mod1
4603                         .long   Op19M1mod1
4604                         .long   Op1AM1mod1
4605                         .long   Op1Bmod1
4606                         .long   Op1CM1mod1
4607                         .long   Op1DM1mod1
4608                         .long   Op1EM1mod1
4609                         .long   Op1FM1mod1
4610                         .long   Op20mod1
4611                         .long   Op21M1mod1
4612                         .long   Op22mod1
4613                         .long   Op23M1mod1
4614                         .long   Op24M1mod1
4615                         .long   Op25M1mod1
4616                         .long   Op26M1mod1
4617                         .long   Op27M1mod1
4618                         .long   Op28mod1
4619                         .long   Op29M1mod1
4620                         .long   Op2AM1mod1
4621                         .long   Op2Bmod1
4622                         .long   Op2CM1mod1
4623                         .long   Op2DM1mod1
4624                         .long   Op2EM1mod1
4625                         .long   Op2FM1mod1
4626                         .long   Op30mod1
4627                         .long   Op31M1mod1
4628                         .long   Op32M1mod1
4629                         .long   Op33M1mod1
4630                         .long   Op34M1mod1
4631                         .long   Op35M1mod1
4632                         .long   Op36M1mod1
4633                         .long   Op37M1mod1
4634                         .long   Op38mod1
4635                         .long   Op39M1mod1
4636                         .long   Op3AM1mod1
4637                         .long   Op3Bmod1
4638                         .long   Op3CM1mod1
4639                         .long   Op3DM1mod1
4640                         .long   Op3EM1mod1
4641                         .long   Op3FM1mod1
4642                         .long   Op40mod1
4643                         .long   Op41M1mod1
4644                         .long   Op42mod1
4645                         .long   Op43M1mod1
4646                         .long   Op44X1mod1
4647                         .long   Op45M1mod1
4648                         .long   Op46M1mod1
4649                         .long   Op47M1mod1
4650                         .long   Op48M1mod1
4651                         .long   Op49M1mod1
4652                         .long   Op4AM1mod1
4653                         .long   Op4Bmod1
4654                         .long   Op4Cmod1
4655                         .long   Op4DM1mod1
4656                         .long   Op4EM1mod1
4657                         .long   Op4FM1mod1
4658                         .long   Op50mod1
4659                         .long   Op51M1mod1
4660                         .long   Op52M1mod1
4661                         .long   Op53M1mod1
4662                         .long   Op54X1mod1
4663                         .long   Op55M1mod1
4664                         .long   Op56M1mod1
4665                         .long   Op57M1mod1
4666                         .long   Op58mod1
4667                         .long   Op59M1mod1
4668                         .long   Op5AX1mod1
4669                         .long   Op5Bmod1
4670                         .long   Op5Cmod1
4671                         .long   Op5DM1mod1
4672                         .long   Op5EM1mod1
4673                         .long   Op5FM1mod1
4674                         .long   Op60mod1
4675                         .long   Op61M1mod1
4676                         .long   Op62mod1
4677                         .long   Op63M1mod1
4678                         .long   Op64M1mod1
4679                         .long   Op65M1mod1
4680                         .long   Op66M1mod1
4681                         .long   Op67M1mod1
4682                         .long   Op68M1mod1
4683                         .long   Op69M1mod1
4684                         .long   Op6AM1mod1
4685                         .long   Op6Bmod1
4686                         .long   Op6Cmod1
4687                         .long   Op6DM1mod1
4688                         .long   Op6EM1mod1
4689                         .long   Op6FM1mod1
4690                         .long   Op70mod1
4691                         .long   Op71M1mod1
4692                         .long   Op72M1mod1
4693                         .long   Op73M1mod1
4694                         .long   Op74M1mod1
4695                         .long   Op75M1mod1
4696                         .long   Op76M1mod1
4697                         .long   Op77M1mod1
4698                         .long   Op78mod1
4699                         .long   Op79M1mod1
4700                         .long   Op7AX1mod1
4701                         .long   Op7Bmod1
4702                         .long   Op7Cmod1
4703                         .long   Op7DM1mod1
4704                         .long   Op7EM1mod1
4705                         .long   Op7FM1mod1
4706                         .long   Op80mod1
4707                         .long   Op81M1mod1
4708                         .long   Op82mod1
4709                         .long   Op83M1mod1
4710                         .long   Op84X1mod1
4711                         .long   Op85M1mod1
4712                         .long   Op86X1mod1
4713                         .long   Op87M1mod1
4714                         .long   Op88X1mod1
4715                         .long   Op89M1mod1
4716                         .long   Op8AM1mod1
4717                         .long   Op8Bmod1
4718                         .long   Op8CX1mod1
4719                         .long   Op8DM1mod1
4720                         .long   Op8EX1mod1
4721                         .long   Op8FM1mod1
4722                         .long   Op90mod1
4723                         .long   Op91M1mod1
4724                         .long   Op92M1mod1
4725                         .long   Op93M1mod1
4726                         .long   Op94X1mod1
4727                         .long   Op95M1mod1
4728                         .long   Op96X1mod1
4729                         .long   Op97M1mod1
4730                         .long   Op98M1mod1
4731                         .long   Op99M1mod1
4732                         .long   Op9Amod1
4733                         .long   Op9BX1mod1
4734                         .long   Op9CM1mod1
4735                         .long   Op9DM1mod1
4736                         .long   Op9EM1mod1
4737                         .long   Op9FM1mod1
4738                         .long   OpA0X1mod1
4739                         .long   OpA1M1mod1
4740                         .long   OpA2X1mod1
4741                         .long   OpA3M1mod1
4742                         .long   OpA4X1mod1
4743                         .long   OpA5M1mod1
4744                         .long   OpA6X1mod1
4745                         .long   OpA7M1mod1
4746                         .long   OpA8X1mod1
4747                         .long   OpA9M1mod1
4748                         .long   OpAAX1mod1
4749                         .long   OpABmod1
4750                         .long   OpACX1mod1
4751                         .long   OpADM1mod1
4752                         .long   OpAEX1mod1
4753                         .long   OpAFM1mod1
4754                         .long   OpB0mod1
4755                         .long   OpB1M1mod1
4756                         .long   OpB2M1mod1
4757                         .long   OpB3M1mod1
4758                         .long   OpB4X1mod1
4759                         .long   OpB5M1mod1
4760                         .long   OpB6X1mod1
4761                         .long   OpB7M1mod1
4762                         .long   OpB8mod1
4763                         .long   OpB9M1mod1
4764                         .long   OpBAX1mod1
4765                         .long   OpBBX1mod1
4766                         .long   OpBCX1mod1
4767                         .long   OpBDM1mod1
4768                         .long   OpBEX1mod1
4769                         .long   OpBFM1mod1
4770                         .long   OpC0X1mod1
4771                         .long   OpC1M1mod1
4772                         .long   OpC2mod1
4773                         .long   OpC3M1mod1
4774                         .long   OpC4X1mod1
4775                         .long   OpC5M1mod1
4776                         .long   OpC6M1mod1
4777                         .long   OpC7M1mod1
4778                         .long   OpC8X1mod1
4779                         .long   OpC9M1mod1
4780                         .long   OpCAX1mod1
4781                         .long   OpCBmod1
4782                         .long   OpCCX1mod1
4783                         .long   OpCDM1mod1
4784                         .long   OpCEM1mod1
4785                         .long   OpCFM1mod1
4786                         .long   OpD0mod1
4787                         .long   OpD1M1mod1
4788                         .long   OpD2M1mod1
4789                         .long   OpD3M1mod1
4790                         .long   OpD4mod1
4791                         .long   OpD5M1mod1
4792                         .long   OpD6M1mod1
4793                         .long   OpD7M1mod1
4794                         .long   OpD8mod1
4795                         .long   OpD9M1mod1
4796                         .long   OpDAX1mod1
4797                         .long   OpDBmod1
4798                         .long   OpDCmod1
4799                         .long   OpDDM1mod1
4800                         .long   OpDEM1mod1
4801                         .long   OpDFM1mod1
4802                         .long   OpE0X1mod1
4803                         .long   OpE1M1mod1
4804                         .long   OpE2mod1
4805                         .long   OpE3M1mod1
4806                         .long   OpE4X1mod1
4807                         .long   OpE5M1mod1
4808                         .long   OpE6M1mod1
4809                         .long   OpE7M1mod1
4810                         .long   OpE8X1mod1
4811                         .long   OpE9M1mod1
4812                         .long   OpEAmod1
4813                         .long   OpEBmod1
4814                         .long   OpECX1mod1
4815                         .long   OpEDM1mod1
4816                         .long   OpEEM1mod1
4817                         .long   OpEFM1mod1
4818                         .long   OpF0mod1
4819                         .long   OpF1M1mod1
4820                         .long   OpF2M1mod1
4821                         .long   OpF3M1mod1
4822                         .long   OpF4mod1
4823                         .long   OpF5M1mod1
4824                         .long   OpF6M1mod1
4825                         .long   OpF7M1mod1
4826                         .long   OpF8mod1
4827                         .long   OpF9M1mod1
4828                         .long   OpFAX1mod1
4829                         .long   OpFBmod1
4830                         .long   OpFCmod1
4831                         .long   OpFDM1mod1
4832                         .long   OpFEM1mod1
4833                         .long   OpFFM1mod1
4834
4835 Op00mod1:
4836 lbl00mod1:      Op00
4837                         NEXTOPCODE
4838 Op01M1mod1:
4839 lbl01mod1a:     DirectIndexedIndirect1
4840 lbl01mod1b:     ORA8
4841                         NEXTOPCODE
4842 Op02mod1:
4843 lbl02mod1:      Op02
4844                         NEXTOPCODE
4845 Op03M1mod1:
4846 lbl03mod1a:     StackasmRelative
4847 lbl03mod1b:     ORA8
4848                         NEXTOPCODE
4849 Op04M1mod1:
4850 lbl04mod1a:     Direct
4851 lbl04mod1b:     TSB8
4852                         NEXTOPCODE
4853 Op05M1mod1:
4854 lbl05mod1a:     Direct
4855 lbl05mod1b:     ORA8
4856                         NEXTOPCODE
4857 Op06M1mod1:
4858 lbl06mod1a:     Direct
4859 lbl06mod1b:     ASL8
4860                         NEXTOPCODE
4861 Op07M1mod1:
4862 lbl07mod1a:     DirectIndirectLong
4863 lbl07mod1b:     ORA8
4864                         NEXTOPCODE
4865 Op08mod1:
4866 lbl08mod1:      Op08
4867                         NEXTOPCODE
4868 Op09M1mod1:
4869 lbl09mod1:      Op09M1
4870                         NEXTOPCODE
4871 Op0AM1mod1:
4872 lbl0Amod1a:     A_ASL8
4873                         NEXTOPCODE
4874 Op0Bmod1:
4875 lbl0Bmod1:      Op0B
4876                         NEXTOPCODE
4877 Op0CM1mod1:
4878 lbl0Cmod1a:     Absolute
4879 lbl0Cmod1b:     TSB8
4880                         NEXTOPCODE
4881 Op0DM1mod1:
4882 lbl0Dmod1a:     Absolute
4883 lbl0Dmod1b:     ORA8
4884                         NEXTOPCODE
4885 Op0EM1mod1:
4886 lbl0Emod1a:     Absolute
4887 lbl0Emod1b:     ASL8
4888                         NEXTOPCODE
4889 Op0FM1mod1:
4890 lbl0Fmod1a:     AbsoluteLong
4891 lbl0Fmod1b:     ORA8
4892                         NEXTOPCODE
4893 Op10mod1:
4894 lbl10mod1:      Op10
4895                         NEXTOPCODE
4896 Op11M1mod1:
4897 lbl11mod1a:     DirectIndirectIndexed1
4898 lbl11mod1b:     ORA8
4899                         NEXTOPCODE
4900 Op12M1mod1:
4901 lbl12mod1a:     DirectIndirect
4902 lbl12mod1b:     ORA8
4903                         NEXTOPCODE
4904 Op13M1mod1:
4905 lbl13mod1a:     StackasmRelativeIndirectIndexed1
4906 lbl13mod1b:     ORA8
4907                         NEXTOPCODE
4908 Op14M1mod1:
4909 lbl14mod1a:     Direct
4910 lbl14mod1b:     TRB8
4911                         NEXTOPCODE
4912 Op15M1mod1:
4913 lbl15mod1a:     DirectIndexedX1
4914 lbl15mod1b:     ORA8
4915                         NEXTOPCODE
4916 Op16M1mod1:
4917 lbl16mod1a:     DirectIndexedX1
4918 lbl16mod1b:     ASL8
4919                         NEXTOPCODE
4920 Op17M1mod1:
4921 lbl17mod1a:     DirectIndirectIndexedLong1
4922 lbl17mod1b:     ORA8
4923                         NEXTOPCODE
4924 Op18mod1:
4925 lbl18mod1:      Op18
4926                         NEXTOPCODE
4927 Op19M1mod1:
4928 lbl19mod1a:     AbsoluteIndexedY1
4929 lbl19mod1b:     ORA8
4930                         NEXTOPCODE
4931 Op1AM1mod1:
4932 lbl1Amod1a:     A_INC8
4933                         NEXTOPCODE
4934 Op1Bmod1:
4935 lbl1Bmod1:      Op1BM1
4936                         NEXTOPCODE
4937 Op1CM1mod1:
4938 lbl1Cmod1a:     Absolute
4939 lbl1Cmod1b:     TRB8
4940                         NEXTOPCODE
4941 Op1DM1mod1:
4942 lbl1Dmod1a:     AbsoluteIndexedX1
4943 lbl1Dmod1b:     ORA8
4944                         NEXTOPCODE
4945 Op1EM1mod1:
4946 lbl1Emod1a:     AbsoluteIndexedX1
4947 lbl1Emod1b:     ASL8
4948                         NEXTOPCODE
4949 Op1FM1mod1:
4950 lbl1Fmod1a:     AbsoluteLongIndexedX1
4951 lbl1Fmod1b:     ORA8
4952                         NEXTOPCODE
4953 Op20mod1:
4954 lbl20mod1:      Op20
4955                         NEXTOPCODE
4956 Op21M1mod1:
4957 lbl21mod1a:     DirectIndexedIndirect1
4958 lbl21mod1b:     AND8
4959                         NEXTOPCODE
4960 Op22mod1:
4961 lbl22mod1:      Op22
4962                         NEXTOPCODE
4963 Op23M1mod1:
4964 lbl23mod1a:     StackasmRelative
4965 lbl23mod1b:     AND8
4966                         NEXTOPCODE
4967 Op24M1mod1:
4968 lbl24mod1a:     Direct
4969 lbl24mod1b:     BIT8
4970                         NEXTOPCODE
4971 Op25M1mod1:
4972 lbl25mod1a:     Direct
4973 lbl25mod1b:     AND8
4974                         NEXTOPCODE
4975 Op26M1mod1:
4976 lbl26mod1a:     Direct
4977 lbl26mod1b:     ROL8
4978                         NEXTOPCODE
4979 Op27M1mod1:
4980 lbl27mod1a:     DirectIndirectLong
4981 lbl27mod1b:     AND8
4982                         NEXTOPCODE
4983 Op28mod1:
4984 lbl28mod1:      Op28X1M1
4985                         NEXTOPCODE
4986 .pool
4987 Op29M1mod1:
4988 lbl29mod1:      Op29M1
4989                         NEXTOPCODE
4990 Op2AM1mod1:
4991 lbl2Amod1a:     A_ROL8
4992                         NEXTOPCODE
4993 Op2Bmod1:
4994 lbl2Bmod1:      Op2B
4995                         NEXTOPCODE
4996 Op2CM1mod1:
4997 lbl2Cmod1a:     Absolute
4998 lbl2Cmod1b:     BIT8
4999                         NEXTOPCODE
5000 Op2DM1mod1:
5001 lbl2Dmod1a:     Absolute
5002 lbl2Dmod1b:     AND8
5003                         NEXTOPCODE
5004 Op2EM1mod1:
5005 lbl2Emod1a:     Absolute
5006 lbl2Emod1b:     ROL8
5007                         NEXTOPCODE
5008 Op2FM1mod1:
5009 lbl2Fmod1a:     AbsoluteLong
5010 lbl2Fmod1b:     AND8
5011                         NEXTOPCODE
5012 Op30mod1:
5013 lbl30mod1:      Op30
5014                         NEXTOPCODE
5015 Op31M1mod1:
5016 lbl31mod1a:     DirectIndirectIndexed1
5017 lbl31mod1b:     AND8
5018                         NEXTOPCODE
5019 Op32M1mod1:
5020 lbl32mod1a:     DirectIndirect
5021 lbl32mod1b:     AND8
5022                         NEXTOPCODE
5023 Op33M1mod1:
5024 lbl33mod1a:     StackasmRelativeIndirectIndexed1
5025 lbl33mod1b:     AND8
5026                         NEXTOPCODE
5027 Op34M1mod1:
5028 lbl34mod1a:     DirectIndexedX1
5029 lbl34mod1b:     BIT8
5030                         NEXTOPCODE
5031 Op35M1mod1:
5032 lbl35mod1a:     DirectIndexedX1
5033 lbl35mod1b:     AND8
5034                         NEXTOPCODE
5035 Op36M1mod1:
5036 lbl36mod1a:     DirectIndexedX1
5037 lbl36mod1b:     ROL8
5038                         NEXTOPCODE
5039 Op37M1mod1:
5040 lbl37mod1a:     DirectIndirectIndexedLong1
5041 lbl37mod1b:     AND8
5042                         NEXTOPCODE
5043 Op38mod1:
5044 lbl38mod1:      Op38
5045                         NEXTOPCODE
5046 Op39M1mod1:
5047 lbl39mod1a:     AbsoluteIndexedY1
5048 lbl39mod1b:     AND8
5049                         NEXTOPCODE
5050 Op3AM1mod1:
5051 lbl3Amod1a:     A_DEC8
5052                         NEXTOPCODE
5053 Op3Bmod1:
5054 lbl3Bmod1:      Op3BM1
5055                         NEXTOPCODE
5056 Op3CM1mod1:
5057 lbl3Cmod1a:     AbsoluteIndexedX1
5058 lbl3Cmod1b:     BIT8
5059                         NEXTOPCODE
5060 Op3DM1mod1:
5061 lbl3Dmod1a:     AbsoluteIndexedX1
5062 lbl3Dmod1b:     AND8
5063                         NEXTOPCODE
5064 Op3EM1mod1:
5065 lbl3Emod1a:     AbsoluteIndexedX1
5066 lbl3Emod1b:     ROL8
5067                         NEXTOPCODE
5068 Op3FM1mod1:
5069 lbl3Fmod1a:     AbsoluteLongIndexedX1
5070 lbl3Fmod1b:     AND8
5071                         NEXTOPCODE
5072 Op40mod1:
5073 lbl40mod1:      Op40X1M1
5074                         NEXTOPCODE
5075 .pool
5076 Op41M1mod1:
5077 lbl41mod1a:     DirectIndexedIndirect1
5078 lbl41mod1b:     EOR8
5079                         NEXTOPCODE
5080 Op42mod1:
5081 lbl42mod1:      Op42
5082                         NEXTOPCODE
5083 Op43M1mod1:
5084 lbl43mod1a:     StackasmRelative
5085 lbl43mod1b:     EOR8
5086                         NEXTOPCODE
5087 Op44X1mod1:
5088 lbl44mod1:      Op44X1M1
5089                         NEXTOPCODE
5090 Op45M1mod1:
5091 lbl45mod1a:     Direct
5092 lbl45mod1b:     EOR8
5093                         NEXTOPCODE
5094 Op46M1mod1:
5095 lbl46mod1a:     Direct
5096 lbl46mod1b:     LSR8
5097                         NEXTOPCODE
5098 Op47M1mod1:
5099 lbl47mod1a:     DirectIndirectLong
5100 lbl47mod1b:     EOR8
5101                         NEXTOPCODE
5102 Op48M1mod1:
5103 lbl48mod1:      Op48M1
5104                         NEXTOPCODE
5105 Op49M1mod1:
5106 lbl49mod1:      Op49M1
5107                         NEXTOPCODE
5108 Op4AM1mod1:
5109 lbl4Amod1a:     A_LSR8
5110                         NEXTOPCODE
5111 Op4Bmod1:
5112 lbl4Bmod1:      Op4B
5113                         NEXTOPCODE
5114 Op4Cmod1:
5115 lbl4Cmod1:      Op4C
5116                         NEXTOPCODE
5117 Op4DM1mod1:
5118 lbl4Dmod1a:     Absolute
5119 lbl4Dmod1b:     EOR8
5120                         NEXTOPCODE
5121 Op4EM1mod1:
5122 lbl4Emod1a:     Absolute
5123 lbl4Emod1b:     LSR8
5124                         NEXTOPCODE
5125 Op4FM1mod1:
5126 lbl4Fmod1a:     AbsoluteLong
5127 lbl4Fmod1b:     EOR8
5128                         NEXTOPCODE
5129 Op50mod1:
5130 lbl50mod1:      Op50
5131                         NEXTOPCODE
5132 Op51M1mod1:
5133 lbl51mod1a:     DirectIndirectIndexed1
5134 lbl51mod1b:     EOR8
5135                         NEXTOPCODE
5136 Op52M1mod1:
5137 lbl52mod1a:     DirectIndirect
5138 lbl52mod1b:     EOR8
5139                         NEXTOPCODE
5140 Op53M1mod1:
5141 lbl53mod1a:     StackasmRelativeIndirectIndexed1
5142 lbl53mod1b:     EOR8
5143                         NEXTOPCODE
5144 Op54X1mod1:
5145 lbl54mod1:      Op54X1M1
5146                         NEXTOPCODE
5147 Op55M1mod1:
5148 lbl55mod1a:     DirectIndexedX1
5149 lbl55mod1b:     EOR8
5150                         NEXTOPCODE
5151 Op56M1mod1:
5152 lbl56mod1a:     DirectIndexedX1
5153 lbl56mod1b:     LSR8
5154                         NEXTOPCODE
5155 Op57M1mod1:
5156 lbl57mod1a:     DirectIndirectIndexedLong1
5157 lbl57mod1b:     EOR8
5158                         NEXTOPCODE
5159 Op58mod1:
5160 lbl58mod1:      Op58
5161                         NEXTOPCODE
5162 Op59M1mod1:
5163 lbl59mod1a:     AbsoluteIndexedY1
5164 lbl59mod1b:     EOR8
5165                         NEXTOPCODE
5166 Op5AX1mod1:
5167 lbl5Amod1:      Op5AX1
5168                         NEXTOPCODE
5169 Op5Bmod1:
5170 lbl5Bmod1:      Op5BM1
5171                         NEXTOPCODE
5172 Op5Cmod1:
5173 lbl5Cmod1:      Op5C
5174                         NEXTOPCODE
5175 Op5DM1mod1:
5176 lbl5Dmod1a:     AbsoluteIndexedX1
5177 lbl5Dmod1b:     EOR8
5178                         NEXTOPCODE
5179 Op5EM1mod1:
5180 lbl5Emod1a:     AbsoluteIndexedX1
5181 lbl5Emod1b:     LSR8
5182                         NEXTOPCODE
5183 Op5FM1mod1:
5184 lbl5Fmod1a:     AbsoluteLongIndexedX1
5185 lbl5Fmod1b:     EOR8
5186                         NEXTOPCODE
5187 Op60mod1:
5188 lbl60mod1:      Op60
5189                         NEXTOPCODE
5190 Op61M1mod1:
5191 lbl61mod1a:     DirectIndexedIndirect1
5192 lbl61mod1b:     ADC8
5193                         NEXTOPCODE
5194 Op62mod1:
5195 lbl62mod1:      Op62
5196                         NEXTOPCODE
5197 Op63M1mod1:
5198 lbl63mod1a:     StackasmRelative
5199 lbl63mod1b:     ADC8
5200                         NEXTOPCODE
5201 Op64M1mod1:
5202 lbl64mod1a:     Direct
5203 lbl64mod1b:     STZ8
5204                         NEXTOPCODE
5205 Op65M1mod1:
5206 lbl65mod1a:     Direct
5207 lbl65mod1b:     ADC8
5208                         NEXTOPCODE
5209 Op66M1mod1:
5210 lbl66mod1a:     Direct
5211 lbl66mod1b:     ROR8
5212                         NEXTOPCODE
5213 Op67M1mod1:
5214 lbl67mod1a:     DirectIndirectLong
5215 lbl67mod1b:     ADC8
5216                         NEXTOPCODE
5217 Op68M1mod1:
5218 lbl68mod1:      Op68M1
5219                         NEXTOPCODE
5220 Op69M1mod1:
5221 lbl69mod1a:     Immediate8
5222 lbl69mod1b:     ADC8
5223                         NEXTOPCODE
5224 Op6AM1mod1:
5225 lbl6Amod1a:     A_ROR8
5226                         NEXTOPCODE
5227 Op6Bmod1:
5228 lbl6Bmod1:      Op6B
5229                         NEXTOPCODE
5230 Op6Cmod1:
5231 lbl6Cmod1:      Op6C
5232                         NEXTOPCODE
5233 Op6DM1mod1:
5234 lbl6Dmod1a:     Absolute
5235 lbl6Dmod1b:     ADC8
5236                         NEXTOPCODE
5237 Op6EM1mod1:
5238 lbl6Emod1a:     Absolute
5239 lbl6Emod1b:     ROR8
5240                         NEXTOPCODE
5241 Op6FM1mod1:
5242 lbl6Fmod1a:     AbsoluteLong
5243 lbl6Fmod1b:     ADC8
5244                         NEXTOPCODE
5245 Op70mod1:
5246 lbl70mod1:      Op70
5247                         NEXTOPCODE
5248 Op71M1mod1:
5249 lbl71mod1a:     DirectIndirectIndexed1
5250 lbl71mod1b:     ADC8
5251                         NEXTOPCODE
5252 Op72M1mod1:
5253 lbl72mod1a:     DirectIndirect
5254 lbl72mod1b:     ADC8
5255                         NEXTOPCODE
5256 Op73M1mod1:
5257 lbl73mod1a:     StackasmRelativeIndirectIndexed1
5258 lbl73mod1b:     ADC8
5259                         NEXTOPCODE
5260
5261 Op74M1mod1:
5262 lbl74mod1a:     DirectIndexedX1
5263 lbl74mod1b:     STZ8
5264                         NEXTOPCODE
5265 Op75M1mod1:
5266 lbl75mod1a:     DirectIndexedX1
5267 lbl75mod1b:     ADC8
5268                         NEXTOPCODE
5269 Op76M1mod1:
5270 lbl76mod1a:     DirectIndexedX1
5271 lbl76mod1b:     ROR8
5272                         NEXTOPCODE
5273 Op77M1mod1:
5274 lbl77mod1a:     DirectIndirectIndexedLong1
5275 lbl77mod1b:     ADC8
5276                         NEXTOPCODE
5277 Op78mod1:
5278 lbl78mod1:      Op78
5279                         NEXTOPCODE
5280 Op79M1mod1:
5281 lbl79mod1a:     AbsoluteIndexedY1
5282 lbl79mod1b:     ADC8
5283                         NEXTOPCODE
5284 Op7AX1mod1:
5285 lbl7Amod1:      Op7AX1
5286                         NEXTOPCODE
5287 Op7Bmod1:
5288 lbl7Bmod1:      Op7BM1
5289                         NEXTOPCODE
5290 Op7Cmod1:
5291 lbl7Cmod1:      AbsoluteIndexedIndirectX1
5292                 Op7C
5293                         NEXTOPCODE
5294 Op7DM1mod1:
5295 lbl7Dmod1a:     AbsoluteIndexedX1
5296 lbl7Dmod1b:     ADC8
5297                         NEXTOPCODE
5298 Op7EM1mod1:
5299 lbl7Emod1a:     AbsoluteIndexedX1
5300 lbl7Emod1b:     ROR8
5301                         NEXTOPCODE
5302 Op7FM1mod1:
5303 lbl7Fmod1a:     AbsoluteLongIndexedX1
5304 lbl7Fmod1b:     ADC8
5305                         NEXTOPCODE
5306
5307
5308 Op80mod1:
5309 lbl80mod1:      Op80
5310                         NEXTOPCODE
5311 Op81M1mod1:
5312 lbl81mod1a:     DirectIndexedIndirect1
5313 lbl81mod1b:     Op81M1
5314                         NEXTOPCODE
5315 Op82mod1:
5316 lbl82mod1:      Op82
5317                         NEXTOPCODE
5318 Op83M1mod1:
5319 lbl83mod1a:     StackasmRelative
5320 lbl83mod1b:     STA8
5321                         NEXTOPCODE
5322 Op84X1mod1:
5323 lbl84mod1a:     Direct
5324 lbl84mod1b:     STY8
5325                         NEXTOPCODE
5326 Op85M1mod1:
5327 lbl85mod1a:     Direct
5328 lbl85mod1b:     STA8
5329                         NEXTOPCODE
5330 Op86X1mod1:
5331 lbl86mod1a:     Direct
5332 lbl86mod1b:     STX8
5333                         NEXTOPCODE
5334 Op87M1mod1:
5335 lbl87mod1a:     DirectIndirectLong
5336 lbl87mod1b:     STA8
5337                         NEXTOPCODE
5338 Op88X1mod1:
5339 lbl88mod1:      Op88X1
5340                         NEXTOPCODE
5341 Op89M1mod1:
5342 lbl89mod1:      Op89M1
5343                         NEXTOPCODE
5344 Op8AM1mod1:
5345 lbl8Amod1:      Op8AM1X1
5346                         NEXTOPCODE
5347 Op8Bmod1:
5348 lbl8Bmod1:      Op8B
5349                         NEXTOPCODE
5350 Op8CX1mod1:
5351 lbl8Cmod1a:     Absolute
5352 lbl8Cmod1b:     STY8
5353                         NEXTOPCODE
5354 Op8DM1mod1:
5355 lbl8Dmod1a:     Absolute
5356 lbl8Dmod1b:     STA8
5357                         NEXTOPCODE
5358 Op8EX1mod1:
5359 lbl8Emod1a:     Absolute
5360 lbl8Emod1b:     STX8
5361                         NEXTOPCODE
5362 Op8FM1mod1:
5363 lbl8Fmod1a:     AbsoluteLong
5364 lbl8Fmod1b:     STA8
5365                         NEXTOPCODE
5366 Op90mod1:
5367 lbl90mod1:      Op90
5368                         NEXTOPCODE
5369 Op91M1mod1:
5370 lbl91mod1a:     DirectIndirectIndexed1
5371 lbl91mod1b:     STA8
5372                         NEXTOPCODE
5373 Op92M1mod1:
5374 lbl92mod1a:     DirectIndirect
5375 lbl92mod1b:     STA8
5376                         NEXTOPCODE
5377 Op93M1mod1:
5378 lbl93mod1a:     StackasmRelativeIndirectIndexed1
5379 lbl93mod1b:     STA8
5380                         NEXTOPCODE
5381 Op94X1mod1:
5382 lbl94mod1a:     DirectIndexedX1
5383 lbl94mod1b:     STY8
5384                         NEXTOPCODE
5385 Op95M1mod1:
5386 lbl95mod1a:     DirectIndexedX1
5387 lbl95mod1b:     STA8
5388                         NEXTOPCODE
5389 Op96X1mod1:
5390 lbl96mod1a:     DirectIndexedY1
5391 lbl96mod1b:     STX8
5392                         NEXTOPCODE
5393 Op97M1mod1:
5394 lbl97mod1a:     DirectIndirectIndexedLong1
5395 lbl97mod1b:     STA8
5396                         NEXTOPCODE
5397 Op98M1mod1:
5398 lbl98mod1:      Op98M1X1
5399                         NEXTOPCODE
5400 Op99M1mod1:
5401 lbl99mod1a:     AbsoluteIndexedY1
5402 lbl99mod1b:     STA8
5403                         NEXTOPCODE
5404 Op9Amod1:
5405 lbl9Amod1:      Op9AX1
5406                         NEXTOPCODE
5407 Op9BX1mod1:
5408 lbl9Bmod1:      Op9BX1
5409                         NEXTOPCODE
5410 Op9CM1mod1:
5411 lbl9Cmod1a:     Absolute
5412 lbl9Cmod1b:     STZ8
5413                         NEXTOPCODE
5414 Op9DM1mod1:
5415 lbl9Dmod1a:     AbsoluteIndexedX1
5416 lbl9Dmod1b:     STA8
5417                         NEXTOPCODE
5418 Op9EM1mod1:
5419 lbl9Emod1:      AbsoluteIndexedX1
5420                 STZ8
5421                         NEXTOPCODE
5422 Op9FM1mod1:
5423 lbl9Fmod1a:     AbsoluteLongIndexedX1
5424 lbl9Fmod1b:     STA8
5425                         NEXTOPCODE
5426 OpA0X1mod1:
5427 lblA0mod1:      OpA0X1
5428                         NEXTOPCODE
5429 OpA1M1mod1:
5430 lblA1mod1a:     DirectIndexedIndirect1
5431 lblA1mod1b:     LDA8
5432                         NEXTOPCODE
5433 OpA2X1mod1:
5434 lblA2mod1:      OpA2X1
5435                         NEXTOPCODE
5436 OpA3M1mod1:
5437 lblA3mod1a:     StackasmRelative
5438 lblA3mod1b:     LDA8
5439                         NEXTOPCODE
5440 OpA4X1mod1:
5441 lblA4mod1a:     Direct
5442 lblA4mod1b:     LDY8
5443                         NEXTOPCODE
5444 OpA5M1mod1:
5445 lblA5mod1a:     Direct
5446 lblA5mod1b:     LDA8
5447                         NEXTOPCODE
5448 OpA6X1mod1:
5449 lblA6mod1a:     Direct
5450 lblA6mod1b:     LDX8
5451                         NEXTOPCODE
5452 OpA7M1mod1:
5453 lblA7mod1a:     DirectIndirectLong
5454 lblA7mod1b:     LDA8
5455                         NEXTOPCODE
5456 OpA8X1mod1:
5457 lblA8mod1:      OpA8X1M1
5458                         NEXTOPCODE
5459 OpA9M1mod1:
5460 lblA9mod1:      OpA9M1
5461                         NEXTOPCODE
5462 OpAAX1mod1:
5463 lblAAmod1:      OpAAX1M1
5464                         NEXTOPCODE
5465 OpABmod1:
5466 lblABmod1:      OpAB
5467                         NEXTOPCODE
5468 OpACX1mod1:
5469 lblACmod1a:     Absolute
5470 lblACmod1b:     LDY8
5471                         NEXTOPCODE
5472 OpADM1mod1:
5473 lblADmod1a:     Absolute
5474 lblADmod1b:     LDA8
5475                         NEXTOPCODE
5476 OpAEX1mod1:
5477 lblAEmod1a:     Absolute
5478 lblAEmod1b:     LDX8
5479                         NEXTOPCODE
5480 OpAFM1mod1:
5481 lblAFmod1a:     AbsoluteLong
5482 lblAFmod1b:     LDA8
5483                         NEXTOPCODE
5484 OpB0mod1:
5485 lblB0mod1:      OpB0
5486                         NEXTOPCODE
5487 OpB1M1mod1:
5488 lblB1mod1a:     DirectIndirectIndexed1
5489 lblB1mod1b:     LDA8
5490                         NEXTOPCODE
5491 OpB2M1mod1:
5492 lblB2mod1a:     DirectIndirect
5493 lblB2mod1b:     LDA8
5494                         NEXTOPCODE
5495 OpB3M1mod1:
5496 lblB3mod1a:     StackasmRelativeIndirectIndexed1
5497 lblB3mod1b:     LDA8
5498                         NEXTOPCODE
5499 OpB4X1mod1:
5500 lblB4mod1a:     DirectIndexedX1
5501 lblB4mod1b:     LDY8
5502                         NEXTOPCODE
5503 OpB5M1mod1:
5504 lblB5mod1a:     DirectIndexedX1
5505 lblB5mod1b:     LDA8
5506                         NEXTOPCODE
5507 OpB6X1mod1:
5508 lblB6mod1a:     DirectIndexedY1
5509 lblB6mod1b:     LDX8
5510                         NEXTOPCODE
5511 OpB7M1mod1:
5512 lblB7mod1a:     DirectIndirectIndexedLong1
5513 lblB7mod1b:     LDA8
5514                         NEXTOPCODE
5515 OpB8mod1:
5516 lblB8mod1:      OpB8
5517                         NEXTOPCODE
5518 OpB9M1mod1:
5519 lblB9mod1a:     AbsoluteIndexedY1
5520 lblB9mod1b:     LDA8
5521                         NEXTOPCODE
5522 OpBAX1mod1:
5523 lblBAmod1:      OpBAX1
5524                         NEXTOPCODE
5525 OpBBX1mod1:
5526 lblBBmod1:      OpBBX1
5527                         NEXTOPCODE
5528 OpBCX1mod1:
5529 lblBCmod1a:     AbsoluteIndexedX1
5530 lblBCmod1b:     LDY8
5531                         NEXTOPCODE
5532 OpBDM1mod1:
5533 lblBDmod1a:     AbsoluteIndexedX1
5534 lblBDmod1b:     LDA8
5535                         NEXTOPCODE
5536 OpBEX1mod1:
5537 lblBEmod1a:     AbsoluteIndexedY1
5538 lblBEmod1b:     LDX8
5539                         NEXTOPCODE
5540 OpBFM1mod1:
5541 lblBFmod1a:     AbsoluteLongIndexedX1
5542 lblBFmod1b:     LDA8
5543                         NEXTOPCODE
5544 OpC0X1mod1:
5545 lblC0mod1:      OpC0X1
5546                         NEXTOPCODE
5547 OpC1M1mod1:
5548 lblC1mod1a:     DirectIndexedIndirect1
5549 lblC1mod1b:     CMP8
5550                         NEXTOPCODE
5551 OpC2mod1:
5552 lblC2mod1:      OpC2
5553                         NEXTOPCODE
5554 .pool
5555 OpC3M1mod1:
5556 lblC3mod1a:     StackasmRelative
5557 lblC3mod1b:     CMP8
5558                         NEXTOPCODE
5559 OpC4X1mod1:
5560 lblC4mod1a:     Direct
5561 lblC4mod1b:     CMY8
5562                         NEXTOPCODE
5563 OpC5M1mod1:
5564 lblC5mod1a:     Direct
5565 lblC5mod1b:     CMP8
5566                         NEXTOPCODE
5567 OpC6M1mod1:
5568 lblC6mod1a:     Direct
5569 lblC6mod1b:     DEC8
5570                         NEXTOPCODE
5571 OpC7M1mod1:
5572 lblC7mod1a:     DirectIndirectLong
5573 lblC7mod1b:     CMP8
5574                         NEXTOPCODE
5575 OpC8X1mod1:
5576 lblC8mod1:      OpC8X1
5577                         NEXTOPCODE
5578 OpC9M1mod1:
5579 lblC9mod1:      OpC9M1
5580                         NEXTOPCODE
5581 OpCAX1mod1:
5582 lblCAmod1:      OpCAX1
5583                         NEXTOPCODE
5584 OpCBmod1:
5585 lblCBmod1:      OpCB
5586                         NEXTOPCODE
5587 OpCCX1mod1:
5588 lblCCmod1a:     Absolute
5589 lblCCmod1b:     CMY8
5590                         NEXTOPCODE
5591 OpCDM1mod1:
5592 lblCDmod1a:     Absolute
5593 lblCDmod1b:     CMP8
5594                         NEXTOPCODE
5595 OpCEM1mod1:
5596 lblCEmod1a:     Absolute
5597 lblCEmod1b:     DEC8
5598                         NEXTOPCODE
5599 OpCFM1mod1:
5600 lblCFmod1a:     AbsoluteLong
5601 lblCFmod1b:     CMP8
5602                         NEXTOPCODE
5603 OpD0mod1:
5604 lblD0mod1:      OpD0
5605                         NEXTOPCODE
5606 OpD1M1mod1:
5607 lblD1mod1a:     DirectIndirectIndexed1
5608 lblD1mod1b:     CMP8
5609                         NEXTOPCODE
5610 OpD2M1mod1:
5611 lblD2mod1a:     DirectIndirect
5612 lblD2mod1b:     CMP8
5613                         NEXTOPCODE
5614 OpD3M1mod1:
5615 lblD3mod1a:     StackasmRelativeIndirectIndexed1
5616 lblD3mod1b:     CMP8
5617                         NEXTOPCODE
5618 OpD4mod1:
5619 lblD4mod1:      OpD4
5620                         NEXTOPCODE
5621 OpD5M1mod1:
5622 lblD5mod1a:     DirectIndexedX1
5623 lblD5mod1b:     CMP8
5624                         NEXTOPCODE
5625 OpD6M1mod1:
5626 lblD6mod1a:     DirectIndexedX1
5627 lblD6mod1b:     DEC8
5628                         NEXTOPCODE
5629 OpD7M1mod1:
5630 lblD7mod1a:     DirectIndirectIndexedLong1
5631 lblD7mod1b:     CMP8
5632                         NEXTOPCODE
5633 OpD8mod1:
5634 lblD8mod1:      OpD8
5635                         NEXTOPCODE
5636 OpD9M1mod1:
5637 lblD9mod1a:     AbsoluteIndexedY1
5638 lblD9mod1b:     CMP8
5639                         NEXTOPCODE
5640 OpDAX1mod1:
5641 lblDAmod1:      OpDAX1
5642                         NEXTOPCODE
5643 OpDBmod1:
5644 lblDBmod1:      OpDB
5645                         NEXTOPCODE
5646 OpDCmod1:
5647 lblDCmod1:      OpDC
5648                         NEXTOPCODE
5649 OpDDM1mod1:
5650 lblDDmod1a:     AbsoluteIndexedX1
5651 lblDDmod1b:     CMP8
5652                         NEXTOPCODE
5653 OpDEM1mod1:
5654 lblDEmod1a:     AbsoluteIndexedX1
5655 lblDEmod1b:     DEC8
5656                         NEXTOPCODE
5657 OpDFM1mod1:
5658 lblDFmod1a:     AbsoluteLongIndexedX1
5659 lblDFmod1b:     CMP8
5660                         NEXTOPCODE
5661 OpE0X1mod1:
5662 lblE0mod1:      OpE0X1
5663                         NEXTOPCODE
5664 OpE1M1mod1:
5665 lblE1mod1a:     DirectIndexedIndirect1
5666 lblE1mod1b:     SBC8
5667                         NEXTOPCODE
5668 OpE2mod1:
5669 lblE2mod1:      OpE2
5670                         NEXTOPCODE
5671 .pool
5672 OpE3M1mod1:
5673 lblE3mod1a:     StackasmRelative
5674 lblE3mod1b:     SBC8
5675                         NEXTOPCODE
5676 OpE4X1mod1:
5677 lblE4mod1a:     Direct
5678 lblE4mod1b:     CMX8
5679                         NEXTOPCODE
5680 OpE5M1mod1:
5681 lblE5mod1a:     Direct
5682 lblE5mod1b:     SBC8
5683                         NEXTOPCODE
5684 OpE6M1mod1:
5685 lblE6mod1a:     Direct
5686 lblE6mod1b:     INC8
5687                         NEXTOPCODE
5688 OpE7M1mod1:
5689 lblE7mod1a:     DirectIndirectLong
5690 lblE7mod1b:     SBC8
5691                         NEXTOPCODE
5692 OpE8X1mod1:
5693 lblE8mod1:      OpE8X1
5694                         NEXTOPCODE
5695 OpE9M1mod1:
5696 lblE9mod1a:     Immediate8
5697 lblE9mod1b:     SBC8
5698                         NEXTOPCODE
5699 OpEAmod1:
5700 lblEAmod1:      OpEA
5701                         NEXTOPCODE
5702 OpEBmod1:
5703 lblEBmod1:      OpEBM1
5704                         NEXTOPCODE
5705 OpECX1mod1:
5706 lblECmod1a:     Absolute
5707 lblECmod1b:     CMX8
5708                         NEXTOPCODE
5709 OpEDM1mod1:
5710 lblEDmod1a:     Absolute
5711 lblEDmod1b:     SBC8
5712                         NEXTOPCODE
5713 OpEEM1mod1:
5714 lblEEmod1a:     Absolute
5715 lblEEmod1b:     INC8
5716                         NEXTOPCODE
5717 OpEFM1mod1:
5718 lblEFmod1a:     AbsoluteLong
5719 lblEFmod1b:     SBC8
5720                         NEXTOPCODE
5721 OpF0mod1:
5722 lblF0mod1:      OpF0
5723                         NEXTOPCODE
5724 OpF1M1mod1:
5725 lblF1mod1a:     DirectIndirectIndexed1
5726 lblF1mod1b:     SBC8
5727                         NEXTOPCODE
5728 OpF2M1mod1:
5729 lblF2mod1a:     DirectIndirect
5730 lblF2mod1b:     SBC8
5731                         NEXTOPCODE
5732 OpF3M1mod1:
5733 lblF3mod1a:     StackasmRelativeIndirectIndexed1
5734 lblF3mod1b:     SBC8
5735                         NEXTOPCODE
5736 OpF4mod1:
5737 lblF4mod1:      OpF4
5738                         NEXTOPCODE
5739 OpF5M1mod1:
5740 lblF5mod1a:     DirectIndexedX1
5741 lblF5mod1b:     SBC8
5742                         NEXTOPCODE
5743 OpF6M1mod1:
5744 lblF6mod1a:     DirectIndexedX1
5745 lblF6mod1b:     INC8
5746                         NEXTOPCODE
5747 OpF7M1mod1:
5748 lblF7mod1a:     DirectIndirectIndexedLong1
5749 lblF7mod1b:     SBC8
5750                         NEXTOPCODE
5751 OpF8mod1:
5752 lblF8mod1:      OpF8
5753                         NEXTOPCODE
5754 OpF9M1mod1:
5755 lblF9mod1a:     AbsoluteIndexedY1
5756 lblF9mod1b:     SBC8
5757                         NEXTOPCODE
5758 OpFAX1mod1:
5759 lblFAmod1:      OpFAX1
5760                         NEXTOPCODE
5761 OpFBmod1:
5762 lblFBmod1:      OpFB
5763                         NEXTOPCODE
5764 OpFCmod1:
5765 lblFCmod1:      OpFCX1
5766                         NEXTOPCODE
5767 OpFDM1mod1:
5768 lblFDmod1a:     AbsoluteIndexedX1
5769 lblFDmod1b:     SBC8
5770                         NEXTOPCODE
5771 OpFEM1mod1:
5772 lblFEmod1a:     AbsoluteIndexedX1
5773 lblFEmod1b:     INC8
5774                         NEXTOPCODE
5775 OpFFM1mod1:
5776 lblFFmod1a:     AbsoluteLongIndexedX1
5777 lblFFmod1b:     SBC8
5778                         NEXTOPCODE
5779 .pool
5780
5781
5782 jumptable2:             .long   Op00mod2
5783                         .long   Op01M1mod2
5784                         .long   Op02mod2
5785                         .long   Op03M1mod2
5786                         .long   Op04M1mod2
5787                         .long   Op05M1mod2
5788                         .long   Op06M1mod2
5789                         .long   Op07M1mod2
5790                         .long   Op08mod2
5791                         .long   Op09M1mod2
5792                         .long   Op0AM1mod2
5793                         .long   Op0Bmod2
5794                         .long   Op0CM1mod2
5795                         .long   Op0DM1mod2
5796                         .long   Op0EM1mod2
5797                         .long   Op0FM1mod2
5798                         .long   Op10mod2
5799                         .long   Op11M1mod2
5800                         .long   Op12M1mod2
5801                         .long   Op13M1mod2
5802                         .long   Op14M1mod2
5803                         .long   Op15M1mod2
5804                         .long   Op16M1mod2
5805                         .long   Op17M1mod2
5806                         .long   Op18mod2
5807                         .long   Op19M1mod2
5808                         .long   Op1AM1mod2
5809                         .long   Op1Bmod2
5810                         .long   Op1CM1mod2
5811                         .long   Op1DM1mod2
5812                         .long   Op1EM1mod2
5813                         .long   Op1FM1mod2
5814                         .long   Op20mod2
5815                         .long   Op21M1mod2
5816                         .long   Op22mod2
5817                         .long   Op23M1mod2
5818                         .long   Op24M1mod2
5819                         .long   Op25M1mod2
5820                         .long   Op26M1mod2
5821                         .long   Op27M1mod2
5822                         .long   Op28mod2
5823                         .long   Op29M1mod2
5824                         .long   Op2AM1mod2
5825                         .long   Op2Bmod2
5826                         .long   Op2CM1mod2
5827                         .long   Op2DM1mod2
5828                         .long   Op2EM1mod2
5829                         .long   Op2FM1mod2
5830                         .long   Op30mod2
5831                         .long   Op31M1mod2
5832                         .long   Op32M1mod2
5833                         .long   Op33M1mod2
5834                         .long   Op34M1mod2
5835                         .long   Op35M1mod2
5836                         .long   Op36M1mod2
5837                         .long   Op37M1mod2
5838                         .long   Op38mod2
5839                         .long   Op39M1mod2
5840                         .long   Op3AM1mod2
5841                         .long   Op3Bmod2
5842                         .long   Op3CM1mod2
5843                         .long   Op3DM1mod2
5844                         .long   Op3EM1mod2
5845                         .long   Op3FM1mod2
5846                         .long   Op40mod2
5847                         .long   Op41M1mod2
5848                         .long   Op42mod2
5849                         .long   Op43M1mod2
5850                         .long   Op44X0mod2
5851                         .long   Op45M1mod2
5852                         .long   Op46M1mod2
5853                         .long   Op47M1mod2
5854                         .long   Op48M1mod2
5855                         .long   Op49M1mod2
5856                         .long   Op4AM1mod2
5857                         .long   Op4Bmod2
5858                         .long   Op4Cmod2
5859                         .long   Op4DM1mod2
5860                         .long   Op4EM1mod2
5861                         .long   Op4FM1mod2
5862                         .long   Op50mod2
5863                         .long   Op51M1mod2
5864                         .long   Op52M1mod2
5865                         .long   Op53M1mod2
5866                         .long   Op54X0mod2
5867                         .long   Op55M1mod2
5868                         .long   Op56M1mod2
5869                         .long   Op57M1mod2
5870                         .long   Op58mod2
5871                         .long   Op59M1mod2
5872                         .long   Op5AX0mod2
5873                         .long   Op5Bmod2
5874                         .long   Op5Cmod2
5875                         .long   Op5DM1mod2
5876                         .long   Op5EM1mod2
5877                         .long   Op5FM1mod2
5878                         .long   Op60mod2
5879                         .long   Op61M1mod2
5880                         .long   Op62mod2
5881                         .long   Op63M1mod2
5882                         .long   Op64M1mod2
5883                         .long   Op65M1mod2
5884                         .long   Op66M1mod2
5885                         .long   Op67M1mod2
5886                         .long   Op68M1mod2
5887                         .long   Op69M1mod2
5888                         .long   Op6AM1mod2
5889                         .long   Op6Bmod2
5890                         .long   Op6Cmod2
5891                         .long   Op6DM1mod2
5892                         .long   Op6EM1mod2
5893                         .long   Op6FM1mod2
5894                         .long   Op70mod2
5895                         .long   Op71M1mod2
5896                         .long   Op72M1mod2
5897                         .long   Op73M1mod2
5898                         .long   Op74M1mod2
5899                         .long   Op75M1mod2
5900                         .long   Op76M1mod2
5901                         .long   Op77M1mod2
5902                         .long   Op78mod2
5903                         .long   Op79M1mod2
5904                         .long   Op7AX0mod2
5905                         .long   Op7Bmod2
5906                         .long   Op7Cmod2
5907                         .long   Op7DM1mod2
5908                         .long   Op7EM1mod2
5909                         .long   Op7FM1mod2
5910                         .long   Op80mod2
5911                         .long   Op81M1mod2
5912                         .long   Op82mod2
5913                         .long   Op83M1mod2
5914                         .long   Op84X0mod2
5915                         .long   Op85M1mod2
5916                         .long   Op86X0mod2
5917                         .long   Op87M1mod2
5918                         .long   Op88X0mod2
5919                         .long   Op89M1mod2
5920                         .long   Op8AM1mod2
5921                         .long   Op8Bmod2
5922                         .long   Op8CX0mod2
5923                         .long   Op8DM1mod2
5924                         .long   Op8EX0mod2
5925                         .long   Op8FM1mod2
5926                         .long   Op90mod2
5927                         .long   Op91M1mod2
5928                         .long   Op92M1mod2
5929                         .long   Op93M1mod2
5930                         .long   Op94X0mod2
5931                         .long   Op95M1mod2
5932                         .long   Op96X0mod2
5933                         .long   Op97M1mod2
5934                         .long   Op98M1mod2
5935                         .long   Op99M1mod2
5936                         .long   Op9Amod2
5937                         .long   Op9BX0mod2
5938                         .long   Op9CM1mod2
5939                         .long   Op9DM1mod2
5940                         .long   Op9EM1mod2
5941                         .long   Op9FM1mod2
5942                         .long   OpA0X0mod2
5943                         .long   OpA1M1mod2
5944                         .long   OpA2X0mod2
5945                         .long   OpA3M1mod2
5946                         .long   OpA4X0mod2
5947                         .long   OpA5M1mod2
5948                         .long   OpA6X0mod2
5949                         .long   OpA7M1mod2
5950                         .long   OpA8X0mod2
5951                         .long   OpA9M1mod2
5952                         .long   OpAAX0mod2
5953                         .long   OpABmod2
5954                         .long   OpACX0mod2
5955                         .long   OpADM1mod2
5956                         .long   OpAEX0mod2
5957                         .long   OpAFM1mod2
5958                         .long   OpB0mod2
5959                         .long   OpB1M1mod2
5960                         .long   OpB2M1mod2
5961                         .long   OpB3M1mod2
5962                         .long   OpB4X0mod2
5963                         .long   OpB5M1mod2
5964                         .long   OpB6X0mod2
5965                         .long   OpB7M1mod2
5966                         .long   OpB8mod2
5967                         .long   OpB9M1mod2
5968                         .long   OpBAX0mod2
5969                         .long   OpBBX0mod2
5970                         .long   OpBCX0mod2
5971                         .long   OpBDM1mod2
5972                         .long   OpBEX0mod2
5973                         .long   OpBFM1mod2
5974                         .long   OpC0X0mod2
5975                         .long   OpC1M1mod2
5976                         .long   OpC2mod2
5977                         .long   OpC3M1mod2
5978                         .long   OpC4X0mod2
5979                         .long   OpC5M1mod2
5980                         .long   OpC6M1mod2
5981                         .long   OpC7M1mod2
5982                         .long   OpC8X0mod2
5983                         .long   OpC9M1mod2
5984                         .long   OpCAX0mod2
5985                         .long   OpCBmod2
5986                         .long   OpCCX0mod2
5987                         .long   OpCDM1mod2
5988                         .long   OpCEM1mod2
5989                         .long   OpCFM1mod2
5990                         .long   OpD0mod2
5991                         .long   OpD1M1mod2
5992                         .long   OpD2M1mod2
5993                         .long   OpD3M1mod2
5994                         .long   OpD4mod2
5995                         .long   OpD5M1mod2
5996                         .long   OpD6M1mod2
5997                         .long   OpD7M1mod2
5998                         .long   OpD8mod2
5999                         .long   OpD9M1mod2
6000                         .long   OpDAX0mod2
6001                         .long   OpDBmod2
6002                         .long   OpDCmod2
6003                         .long   OpDDM1mod2
6004                         .long   OpDEM1mod2
6005                         .long   OpDFM1mod2
6006                         .long   OpE0X0mod2
6007                         .long   OpE1M1mod2
6008                         .long   OpE2mod2
6009                         .long   OpE3M1mod2
6010                         .long   OpE4X0mod2
6011                         .long   OpE5M1mod2
6012                         .long   OpE6M1mod2
6013                         .long   OpE7M1mod2
6014                         .long   OpE8X0mod2
6015                         .long   OpE9M1mod2
6016                         .long   OpEAmod2
6017                         .long   OpEBmod2
6018                         .long   OpECX0mod2
6019                         .long   OpEDM1mod2
6020                         .long   OpEEM1mod2
6021                         .long   OpEFM1mod2
6022                         .long   OpF0mod2
6023                         .long   OpF1M1mod2
6024                         .long   OpF2M1mod2
6025                         .long   OpF3M1mod2
6026                         .long   OpF4mod2
6027                         .long   OpF5M1mod2
6028                         .long   OpF6M1mod2
6029                         .long   OpF7M1mod2
6030                         .long   OpF8mod2
6031                         .long   OpF9M1mod2
6032                         .long   OpFAX0mod2
6033                         .long   OpFBmod2
6034                         .long   OpFCmod2
6035                         .long   OpFDM1mod2
6036                         .long   OpFEM1mod2
6037                         .long   OpFFM1mod2
6038 Op00mod2:
6039 lbl00mod2:      Op00
6040                         NEXTOPCODE
6041 Op01M1mod2:
6042 lbl01mod2a:     DirectIndexedIndirect0
6043 lbl01mod2b:     ORA8
6044                         NEXTOPCODE
6045 Op02mod2:
6046 lbl02mod2:      Op02
6047                         NEXTOPCODE
6048 Op03M1mod2:
6049 lbl03mod2a:     StackasmRelative
6050 lbl03mod2b:     ORA8
6051                         NEXTOPCODE
6052 Op04M1mod2:
6053 lbl04mod2a:     Direct
6054 lbl04mod2b:     TSB8
6055                         NEXTOPCODE
6056 Op05M1mod2:
6057 lbl05mod2a:     Direct
6058 lbl05mod2b:     ORA8
6059                         NEXTOPCODE
6060 Op06M1mod2:
6061 lbl06mod2a:     Direct
6062 lbl06mod2b:     ASL8
6063                         NEXTOPCODE
6064 Op07M1mod2:
6065 lbl07mod2a:     DirectIndirectLong
6066 lbl07mod2b:     ORA8
6067                         NEXTOPCODE
6068 Op08mod2:
6069 lbl08mod2:      Op08
6070                         NEXTOPCODE
6071 Op09M1mod2:
6072 lbl09mod2:      Op09M1
6073                         NEXTOPCODE
6074 Op0AM1mod2:
6075 lbl0Amod2a:     A_ASL8
6076                         NEXTOPCODE
6077 Op0Bmod2:
6078 lbl0Bmod2:      Op0B
6079                         NEXTOPCODE
6080 Op0CM1mod2:
6081 lbl0Cmod2a:     Absolute
6082 lbl0Cmod2b:     TSB8
6083                         NEXTOPCODE
6084 Op0DM1mod2:
6085 lbl0Dmod2a:     Absolute
6086 lbl0Dmod2b:     ORA8
6087                         NEXTOPCODE
6088 Op0EM1mod2:
6089 lbl0Emod2a:     Absolute
6090 lbl0Emod2b:     ASL8
6091                         NEXTOPCODE
6092 Op0FM1mod2:
6093 lbl0Fmod2a:     AbsoluteLong
6094 lbl0Fmod2b:     ORA8
6095                         NEXTOPCODE
6096 Op10mod2:
6097 lbl10mod2:      Op10
6098                         NEXTOPCODE
6099 Op11M1mod2:
6100 lbl11mod2a:     DirectIndirectIndexed0
6101 lbl11mod2b:     ORA8
6102                         NEXTOPCODE
6103 Op12M1mod2:
6104 lbl12mod2a:     DirectIndirect
6105 lbl12mod2b:     ORA8
6106                         NEXTOPCODE
6107 Op13M1mod2:
6108 lbl13mod2a:     StackasmRelativeIndirectIndexed0
6109 lbl13mod2b:     ORA8
6110                         NEXTOPCODE
6111 Op14M1mod2:
6112 lbl14mod2a:     Direct
6113 lbl14mod2b:     TRB8
6114                         NEXTOPCODE
6115 Op15M1mod2:
6116 lbl15mod2a:     DirectIndexedX0
6117 lbl15mod2b:     ORA8
6118                         NEXTOPCODE
6119 Op16M1mod2:
6120 lbl16mod2a:     DirectIndexedX0
6121 lbl16mod2b:     ASL8
6122                         NEXTOPCODE
6123 Op17M1mod2:
6124 lbl17mod2a:     DirectIndirectIndexedLong0
6125 lbl17mod2b:     ORA8
6126                         NEXTOPCODE
6127 Op18mod2:
6128 lbl18mod2:      Op18
6129                         NEXTOPCODE
6130 Op19M1mod2:
6131 lbl19mod2a:     AbsoluteIndexedY0
6132 lbl19mod2b:     ORA8
6133                         NEXTOPCODE
6134 Op1AM1mod2:
6135 lbl1Amod2a:     A_INC8
6136                         NEXTOPCODE
6137 Op1Bmod2:
6138 lbl1Bmod2:      Op1BM1
6139                         NEXTOPCODE
6140 Op1CM1mod2:
6141 lbl1Cmod2a:     Absolute
6142 lbl1Cmod2b:     TRB8
6143                         NEXTOPCODE
6144 Op1DM1mod2:
6145 lbl1Dmod2a:     AbsoluteIndexedX0
6146 lbl1Dmod2b:     ORA8
6147                         NEXTOPCODE
6148 Op1EM1mod2:
6149 lbl1Emod2a:     AbsoluteIndexedX0
6150 lbl1Emod2b:     ASL8
6151                         NEXTOPCODE
6152 Op1FM1mod2:
6153 lbl1Fmod2a:     AbsoluteLongIndexedX0
6154 lbl1Fmod2b:     ORA8
6155                         NEXTOPCODE
6156 Op20mod2:
6157 lbl20mod2:      Op20
6158                         NEXTOPCODE
6159 Op21M1mod2:
6160 lbl21mod2a:     DirectIndexedIndirect0
6161 lbl21mod2b:     AND8
6162                         NEXTOPCODE
6163 Op22mod2:
6164 lbl22mod2:      Op22
6165                         NEXTOPCODE
6166 Op23M1mod2:
6167 lbl23mod2a:     StackasmRelative
6168 lbl23mod2b:     AND8
6169                         NEXTOPCODE
6170 Op24M1mod2:
6171 lbl24mod2a:     Direct
6172 lbl24mod2b:     BIT8
6173                         NEXTOPCODE
6174 Op25M1mod2:
6175 lbl25mod2a:     Direct
6176 lbl25mod2b:     AND8
6177                         NEXTOPCODE
6178 Op26M1mod2:
6179 lbl26mod2a:     Direct
6180 lbl26mod2b:     ROL8
6181                         NEXTOPCODE
6182 Op27M1mod2:
6183 lbl27mod2a:     DirectIndirectLong
6184 lbl27mod2b:     AND8
6185                         NEXTOPCODE
6186 Op28mod2:
6187 lbl28mod2:      Op28X0M1
6188                         NEXTOPCODE
6189 .pool
6190 Op29M1mod2:
6191 lbl29mod2:      Op29M1
6192                         NEXTOPCODE
6193 Op2AM1mod2:
6194 lbl2Amod2a:     A_ROL8
6195                         NEXTOPCODE
6196 Op2Bmod2:
6197 lbl2Bmod2:      Op2B
6198                         NEXTOPCODE
6199 Op2CM1mod2:
6200 lbl2Cmod2a:     Absolute
6201 lbl2Cmod2b:     BIT8
6202                         NEXTOPCODE
6203 Op2DM1mod2:
6204 lbl2Dmod2a:     Absolute
6205 lbl2Dmod2b:     AND8
6206                         NEXTOPCODE
6207 Op2EM1mod2:
6208 lbl2Emod2a:     Absolute
6209 lbl2Emod2b:     ROL8
6210                         NEXTOPCODE
6211 Op2FM1mod2:
6212 lbl2Fmod2a:     AbsoluteLong
6213 lbl2Fmod2b:     AND8
6214                         NEXTOPCODE
6215 Op30mod2:
6216 lbl30mod2:      Op30
6217                         NEXTOPCODE
6218 Op31M1mod2:
6219 lbl31mod2a:     DirectIndirectIndexed0
6220 lbl31mod2b:     AND8
6221                         NEXTOPCODE
6222 Op32M1mod2:
6223 lbl32mod2a:     DirectIndirect
6224 lbl32mod2b:     AND8
6225                         NEXTOPCODE
6226 Op33M1mod2:
6227 lbl33mod2a:     StackasmRelativeIndirectIndexed0
6228 lbl33mod2b:     AND8
6229                         NEXTOPCODE
6230 Op34M1mod2:
6231 lbl34mod2a:     DirectIndexedX0
6232 lbl34mod2b:     BIT8
6233                         NEXTOPCODE
6234 Op35M1mod2:
6235 lbl35mod2a:     DirectIndexedX0
6236 lbl35mod2b:     AND8
6237                         NEXTOPCODE
6238 Op36M1mod2:
6239 lbl36mod2a:     DirectIndexedX0
6240 lbl36mod2b:     ROL8
6241                         NEXTOPCODE
6242 Op37M1mod2:
6243 lbl37mod2a:     DirectIndirectIndexedLong0
6244 lbl37mod2b:     AND8
6245                         NEXTOPCODE
6246 Op38mod2:
6247 lbl38mod2:      Op38
6248                         NEXTOPCODE
6249 Op39M1mod2:
6250 lbl39mod2a:     AbsoluteIndexedY0
6251 lbl39mod2b:     AND8
6252                         NEXTOPCODE
6253 Op3AM1mod2:
6254 lbl3Amod2a:     A_DEC8
6255                         NEXTOPCODE
6256 Op3Bmod2:
6257 lbl3Bmod2:      Op3BM1
6258                         NEXTOPCODE
6259 Op3CM1mod2:
6260 lbl3Cmod2a:     AbsoluteIndexedX0
6261 lbl3Cmod2b:     BIT8
6262                         NEXTOPCODE
6263 Op3DM1mod2:
6264 lbl3Dmod2a:     AbsoluteIndexedX0
6265 lbl3Dmod2b:     AND8
6266                         NEXTOPCODE
6267 Op3EM1mod2:
6268 lbl3Emod2a:     AbsoluteIndexedX0
6269 lbl3Emod2b:     ROL8
6270                         NEXTOPCODE
6271 Op3FM1mod2:
6272 lbl3Fmod2a:     AbsoluteLongIndexedX0
6273 lbl3Fmod2b:     AND8
6274                         NEXTOPCODE
6275 Op40mod2:
6276 lbl40mod2:      Op40X0M1
6277                         NEXTOPCODE
6278 .pool
6279 Op41M1mod2:
6280 lbl41mod2a:     DirectIndexedIndirect0
6281 lbl41mod2b:     EOR8
6282                         NEXTOPCODE
6283 Op42mod2:
6284 lbl42mod2:      Op42
6285                         NEXTOPCODE
6286 Op43M1mod2:
6287 lbl43mod2a:     StackasmRelative
6288 lbl43mod2b:     EOR8
6289                         NEXTOPCODE
6290 Op44X0mod2:
6291 lbl44mod2:      Op44X0M1
6292                         NEXTOPCODE
6293 Op45M1mod2:
6294 lbl45mod2a:     Direct
6295 lbl45mod2b:     EOR8
6296                         NEXTOPCODE
6297 Op46M1mod2:
6298 lbl46mod2a:     Direct
6299 lbl46mod2b:     LSR8
6300                         NEXTOPCODE
6301 Op47M1mod2:
6302 lbl47mod2a:     DirectIndirectLong
6303 lbl47mod2b:     EOR8
6304                         NEXTOPCODE
6305 Op48M1mod2:
6306 lbl48mod2:      Op48M1
6307                         NEXTOPCODE
6308 Op49M1mod2:
6309 lbl49mod2:      Op49M1
6310                         NEXTOPCODE
6311 Op4AM1mod2:
6312 lbl4Amod2a:     A_LSR8
6313                         NEXTOPCODE
6314 Op4Bmod2:
6315 lbl4Bmod2:      Op4B
6316                         NEXTOPCODE
6317 Op4Cmod2:
6318 lbl4Cmod2:      Op4C
6319                         NEXTOPCODE
6320 Op4DM1mod2:
6321 lbl4Dmod2a:     Absolute
6322 lbl4Dmod2b:     EOR8
6323                         NEXTOPCODE
6324 Op4EM1mod2:
6325 lbl4Emod2a:     Absolute
6326 lbl4Emod2b:     LSR8
6327                         NEXTOPCODE
6328 Op4FM1mod2:
6329 lbl4Fmod2a:     AbsoluteLong
6330 lbl4Fmod2b:     EOR8
6331                         NEXTOPCODE
6332 Op50mod2:
6333 lbl50mod2:      Op50
6334                         NEXTOPCODE
6335 Op51M1mod2:
6336 lbl51mod2a:     DirectIndirectIndexed0
6337 lbl51mod2b:     EOR8
6338                         NEXTOPCODE
6339 Op52M1mod2:
6340 lbl52mod2a:     DirectIndirect
6341 lbl52mod2b:     EOR8
6342                         NEXTOPCODE
6343 Op53M1mod2:
6344 lbl53mod2a:     StackasmRelativeIndirectIndexed0
6345 lbl53mod2b:     EOR8
6346                         NEXTOPCODE
6347 Op54X0mod2:
6348 lbl54mod2:      Op54X0M1
6349                         NEXTOPCODE
6350 Op55M1mod2:
6351 lbl55mod2a:     DirectIndexedX0
6352 lbl55mod2b:     EOR8
6353                         NEXTOPCODE
6354 Op56M1mod2:
6355 lbl56mod2a:     DirectIndexedX0
6356 lbl56mod2b:     LSR8
6357                         NEXTOPCODE
6358 Op57M1mod2:
6359 lbl57mod2a:     DirectIndirectIndexedLong0
6360 lbl57mod2b:     EOR8
6361                         NEXTOPCODE
6362 Op58mod2:
6363 lbl58mod2:      Op58
6364                         NEXTOPCODE
6365 Op59M1mod2:
6366 lbl59mod2a:     AbsoluteIndexedY0
6367 lbl59mod2b:     EOR8
6368                         NEXTOPCODE
6369 Op5AX0mod2:
6370 lbl5Amod2:      Op5AX0
6371                         NEXTOPCODE
6372 Op5Bmod2:
6373 lbl5Bmod2:      Op5BM1
6374                         NEXTOPCODE
6375 Op5Cmod2:
6376 lbl5Cmod2:      Op5C
6377                         NEXTOPCODE
6378 Op5DM1mod2:
6379 lbl5Dmod2a:     AbsoluteIndexedX0
6380 lbl5Dmod2b:     EOR8
6381                         NEXTOPCODE
6382 Op5EM1mod2:
6383 lbl5Emod2a:     AbsoluteIndexedX0
6384 lbl5Emod2b:     LSR8
6385                         NEXTOPCODE
6386 Op5FM1mod2:
6387 lbl5Fmod2a:     AbsoluteLongIndexedX0
6388 lbl5Fmod2b:     EOR8
6389                         NEXTOPCODE
6390 Op60mod2:
6391 lbl60mod2:      Op60
6392                         NEXTOPCODE
6393 Op61M1mod2:
6394 lbl61mod2a:     DirectIndexedIndirect0
6395 lbl61mod2b:     ADC8
6396                         NEXTOPCODE
6397 Op62mod2:
6398 lbl62mod2:      Op62
6399                         NEXTOPCODE
6400 Op63M1mod2:
6401 lbl63mod2a:     StackasmRelative
6402 lbl63mod2b:     ADC8
6403                         NEXTOPCODE
6404 Op64M1mod2:
6405 lbl64mod2a:     Direct
6406 lbl64mod2b:     STZ8
6407                         NEXTOPCODE
6408 Op65M1mod2:
6409 lbl65mod2a:     Direct
6410 lbl65mod2b:     ADC8
6411                         NEXTOPCODE
6412 Op66M1mod2:
6413 lbl66mod2a:     Direct
6414 lbl66mod2b:     ROR8
6415                         NEXTOPCODE
6416 Op67M1mod2:
6417 lbl67mod2a:     DirectIndirectLong
6418 lbl67mod2b:     ADC8
6419                         NEXTOPCODE
6420 Op68M1mod2:
6421 lbl68mod2:      Op68M1
6422                         NEXTOPCODE
6423 Op69M1mod2:
6424 lbl69mod2a:     Immediate8
6425 lbl69mod2b:     ADC8
6426                         NEXTOPCODE
6427 Op6AM1mod2:
6428 lbl6Amod2a:     A_ROR8
6429                         NEXTOPCODE
6430 Op6Bmod2:
6431 lbl6Bmod2:      Op6B
6432                         NEXTOPCODE
6433 Op6Cmod2:
6434 lbl6Cmod2:      Op6C
6435                         NEXTOPCODE
6436 Op6DM1mod2:
6437 lbl6Dmod2a:     Absolute
6438 lbl6Dmod2b:     ADC8
6439                         NEXTOPCODE
6440 Op6EM1mod2:
6441 lbl6Emod2a:     Absolute
6442 lbl6Emod2b:     ROR8
6443                         NEXTOPCODE
6444 Op6FM1mod2:
6445 lbl6Fmod2a:     AbsoluteLong
6446 lbl6Fmod2b:     ADC8
6447                         NEXTOPCODE
6448 Op70mod2:
6449 lbl70mod2:      Op70
6450                         NEXTOPCODE
6451 Op71M1mod2:
6452 lbl71mod2a:     DirectIndirectIndexed0
6453 lbl71mod2b:     ADC8
6454                         NEXTOPCODE
6455 Op72M1mod2:
6456 lbl72mod2a:     DirectIndirect
6457 lbl72mod2b:     ADC8
6458                         NEXTOPCODE
6459 Op73M1mod2:
6460 lbl73mod2a:     StackasmRelativeIndirectIndexed0
6461 lbl73mod2b:     ADC8
6462                         NEXTOPCODE
6463 Op74M1mod2:
6464 lbl74mod2a:     DirectIndexedX0
6465 lbl74mod2b:     STZ8
6466                         NEXTOPCODE
6467 Op75M1mod2:
6468 lbl75mod2a:     DirectIndexedX0
6469 lbl75mod2b:     ADC8
6470                         NEXTOPCODE
6471 Op76M1mod2:
6472 lbl76mod2a:     DirectIndexedX0
6473 lbl76mod2b:     ROR8
6474                         NEXTOPCODE
6475 Op77M1mod2:
6476 lbl77mod2a:     DirectIndirectIndexedLong0
6477 lbl77mod2b:     ADC8
6478                         NEXTOPCODE
6479 Op78mod2:
6480 lbl78mod2:      Op78
6481                         NEXTOPCODE
6482 Op79M1mod2:
6483 lbl79mod2a:     AbsoluteIndexedY0
6484 lbl79mod2b:     ADC8
6485                         NEXTOPCODE
6486 Op7AX0mod2:
6487 lbl7Amod2:      Op7AX0
6488                         NEXTOPCODE
6489 Op7Bmod2:
6490 lbl7Bmod2:      Op7BM1
6491                         NEXTOPCODE
6492 Op7Cmod2:
6493 lbl7Cmod2:      AbsoluteIndexedIndirectX0
6494                 Op7C
6495                         NEXTOPCODE
6496 Op7DM1mod2:
6497 lbl7Dmod2a:     AbsoluteIndexedX0
6498 lbl7Dmod2b:     ADC8
6499                         NEXTOPCODE
6500 Op7EM1mod2:
6501 lbl7Emod2a:     AbsoluteIndexedX0
6502 lbl7Emod2b:     ROR8
6503                         NEXTOPCODE
6504 Op7FM1mod2:
6505 lbl7Fmod2a:     AbsoluteLongIndexedX0
6506 lbl7Fmod2b:     ADC8
6507                         NEXTOPCODE
6508
6509
6510 Op80mod2:
6511 lbl80mod2:      Op80
6512                         NEXTOPCODE
6513 Op81M1mod2:
6514 lbl81mod2a:     DirectIndexedIndirect0
6515 lbl81mod2b:     Op81M1
6516                         NEXTOPCODE
6517 Op82mod2:
6518 lbl82mod2:      Op82
6519                         NEXTOPCODE
6520 Op83M1mod2:
6521 lbl83mod2a:     StackasmRelative
6522 lbl83mod2b:     STA8
6523                         NEXTOPCODE
6524 Op84X0mod2:
6525 lbl84mod2a:     Direct
6526 lbl84mod2b:     STY16
6527                         NEXTOPCODE
6528 Op85M1mod2:
6529 lbl85mod2a:     Direct
6530 lbl85mod2b:     STA8
6531                         NEXTOPCODE
6532 Op86X0mod2:
6533 lbl86mod2a:     Direct
6534 lbl86mod2b:     STX16
6535                         NEXTOPCODE
6536 Op87M1mod2:
6537 lbl87mod2a:     DirectIndirectLong
6538 lbl87mod2b:     STA8
6539                         NEXTOPCODE
6540 Op88X0mod2:
6541 lbl88mod2:      Op88X0
6542                         NEXTOPCODE
6543 Op89M1mod2:
6544 lbl89mod2:      Op89M1
6545                         NEXTOPCODE
6546 Op8AM1mod2:
6547 lbl8Amod2:      Op8AM1X0
6548                         NEXTOPCODE
6549 Op8Bmod2:
6550 lbl8Bmod2:      Op8B
6551                         NEXTOPCODE
6552 Op8CX0mod2:
6553 lbl8Cmod2a:     Absolute
6554 lbl8Cmod2b:     STY16
6555                         NEXTOPCODE
6556 Op8DM1mod2:
6557 lbl8Dmod2a:     Absolute
6558 lbl8Dmod2b:     STA8
6559                         NEXTOPCODE
6560 Op8EX0mod2:
6561 lbl8Emod2a:     Absolute
6562 lbl8Emod2b:     STX16
6563                         NEXTOPCODE
6564 Op8FM1mod2:
6565 lbl8Fmod2a:     AbsoluteLong
6566 lbl8Fmod2b:     STA8
6567                         NEXTOPCODE
6568 Op90mod2:
6569 lbl90mod2:      Op90
6570                         NEXTOPCODE
6571 Op91M1mod2:
6572 lbl91mod2a:     DirectIndirectIndexed0
6573 lbl91mod2b:     STA8
6574                         NEXTOPCODE
6575 Op92M1mod2:
6576 lbl92mod2a:     DirectIndirect
6577 lbl92mod2b:     STA8
6578                         NEXTOPCODE
6579 Op93M1mod2:
6580 lbl93mod2a:     StackasmRelativeIndirectIndexed0
6581 lbl93mod2b:     STA8
6582                         NEXTOPCODE
6583 Op94X0mod2:
6584 lbl94mod2a:     DirectIndexedX0
6585 lbl94mod2b:     STY16
6586                         NEXTOPCODE
6587 Op95M1mod2:
6588 lbl95mod2a:     DirectIndexedX0
6589 lbl95mod2b:     STA8
6590                         NEXTOPCODE
6591 Op96X0mod2:
6592 lbl96mod2a:     DirectIndexedY0
6593 lbl96mod2b:     STX16
6594                         NEXTOPCODE
6595 Op97M1mod2:
6596 lbl97mod2a:     DirectIndirectIndexedLong0
6597 lbl97mod2b:     STA8
6598                         NEXTOPCODE
6599 Op98M1mod2:
6600 lbl98mod2:      Op98M1X0
6601                         NEXTOPCODE
6602 Op99M1mod2:
6603 lbl99mod2a:     AbsoluteIndexedY0
6604 lbl99mod2b:     STA8
6605                         NEXTOPCODE
6606 Op9Amod2:
6607 lbl9Amod2:      Op9AX0
6608                         NEXTOPCODE
6609 Op9BX0mod2:
6610 lbl9Bmod2:      Op9BX0
6611                         NEXTOPCODE
6612 Op9CM1mod2:
6613 lbl9Cmod2a:     Absolute
6614 lbl9Cmod2b:     STZ8
6615                         NEXTOPCODE
6616 Op9DM1mod2:
6617 lbl9Dmod2a:     AbsoluteIndexedX0
6618 lbl9Dmod2b:     STA8
6619                         NEXTOPCODE
6620 Op9EM1mod2:
6621 lbl9Emod2:      AbsoluteIndexedX0
6622                 STZ8
6623                         NEXTOPCODE
6624 Op9FM1mod2:
6625 lbl9Fmod2a:     AbsoluteLongIndexedX0
6626 lbl9Fmod2b:     STA8
6627                         NEXTOPCODE
6628 OpA0X0mod2:
6629 lblA0mod2:      OpA0X0
6630                         NEXTOPCODE
6631 OpA1M1mod2:
6632 lblA1mod2a:     DirectIndexedIndirect0
6633 lblA1mod2b:     LDA8
6634                         NEXTOPCODE
6635 OpA2X0mod2:
6636 lblA2mod2:      OpA2X0
6637                         NEXTOPCODE
6638 OpA3M1mod2:
6639 lblA3mod2a:     StackasmRelative
6640 lblA3mod2b:     LDA8
6641                         NEXTOPCODE
6642 OpA4X0mod2:
6643 lblA4mod2a:     Direct
6644 lblA4mod2b:     LDY16
6645                         NEXTOPCODE
6646 OpA5M1mod2:
6647 lblA5mod2a:     Direct
6648 lblA5mod2b:     LDA8
6649                         NEXTOPCODE
6650 OpA6X0mod2:
6651 lblA6mod2a:     Direct
6652 lblA6mod2b:     LDX16
6653                         NEXTOPCODE
6654 OpA7M1mod2:
6655 lblA7mod2a:     DirectIndirectLong
6656 lblA7mod2b:     LDA8
6657                         NEXTOPCODE
6658 OpA8X0mod2:
6659 lblA8mod2:      OpA8X0M1
6660                         NEXTOPCODE
6661 OpA9M1mod2:
6662 lblA9mod2:      OpA9M1
6663                         NEXTOPCODE
6664 OpAAX0mod2:
6665 lblAAmod2:      OpAAX0M1
6666                         NEXTOPCODE
6667 OpABmod2:
6668 lblABmod2:      OpAB
6669                         NEXTOPCODE
6670 OpACX0mod2:
6671 lblACmod2a:     Absolute
6672 lblACmod2b:     LDY16
6673                         NEXTOPCODE
6674 OpADM1mod2:
6675 lblADmod2a:     Absolute
6676 lblADmod2b:     LDA8
6677                         NEXTOPCODE
6678 OpAEX0mod2:
6679 lblAEmod2a:     Absolute
6680 lblAEmod2b:     LDX16
6681                         NEXTOPCODE
6682 OpAFM1mod2:
6683 lblAFmod2a:     AbsoluteLong
6684 lblAFmod2b:     LDA8
6685                         NEXTOPCODE
6686 OpB0mod2:
6687 lblB0mod2:      OpB0
6688                         NEXTOPCODE
6689 OpB1M1mod2:
6690 lblB1mod2a:     DirectIndirectIndexed0
6691 lblB1mod2b:     LDA8
6692                         NEXTOPCODE
6693 OpB2M1mod2:
6694 lblB2mod2a:     DirectIndirect
6695 lblB2mod2b:     LDA8
6696                         NEXTOPCODE
6697 OpB3M1mod2:
6698 lblB3mod2a:     StackasmRelativeIndirectIndexed0
6699 lblB3mod2b:     LDA8
6700                         NEXTOPCODE
6701 OpB4X0mod2:
6702 lblB4mod2a:     DirectIndexedX0
6703 lblB4mod2b:     LDY16
6704                         NEXTOPCODE
6705 OpB5M1mod2:
6706 lblB5mod2a:     DirectIndexedX0
6707 lblB5mod2b:     LDA8
6708                         NEXTOPCODE
6709 OpB6X0mod2:
6710 lblB6mod2a:     DirectIndexedY0
6711 lblB6mod2b:     LDX16
6712                         NEXTOPCODE
6713 OpB7M1mod2:
6714 lblB7mod2a:     DirectIndirectIndexedLong0
6715 lblB7mod2b:     LDA8
6716                         NEXTOPCODE
6717 OpB8mod2:
6718 lblB8mod2:      OpB8
6719                         NEXTOPCODE
6720 OpB9M1mod2:
6721 lblB9mod2a:     AbsoluteIndexedY0
6722 lblB9mod2b:     LDA8
6723                         NEXTOPCODE
6724 OpBAX0mod2:
6725 lblBAmod2:      OpBAX0
6726                         NEXTOPCODE
6727 OpBBX0mod2:
6728 lblBBmod2:      OpBBX0
6729                         NEXTOPCODE
6730 OpBCX0mod2:
6731 lblBCmod2a:     AbsoluteIndexedX0
6732 lblBCmod2b:     LDY16
6733                         NEXTOPCODE
6734 OpBDM1mod2:
6735 lblBDmod2a:     AbsoluteIndexedX0
6736 lblBDmod2b:     LDA8
6737                         NEXTOPCODE
6738 OpBEX0mod2:
6739 lblBEmod2a:     AbsoluteIndexedY0
6740 lblBEmod2b:     LDX16
6741                         NEXTOPCODE
6742 OpBFM1mod2:
6743 lblBFmod2a:     AbsoluteLongIndexedX0
6744 lblBFmod2b:     LDA8
6745                         NEXTOPCODE
6746 OpC0X0mod2:
6747 lblC0mod2:      OpC0X0
6748                         NEXTOPCODE
6749 OpC1M1mod2:
6750 lblC1mod2a:     DirectIndexedIndirect0
6751 lblC1mod2b:     CMP8
6752                         NEXTOPCODE
6753 OpC2mod2:
6754 lblC2mod2:      OpC2
6755                         NEXTOPCODE
6756 .pool
6757 OpC3M1mod2:
6758 lblC3mod2a:     StackasmRelative
6759 lblC3mod2b:     CMP8
6760                         NEXTOPCODE
6761 OpC4X0mod2:
6762 lblC4mod2a:     Direct
6763 lblC4mod2b:     CMY16
6764                         NEXTOPCODE
6765 OpC5M1mod2:
6766 lblC5mod2a:     Direct
6767 lblC5mod2b:     CMP8
6768                         NEXTOPCODE
6769 OpC6M1mod2:
6770 lblC6mod2a:     Direct
6771 lblC6mod2b:     DEC8
6772                         NEXTOPCODE
6773 OpC7M1mod2:
6774 lblC7mod2a:     DirectIndirectLong
6775 lblC7mod2b:     CMP8
6776                         NEXTOPCODE
6777 OpC8X0mod2:
6778 lblC8mod2:      OpC8X0
6779                         NEXTOPCODE
6780 OpC9M1mod2:
6781 lblC9mod2:      OpC9M1
6782                         NEXTOPCODE
6783 OpCAX0mod2:
6784 lblCAmod2:      OpCAX0
6785                         NEXTOPCODE
6786 OpCBmod2:
6787 lblCBmod2:      OpCB
6788                         NEXTOPCODE
6789 OpCCX0mod2:
6790 lblCCmod2a:     Absolute
6791 lblCCmod2b:     CMY16
6792                         NEXTOPCODE
6793 OpCDM1mod2:
6794 lblCDmod2a:     Absolute
6795 lblCDmod2b:     CMP8
6796                         NEXTOPCODE
6797 OpCEM1mod2:
6798 lblCEmod2a:     Absolute
6799 lblCEmod2b:     DEC8
6800                         NEXTOPCODE
6801 OpCFM1mod2:
6802 lblCFmod2a:     AbsoluteLong
6803 lblCFmod2b:     CMP8
6804                         NEXTOPCODE
6805 OpD0mod2:
6806 lblD0mod2:      OpD0
6807                         NEXTOPCODE
6808 OpD1M1mod2:
6809 lblD1mod2a:     DirectIndirectIndexed0
6810 lblD1mod2b:     CMP8
6811                         NEXTOPCODE
6812 OpD2M1mod2:
6813 lblD2mod2a:     DirectIndirect
6814 lblD2mod2b:     CMP8
6815                         NEXTOPCODE
6816 OpD3M1mod2:
6817 lblD3mod2a:     StackasmRelativeIndirectIndexed0
6818 lblD3mod2b:     CMP8
6819                         NEXTOPCODE
6820 OpD4mod2:
6821 lblD4mod2:      OpD4
6822                         NEXTOPCODE
6823 OpD5M1mod2:
6824 lblD5mod2a:     DirectIndexedX0
6825 lblD5mod2b:     CMP8
6826                         NEXTOPCODE
6827 OpD6M1mod2:
6828 lblD6mod2a:     DirectIndexedX0
6829 lblD6mod2b:     DEC8
6830                         NEXTOPCODE
6831 OpD7M1mod2:
6832 lblD7mod2a:     DirectIndirectIndexedLong0
6833 lblD7mod2b:     CMP8
6834                         NEXTOPCODE
6835 OpD8mod2:
6836 lblD8mod2:      OpD8
6837                         NEXTOPCODE
6838 OpD9M1mod2:
6839 lblD9mod2a:     AbsoluteIndexedY0
6840 lblD9mod2b:     CMP8
6841                         NEXTOPCODE
6842 OpDAX0mod2:
6843 lblDAmod2:      OpDAX0
6844                         NEXTOPCODE
6845 OpDBmod2:
6846 lblDBmod2:      OpDB
6847                         NEXTOPCODE
6848 OpDCmod2:
6849 lblDCmod2:      OpDC
6850                         NEXTOPCODE
6851 OpDDM1mod2:
6852 lblDDmod2a:     AbsoluteIndexedX0
6853 lblDDmod2b:     CMP8
6854                         NEXTOPCODE
6855 OpDEM1mod2:
6856 lblDEmod2a:     AbsoluteIndexedX0
6857 lblDEmod2b:     DEC8
6858                         NEXTOPCODE
6859 OpDFM1mod2:
6860 lblDFmod2a:     AbsoluteLongIndexedX0
6861 lblDFmod2b:     CMP8
6862                         NEXTOPCODE
6863 OpE0X0mod2:
6864 lblE0mod2:      OpE0X0
6865                         NEXTOPCODE
6866 OpE1M1mod2:
6867 lblE1mod2a:     DirectIndexedIndirect0
6868 lblE1mod2b:     SBC8
6869                         NEXTOPCODE
6870 OpE2mod2:
6871 lblE2mod2:      OpE2
6872                         NEXTOPCODE
6873 .pool
6874 OpE3M1mod2:
6875 lblE3mod2a:     StackasmRelative
6876 lblE3mod2b:     SBC8
6877                         NEXTOPCODE
6878 OpE4X0mod2:
6879 lblE4mod2a:     Direct
6880 lblE4mod2b:     CMX16
6881                         NEXTOPCODE
6882 OpE5M1mod2:
6883 lblE5mod2a:     Direct
6884 lblE5mod2b:     SBC8
6885                         NEXTOPCODE
6886 OpE6M1mod2:
6887 lblE6mod2a:     Direct
6888 lblE6mod2b:     INC8
6889                         NEXTOPCODE
6890 OpE7M1mod2:
6891 lblE7mod2a:     DirectIndirectLong
6892 lblE7mod2b:     SBC8
6893                         NEXTOPCODE
6894 OpE8X0mod2:
6895 lblE8mod2:      OpE8X0
6896                         NEXTOPCODE
6897 OpE9M1mod2:
6898 lblE9mod2a:     Immediate8
6899 lblE9mod2b:     SBC8
6900                         NEXTOPCODE
6901 OpEAmod2:
6902 lblEAmod2:      OpEA
6903                         NEXTOPCODE
6904 OpEBmod2:
6905 lblEBmod2:      OpEBM1
6906                         NEXTOPCODE
6907 OpECX0mod2:
6908 lblECmod2a:     Absolute
6909 lblECmod2b:     CMX16
6910                         NEXTOPCODE
6911 OpEDM1mod2:
6912 lblEDmod2a:     Absolute
6913 lblEDmod2b:     SBC8
6914                         NEXTOPCODE
6915 OpEEM1mod2:
6916 lblEEmod2a:     Absolute
6917 lblEEmod2b:     INC8
6918                         NEXTOPCODE
6919 OpEFM1mod2:
6920 lblEFmod2a:     AbsoluteLong
6921 lblEFmod2b:     SBC8
6922                         NEXTOPCODE
6923 OpF0mod2:
6924 lblF0mod2:      OpF0
6925                         NEXTOPCODE
6926 OpF1M1mod2:
6927 lblF1mod2a:     DirectIndirectIndexed0
6928 lblF1mod2b:     SBC8
6929                         NEXTOPCODE
6930 OpF2M1mod2:
6931 lblF2mod2a:     DirectIndirect
6932 lblF2mod2b:     SBC8
6933                         NEXTOPCODE
6934 OpF3M1mod2:
6935 lblF3mod2a:     StackasmRelativeIndirectIndexed0
6936 lblF3mod2b:     SBC8
6937                         NEXTOPCODE
6938 OpF4mod2:
6939 lblF4mod2:      OpF4
6940                         NEXTOPCODE
6941 OpF5M1mod2:
6942 lblF5mod2a:     DirectIndexedX0
6943 lblF5mod2b:     SBC8
6944                         NEXTOPCODE
6945 OpF6M1mod2:
6946 lblF6mod2a:     DirectIndexedX0
6947 lblF6mod2b:     INC8
6948                         NEXTOPCODE
6949 OpF7M1mod2:
6950 lblF7mod2a:     DirectIndirectIndexedLong0
6951 lblF7mod2b:     SBC8
6952                         NEXTOPCODE
6953 OpF8mod2:
6954 lblF8mod2:      OpF8
6955                         NEXTOPCODE
6956 OpF9M1mod2:
6957 lblF9mod2a:     AbsoluteIndexedY0
6958 lblF9mod2b:     SBC8
6959                         NEXTOPCODE
6960 OpFAX0mod2:
6961 lblFAmod2:      OpFAX0
6962                         NEXTOPCODE
6963 OpFBmod2:
6964 lblFBmod2:      OpFB
6965                         NEXTOPCODE
6966 OpFCmod2:
6967 lblFCmod2:      OpFCX0
6968                         NEXTOPCODE
6969 OpFDM1mod2:
6970 lblFDmod2a:     AbsoluteIndexedX0
6971 lblFDmod2b:     SBC8
6972                         NEXTOPCODE
6973 OpFEM1mod2:
6974 lblFEmod2a:     AbsoluteIndexedX0
6975 lblFEmod2b:     INC8
6976                         NEXTOPCODE
6977 OpFFM1mod2:
6978 lblFFmod2a:     AbsoluteLongIndexedX0
6979 lblFFmod2b:     SBC8
6980                         NEXTOPCODE
6981
6982 .pool
6983
6984
6985 jumptable3:             .long   Op00mod3
6986                         .long   Op01M0mod3
6987                         .long   Op02mod3
6988                         .long   Op03M0mod3
6989                         .long   Op04M0mod3
6990                         .long   Op05M0mod3
6991                         .long   Op06M0mod3
6992                         .long   Op07M0mod3
6993                         .long   Op08mod3
6994                         .long   Op09M0mod3
6995                         .long   Op0AM0mod3
6996                         .long   Op0Bmod3
6997                         .long   Op0CM0mod3
6998                         .long   Op0DM0mod3
6999                         .long   Op0EM0mod3
7000                         .long   Op0FM0mod3
7001                         .long   Op10mod3
7002                         .long   Op11M0mod3
7003                         .long   Op12M0mod3
7004                         .long   Op13M0mod3
7005                         .long   Op14M0mod3
7006                         .long   Op15M0mod3
7007                         .long   Op16M0mod3
7008                         .long   Op17M0mod3
7009                         .long   Op18mod3
7010                         .long   Op19M0mod3
7011                         .long   Op1AM0mod3
7012                         .long   Op1Bmod3
7013                         .long   Op1CM0mod3
7014                         .long   Op1DM0mod3
7015                         .long   Op1EM0mod3
7016                         .long   Op1FM0mod3
7017                         .long   Op20mod3
7018                         .long   Op21M0mod3
7019                         .long   Op22mod3
7020                         .long   Op23M0mod3
7021                         .long   Op24M0mod3
7022                         .long   Op25M0mod3
7023                         .long   Op26M0mod3
7024                         .long   Op27M0mod3
7025                         .long   Op28mod3
7026                         .long   Op29M0mod3
7027                         .long   Op2AM0mod3
7028                         .long   Op2Bmod3
7029                         .long   Op2CM0mod3
7030                         .long   Op2DM0mod3
7031                         .long   Op2EM0mod3
7032                         .long   Op2FM0mod3
7033                         .long   Op30mod3
7034                         .long   Op31M0mod3
7035                         .long   Op32M0mod3
7036                         .long   Op33M0mod3
7037                         .long   Op34M0mod3
7038                         .long   Op35M0mod3
7039                         .long   Op36M0mod3
7040                         .long   Op37M0mod3
7041                         .long   Op38mod3
7042                         .long   Op39M0mod3
7043                         .long   Op3AM0mod3
7044                         .long   Op3Bmod3
7045                         .long   Op3CM0mod3
7046                         .long   Op3DM0mod3
7047                         .long   Op3EM0mod3
7048                         .long   Op3FM0mod3
7049                         .long   Op40mod3
7050                         .long   Op41M0mod3
7051                         .long   Op42mod3
7052                         .long   Op43M0mod3
7053                         .long   Op44X0mod3
7054                         .long   Op45M0mod3
7055                         .long   Op46M0mod3
7056                         .long   Op47M0mod3
7057                         .long   Op48M0mod3
7058                         .long   Op49M0mod3
7059                         .long   Op4AM0mod3
7060                         .long   Op4Bmod3
7061                         .long   Op4Cmod3
7062                         .long   Op4DM0mod3
7063                         .long   Op4EM0mod3
7064                         .long   Op4FM0mod3
7065                         .long   Op50mod3
7066                         .long   Op51M0mod3
7067                         .long   Op52M0mod3
7068                         .long   Op53M0mod3
7069                         .long   Op54X0mod3
7070                         .long   Op55M0mod3
7071                         .long   Op56M0mod3
7072                         .long   Op57M0mod3
7073                         .long   Op58mod3
7074                         .long   Op59M0mod3
7075                         .long   Op5AX0mod3
7076                         .long   Op5Bmod3
7077                         .long   Op5Cmod3
7078                         .long   Op5DM0mod3
7079                         .long   Op5EM0mod3
7080                         .long   Op5FM0mod3
7081                         .long   Op60mod3
7082                         .long   Op61M0mod3
7083                         .long   Op62mod3
7084                         .long   Op63M0mod3
7085                         .long   Op64M0mod3
7086                         .long   Op65M0mod3
7087                         .long   Op66M0mod3
7088                         .long   Op67M0mod3
7089                         .long   Op68M0mod3
7090                         .long   Op69M0mod3
7091                         .long   Op6AM0mod3
7092                         .long   Op6Bmod3
7093                         .long   Op6Cmod3
7094                         .long   Op6DM0mod3
7095                         .long   Op6EM0mod3
7096                         .long   Op6FM0mod3
7097                         .long   Op70mod3
7098                         .long   Op71M0mod3
7099                         .long   Op72M0mod3
7100                         .long   Op73M0mod3
7101                         .long   Op74M0mod3
7102                         .long   Op75M0mod3
7103                         .long   Op76M0mod3
7104                         .long   Op77M0mod3
7105                         .long   Op78mod3
7106                         .long   Op79M0mod3
7107                         .long   Op7AX0mod3
7108                         .long   Op7Bmod3
7109                         .long   Op7Cmod3
7110                         .long   Op7DM0mod3
7111                         .long   Op7EM0mod3
7112                         .long   Op7FM0mod3
7113                         .long   Op80mod3
7114                         .long   Op81M0mod3
7115                         .long   Op82mod3
7116                         .long   Op83M0mod3
7117                         .long   Op84X0mod3
7118                         .long   Op85M0mod3
7119                         .long   Op86X0mod3
7120                         .long   Op87M0mod3
7121                         .long   Op88X0mod3
7122                         .long   Op89M0mod3
7123                         .long   Op8AM0mod3
7124                         .long   Op8Bmod3
7125                         .long   Op8CX0mod3
7126                         .long   Op8DM0mod3
7127                         .long   Op8EX0mod3
7128                         .long   Op8FM0mod3
7129                         .long   Op90mod3
7130                         .long   Op91M0mod3
7131                         .long   Op92M0mod3
7132                         .long   Op93M0mod3
7133                         .long   Op94X0mod3
7134                         .long   Op95M0mod3
7135                         .long   Op96X0mod3
7136                         .long   Op97M0mod3
7137                         .long   Op98M0mod3
7138                         .long   Op99M0mod3
7139                         .long   Op9Amod3
7140                         .long   Op9BX0mod3
7141                         .long   Op9CM0mod3
7142                         .long   Op9DM0mod3
7143                         .long   Op9EM0mod3
7144                         .long   Op9FM0mod3
7145                         .long   OpA0X0mod3
7146                         .long   OpA1M0mod3
7147                         .long   OpA2X0mod3
7148                         .long   OpA3M0mod3
7149                         .long   OpA4X0mod3
7150                         .long   OpA5M0mod3
7151                         .long   OpA6X0mod3
7152                         .long   OpA7M0mod3
7153                         .long   OpA8X0mod3
7154                         .long   OpA9M0mod3
7155                         .long   OpAAX0mod3
7156                         .long   OpABmod3
7157                         .long   OpACX0mod3
7158                         .long   OpADM0mod3
7159                         .long   OpAEX0mod3
7160                         .long   OpAFM0mod3
7161                         .long   OpB0mod3
7162                         .long   OpB1M0mod3
7163                         .long   OpB2M0mod3
7164                         .long   OpB3M0mod3
7165                         .long   OpB4X0mod3
7166                         .long   OpB5M0mod3
7167                         .long   OpB6X0mod3
7168                         .long   OpB7M0mod3
7169                         .long   OpB8mod3
7170                         .long   OpB9M0mod3
7171                         .long   OpBAX0mod3
7172                         .long   OpBBX0mod3
7173                         .long   OpBCX0mod3
7174                         .long   OpBDM0mod3
7175                         .long   OpBEX0mod3
7176                         .long   OpBFM0mod3
7177                         .long   OpC0X0mod3
7178                         .long   OpC1M0mod3
7179                         .long   OpC2mod3
7180                         .long   OpC3M0mod3
7181                         .long   OpC4X0mod3
7182                         .long   OpC5M0mod3
7183                         .long   OpC6M0mod3
7184                         .long   OpC7M0mod3
7185                         .long   OpC8X0mod3
7186                         .long   OpC9M0mod3
7187                         .long   OpCAX0mod3
7188                         .long   OpCBmod3
7189                         .long   OpCCX0mod3
7190                         .long   OpCDM0mod3
7191                         .long   OpCEM0mod3
7192                         .long   OpCFM0mod3
7193                         .long   OpD0mod3
7194                         .long   OpD1M0mod3
7195                         .long   OpD2M0mod3
7196                         .long   OpD3M0mod3
7197                         .long   OpD4mod3
7198                         .long   OpD5M0mod3
7199                         .long   OpD6M0mod3
7200                         .long   OpD7M0mod3
7201                         .long   OpD8mod3
7202                         .long   OpD9M0mod3
7203                         .long   OpDAX0mod3
7204                         .long   OpDBmod3
7205                         .long   OpDCmod3
7206                         .long   OpDDM0mod3
7207                         .long   OpDEM0mod3
7208                         .long   OpDFM0mod3
7209                         .long   OpE0X0mod3
7210                         .long   OpE1M0mod3
7211                         .long   OpE2mod3
7212                         .long   OpE3M0mod3
7213                         .long   OpE4X0mod3
7214                         .long   OpE5M0mod3
7215                         .long   OpE6M0mod3
7216                         .long   OpE7M0mod3
7217                         .long   OpE8X0mod3
7218                         .long   OpE9M0mod3
7219                         .long   OpEAmod3
7220                         .long   OpEBmod3
7221                         .long   OpECX0mod3
7222                         .long   OpEDM0mod3
7223                         .long   OpEEM0mod3
7224                         .long   OpEFM0mod3
7225                         .long   OpF0mod3
7226                         .long   OpF1M0mod3
7227                         .long   OpF2M0mod3
7228                         .long   OpF3M0mod3
7229                         .long   OpF4mod3
7230                         .long   OpF5M0mod3
7231                         .long   OpF6M0mod3
7232                         .long   OpF7M0mod3
7233                         .long   OpF8mod3
7234                         .long   OpF9M0mod3
7235                         .long   OpFAX0mod3
7236                         .long   OpFBmod3
7237                         .long   OpFCmod3
7238                         .long   OpFDM0mod3
7239                         .long   OpFEM0mod3
7240                         .long   OpFFM0mod3
7241 Op00mod3:
7242 lbl00mod3:      Op00
7243                         NEXTOPCODE
7244 Op01M0mod3:
7245 lbl01mod3a:     DirectIndexedIndirect0
7246 lbl01mod3b:     ORA16
7247                         NEXTOPCODE
7248 Op02mod3:
7249 lbl02mod3:      Op02
7250                         NEXTOPCODE
7251 Op03M0mod3:
7252 lbl03mod3a:     StackasmRelative
7253 lbl03mod3b:     ORA16
7254                         NEXTOPCODE
7255 Op04M0mod3:
7256 lbl04mod3a:     Direct
7257 lbl04mod3b:     TSB16
7258                         NEXTOPCODE
7259 Op05M0mod3:
7260 lbl05mod3a:     Direct
7261 lbl05mod3b:     ORA16
7262                         NEXTOPCODE
7263 Op06M0mod3:
7264 lbl06mod3a:     Direct
7265 lbl06mod3b:     ASL16
7266                         NEXTOPCODE
7267 Op07M0mod3:
7268 lbl07mod3a:     DirectIndirectLong
7269 lbl07mod3b:     ORA16
7270                         NEXTOPCODE
7271 Op08mod3:
7272 lbl08mod3:      Op08
7273                         NEXTOPCODE
7274 Op09M0mod3:
7275 lbl09mod3:      Op09M0
7276                         NEXTOPCODE
7277 Op0AM0mod3:
7278 lbl0Amod3a:     A_ASL16
7279                         NEXTOPCODE
7280 Op0Bmod3:
7281 lbl0Bmod3:      Op0B
7282                         NEXTOPCODE
7283 Op0CM0mod3:
7284 lbl0Cmod3a:     Absolute
7285 lbl0Cmod3b:     TSB16
7286                         NEXTOPCODE
7287 Op0DM0mod3:
7288 lbl0Dmod3a:     Absolute
7289 lbl0Dmod3b:     ORA16
7290                         NEXTOPCODE
7291 Op0EM0mod3:
7292 lbl0Emod3a:     Absolute
7293 lbl0Emod3b:     ASL16
7294                         NEXTOPCODE
7295 Op0FM0mod3:
7296 lbl0Fmod3a:     AbsoluteLong
7297 lbl0Fmod3b:     ORA16
7298                         NEXTOPCODE
7299 Op10mod3:
7300 lbl10mod3:      Op10
7301                         NEXTOPCODE
7302 Op11M0mod3:
7303 lbl11mod3a:     DirectIndirectIndexed0
7304 lbl11mod3b:     ORA16
7305                         NEXTOPCODE
7306 Op12M0mod3:
7307 lbl12mod3a:     DirectIndirect
7308 lbl12mod3b:     ORA16
7309                         NEXTOPCODE
7310 Op13M0mod3:
7311 lbl13mod3a:     StackasmRelativeIndirectIndexed0
7312 lbl13mod3b:     ORA16
7313                         NEXTOPCODE
7314 Op14M0mod3:
7315 lbl14mod3a:     Direct
7316 lbl14mod3b:     TRB16
7317                         NEXTOPCODE
7318 Op15M0mod3:
7319 lbl15mod3a:     DirectIndexedX0
7320 lbl15mod3b:     ORA16
7321                         NEXTOPCODE
7322 Op16M0mod3:
7323 lbl16mod3a:     DirectIndexedX0
7324 lbl16mod3b:     ASL16
7325                         NEXTOPCODE
7326 Op17M0mod3:
7327 lbl17mod3a:     DirectIndirectIndexedLong0
7328 lbl17mod3b:     ORA16
7329                         NEXTOPCODE
7330 Op18mod3:
7331 lbl18mod3:      Op18
7332                         NEXTOPCODE
7333 Op19M0mod3:
7334 lbl19mod3a:     AbsoluteIndexedY0
7335 lbl19mod3b:     ORA16
7336                         NEXTOPCODE
7337 Op1AM0mod3:
7338 lbl1Amod3a:     A_INC16
7339                         NEXTOPCODE
7340 Op1Bmod3:
7341 lbl1Bmod3:      Op1BM0
7342                         NEXTOPCODE
7343 Op1CM0mod3:
7344 lbl1Cmod3a:     Absolute
7345 lbl1Cmod3b:     TRB16
7346                         NEXTOPCODE
7347 Op1DM0mod3:
7348 lbl1Dmod3a:     AbsoluteIndexedX0
7349 lbl1Dmod3b:     ORA16
7350                         NEXTOPCODE
7351 Op1EM0mod3:
7352 lbl1Emod3a:     AbsoluteIndexedX0
7353 lbl1Emod3b:     ASL16
7354                         NEXTOPCODE
7355 Op1FM0mod3:
7356 lbl1Fmod3a:     AbsoluteLongIndexedX0
7357 lbl1Fmod3b:     ORA16
7358                         NEXTOPCODE
7359 Op20mod3:
7360 lbl20mod3:      Op20
7361                         NEXTOPCODE
7362 Op21M0mod3:
7363 lbl21mod3a:     DirectIndexedIndirect0
7364 lbl21mod3b:     AND16
7365                         NEXTOPCODE
7366 Op22mod3:
7367 lbl22mod3:      Op22
7368                         NEXTOPCODE
7369 Op23M0mod3:
7370 lbl23mod3a:     StackasmRelative
7371 lbl23mod3b:     AND16
7372                         NEXTOPCODE
7373 Op24M0mod3:
7374 lbl24mod3a:     Direct
7375 lbl24mod3b:     BIT16
7376                         NEXTOPCODE
7377 Op25M0mod3:
7378 lbl25mod3a:     Direct
7379 lbl25mod3b:     AND16
7380                         NEXTOPCODE
7381 Op26M0mod3:
7382 lbl26mod3a:     Direct
7383 lbl26mod3b:     ROL16
7384                         NEXTOPCODE
7385 Op27M0mod3:
7386 lbl27mod3a:     DirectIndirectLong
7387 lbl27mod3b:     AND16
7388                         NEXTOPCODE
7389 Op28mod3:
7390 lbl28mod3:      Op28X0M0
7391                         NEXTOPCODE
7392 .pool
7393 Op29M0mod3:
7394 lbl29mod3:      Op29M0
7395                         NEXTOPCODE
7396 Op2AM0mod3:
7397 lbl2Amod3a:     A_ROL16
7398                         NEXTOPCODE
7399 Op2Bmod3:
7400 lbl2Bmod3:      Op2B
7401                         NEXTOPCODE
7402 Op2CM0mod3:
7403 lbl2Cmod3a:     Absolute
7404 lbl2Cmod3b:     BIT16
7405                         NEXTOPCODE
7406 Op2DM0mod3:
7407 lbl2Dmod3a:     Absolute
7408 lbl2Dmod3b:     AND16
7409                         NEXTOPCODE
7410 Op2EM0mod3:
7411 lbl2Emod3a:     Absolute
7412 lbl2Emod3b:     ROL16
7413                         NEXTOPCODE
7414 Op2FM0mod3:
7415 lbl2Fmod3a:     AbsoluteLong
7416 lbl2Fmod3b:     AND16
7417                         NEXTOPCODE
7418 Op30mod3:
7419 lbl30mod3:      Op30
7420                         NEXTOPCODE
7421 Op31M0mod3:
7422 lbl31mod3a:     DirectIndirectIndexed0
7423 lbl31mod3b:     AND16
7424                         NEXTOPCODE
7425 Op32M0mod3:
7426 lbl32mod3a:     DirectIndirect
7427 lbl32mod3b:     AND16
7428                         NEXTOPCODE
7429 Op33M0mod3:
7430 lbl33mod3a:     StackasmRelativeIndirectIndexed0
7431 lbl33mod3b:     AND16
7432                         NEXTOPCODE
7433 Op34M0mod3:
7434 lbl34mod3a:     DirectIndexedX0
7435 lbl34mod3b:     BIT16
7436                         NEXTOPCODE
7437 Op35M0mod3:
7438 lbl35mod3a:     DirectIndexedX0
7439 lbl35mod3b:     AND16
7440                         NEXTOPCODE
7441 Op36M0mod3:
7442 lbl36mod3a:     DirectIndexedX0
7443 lbl36mod3b:     ROL16
7444                         NEXTOPCODE
7445 Op37M0mod3:
7446 lbl37mod3a:     DirectIndirectIndexedLong0
7447 lbl37mod3b:     AND16
7448                         NEXTOPCODE
7449 Op38mod3:
7450 lbl38mod3:      Op38
7451                         NEXTOPCODE
7452 Op39M0mod3:
7453 lbl39mod3a:     AbsoluteIndexedY0
7454 lbl39mod3b:     AND16
7455                         NEXTOPCODE
7456 Op3AM0mod3:
7457 lbl3Amod3a:     A_DEC16
7458                         NEXTOPCODE
7459 Op3Bmod3:
7460 lbl3Bmod3:      Op3BM0
7461                         NEXTOPCODE
7462 Op3CM0mod3:
7463 lbl3Cmod3a:     AbsoluteIndexedX0
7464 lbl3Cmod3b:     BIT16
7465                         NEXTOPCODE
7466 Op3DM0mod3:
7467 lbl3Dmod3a:     AbsoluteIndexedX0
7468 lbl3Dmod3b:     AND16
7469                         NEXTOPCODE
7470 Op3EM0mod3:
7471 lbl3Emod3a:     AbsoluteIndexedX0
7472 lbl3Emod3b:     ROL16
7473                         NEXTOPCODE
7474 Op3FM0mod3:
7475 lbl3Fmod3a:     AbsoluteLongIndexedX0
7476 lbl3Fmod3b:     AND16
7477                         NEXTOPCODE
7478 Op40mod3:
7479 lbl40mod3:      Op40X0M0
7480                         NEXTOPCODE
7481 .pool
7482 Op41M0mod3:
7483 lbl41mod3a:     DirectIndexedIndirect0
7484 lbl41mod3b:     EOR16
7485                         NEXTOPCODE
7486 Op42mod3:
7487 lbl42mod3:      Op42
7488                         NEXTOPCODE
7489 Op43M0mod3:
7490 lbl43mod3a:     StackasmRelative
7491 lbl43mod3b:     EOR16
7492                         NEXTOPCODE
7493 Op44X0mod3:
7494 lbl44mod3:      Op44X0M0
7495                         NEXTOPCODE
7496 Op45M0mod3:
7497 lbl45mod3a:     Direct
7498 lbl45mod3b:     EOR16
7499                         NEXTOPCODE
7500 Op46M0mod3:
7501 lbl46mod3a:     Direct
7502 lbl46mod3b:     LSR16
7503                         NEXTOPCODE
7504 Op47M0mod3:
7505 lbl47mod3a:     DirectIndirectLong
7506 lbl47mod3b:     EOR16
7507                         NEXTOPCODE
7508 Op48M0mod3:
7509 lbl48mod3:      Op48M0
7510                         NEXTOPCODE
7511 Op49M0mod3:
7512 lbl49mod3:      Op49M0
7513                         NEXTOPCODE
7514 Op4AM0mod3:
7515 lbl4Amod3a:     A_LSR16
7516                         NEXTOPCODE
7517 Op4Bmod3:
7518 lbl4Bmod3:      Op4B
7519                         NEXTOPCODE
7520 Op4Cmod3:
7521 lbl4Cmod3:      Op4C
7522                         NEXTOPCODE
7523 Op4DM0mod3:
7524 lbl4Dmod3a:     Absolute
7525 lbl4Dmod3b:     EOR16
7526                         NEXTOPCODE
7527 Op4EM0mod3:
7528 lbl4Emod3a:     Absolute
7529 lbl4Emod3b:     LSR16
7530                         NEXTOPCODE
7531 Op4FM0mod3:
7532 lbl4Fmod3a:     AbsoluteLong
7533 lbl4Fmod3b:     EOR16
7534                         NEXTOPCODE
7535 Op50mod3:
7536 lbl50mod3:      Op50
7537                         NEXTOPCODE
7538 Op51M0mod3:
7539 lbl51mod3a:     DirectIndirectIndexed0
7540 lbl51mod3b:     EOR16
7541                         NEXTOPCODE
7542 Op52M0mod3:
7543 lbl52mod3a:     DirectIndirect
7544 lbl52mod3b:     EOR16
7545                         NEXTOPCODE
7546 Op53M0mod3:
7547 lbl53mod3a:     StackasmRelativeIndirectIndexed0
7548 lbl53mod3b:     EOR16
7549                         NEXTOPCODE
7550 Op54X0mod3:
7551 lbl54mod3:      Op54X0M0
7552                         NEXTOPCODE
7553 Op55M0mod3:
7554 lbl55mod3a:     DirectIndexedX0
7555 lbl55mod3b:     EOR16
7556                         NEXTOPCODE
7557 Op56M0mod3:
7558 lbl56mod3a:     DirectIndexedX0
7559 lbl56mod3b:     LSR16
7560                         NEXTOPCODE
7561 Op57M0mod3:
7562 lbl57mod3a:     DirectIndirectIndexedLong0
7563 lbl57mod3b:     EOR16
7564                         NEXTOPCODE
7565 Op58mod3:
7566 lbl58mod3:      Op58
7567                         NEXTOPCODE
7568 Op59M0mod3:
7569 lbl59mod3a:     AbsoluteIndexedY0
7570 lbl59mod3b:     EOR16
7571                         NEXTOPCODE
7572 Op5AX0mod3:
7573 lbl5Amod3:      Op5AX0
7574                         NEXTOPCODE
7575 Op5Bmod3:
7576 lbl5Bmod3:      Op5BM0
7577                         NEXTOPCODE
7578 Op5Cmod3:
7579 lbl5Cmod3:      Op5C
7580                         NEXTOPCODE
7581 Op5DM0mod3:
7582 lbl5Dmod3a:     AbsoluteIndexedX0
7583 lbl5Dmod3b:     EOR16
7584                         NEXTOPCODE
7585 Op5EM0mod3:
7586 lbl5Emod3a:     AbsoluteIndexedX0
7587 lbl5Emod3b:     LSR16
7588                         NEXTOPCODE
7589 Op5FM0mod3:
7590 lbl5Fmod3a:     AbsoluteLongIndexedX0
7591 lbl5Fmod3b:     EOR16
7592                         NEXTOPCODE
7593 Op60mod3:
7594 lbl60mod3:      Op60
7595                         NEXTOPCODE
7596 Op61M0mod3:
7597 lbl61mod3a:     DirectIndexedIndirect0
7598 lbl61mod3b:     ADC16
7599                         NEXTOPCODE
7600 Op62mod3:
7601 lbl62mod3:      Op62
7602                         NEXTOPCODE
7603 Op63M0mod3:
7604 lbl63mod3a:     StackasmRelative
7605 lbl63mod3b:     ADC16
7606                         NEXTOPCODE
7607 .pool
7608 Op64M0mod3:
7609 lbl64mod3a:     Direct
7610 lbl64mod3b:     STZ16
7611                         NEXTOPCODE
7612 Op65M0mod3:
7613 lbl65mod3a:     Direct
7614 lbl65mod3b:     ADC16
7615                         NEXTOPCODE
7616 .pool
7617 Op66M0mod3:
7618 lbl66mod3a:     Direct
7619 lbl66mod3b:     ROR16
7620                         NEXTOPCODE
7621 Op67M0mod3:
7622 lbl67mod3a:     DirectIndirectLong
7623 lbl67mod3b:     ADC16
7624                         NEXTOPCODE
7625 .pool
7626 Op68M0mod3:
7627 lbl68mod3:      Op68M0
7628                         NEXTOPCODE
7629 Op69M0mod3:
7630 lbl69mod3a:     Immediate16
7631 lbl69mod3b:     ADC16
7632                         NEXTOPCODE
7633 .pool
7634 Op6AM0mod3:
7635 lbl6Amod3a:     A_ROR16
7636                         NEXTOPCODE
7637 Op6Bmod3:
7638 lbl6Bmod3:      Op6B
7639                         NEXTOPCODE
7640 Op6Cmod3:
7641 lbl6Cmod3:      Op6C
7642                         NEXTOPCODE
7643 Op6DM0mod3:
7644 lbl6Dmod3a:     Absolute
7645 lbl6Dmod3b:     ADC16
7646                         NEXTOPCODE
7647 Op6EM0mod3:
7648 lbl6Emod3a:     Absolute
7649 lbl6Emod3b:     ROR16
7650                         NEXTOPCODE
7651 Op6FM0mod3:
7652 lbl6Fmod3a:     AbsoluteLong
7653 lbl6Fmod3b:     ADC16
7654                         NEXTOPCODE
7655 Op70mod3:
7656 lbl70mod3:      Op70
7657                         NEXTOPCODE
7658 Op71M0mod3:
7659 lbl71mod3a:     DirectIndirectIndexed0
7660 lbl71mod3b:     ADC16
7661                         NEXTOPCODE
7662 Op72M0mod3:
7663 lbl72mod3a:     DirectIndirect
7664 lbl72mod3b:     ADC16
7665                         NEXTOPCODE
7666 Op73M0mod3:
7667 lbl73mod3a:     StackasmRelativeIndirectIndexed0
7668 lbl73mod3b:     ADC16
7669                         NEXTOPCODE
7670 .pool
7671 Op74M0mod3:
7672 lbl74mod3a:     DirectIndexedX0
7673 lbl74mod3b:     STZ16
7674                         NEXTOPCODE
7675 Op75M0mod3:
7676 lbl75mod3a:     DirectIndexedX0
7677 lbl75mod3b:     ADC16
7678                         NEXTOPCODE
7679 .pool
7680 Op76M0mod3:
7681 lbl76mod3a:     DirectIndexedX0
7682 lbl76mod3b:     ROR16
7683                         NEXTOPCODE
7684 Op77M0mod3:
7685 lbl77mod3a:     DirectIndirectIndexedLong0
7686 lbl77mod3b:     ADC16
7687                         NEXTOPCODE
7688 Op78mod3:
7689 lbl78mod3:      Op78
7690                         NEXTOPCODE
7691 Op79M0mod3:
7692 lbl79mod3a:     AbsoluteIndexedY0
7693 lbl79mod3b:     ADC16
7694                         NEXTOPCODE
7695 Op7AX0mod3:
7696 lbl7Amod3:      Op7AX0
7697                         NEXTOPCODE
7698 Op7Bmod3:
7699 lbl7Bmod3:      Op7BM0
7700                         NEXTOPCODE
7701 Op7Cmod3:
7702 lbl7Cmod3:      AbsoluteIndexedIndirectX0
7703                 Op7C
7704                         NEXTOPCODE
7705 Op7DM0mod3:
7706 lbl7Dmod3a:     AbsoluteIndexedX0
7707 lbl7Dmod3b:     ADC16
7708                         NEXTOPCODE
7709 Op7EM0mod3:
7710 lbl7Emod3a:     AbsoluteIndexedX0
7711 lbl7Emod3b:     ROR16
7712                         NEXTOPCODE
7713 Op7FM0mod3:
7714 lbl7Fmod3a:     AbsoluteLongIndexedX0
7715 lbl7Fmod3b:     ADC16
7716                         NEXTOPCODE
7717 .pool
7718 Op80mod3:
7719 lbl80mod3:      Op80
7720                         NEXTOPCODE
7721 Op81M0mod3:
7722 lbl81mod3a:     DirectIndexedIndirect0
7723 lbl81mod3b:     Op81M0
7724                         NEXTOPCODE
7725 Op82mod3:
7726 lbl82mod3:      Op82
7727                         NEXTOPCODE
7728 Op83M0mod3:
7729 lbl83mod3a:     StackasmRelative
7730 lbl83mod3b:     STA16
7731                         NEXTOPCODE
7732 Op84X0mod3:
7733 lbl84mod3a:     Direct
7734 lbl84mod3b:     STY16
7735                         NEXTOPCODE
7736 Op85M0mod3:
7737 lbl85mod3a:     Direct
7738 lbl85mod3b:     STA16
7739                         NEXTOPCODE
7740 Op86X0mod3:
7741 lbl86mod3a:     Direct
7742 lbl86mod3b:     STX16
7743                         NEXTOPCODE
7744 Op87M0mod3:
7745 lbl87mod3a:     DirectIndirectLong
7746 lbl87mod3b:     STA16
7747                         NEXTOPCODE
7748 Op88X0mod3:
7749 lbl88mod3:      Op88X0
7750                         NEXTOPCODE
7751 Op89M0mod3:
7752 lbl89mod3:      Op89M0
7753                         NEXTOPCODE
7754 Op8AM0mod3:
7755 lbl8Amod3:      Op8AM0X0
7756                         NEXTOPCODE
7757 Op8Bmod3:
7758 lbl8Bmod3:      Op8B
7759                         NEXTOPCODE
7760 Op8CX0mod3:
7761 lbl8Cmod3a:     Absolute
7762 lbl8Cmod3b:     STY16
7763                         NEXTOPCODE
7764 Op8DM0mod3:
7765 lbl8Dmod3a:     Absolute
7766 lbl8Dmod3b:     STA16
7767                         NEXTOPCODE
7768 Op8EX0mod3:
7769 lbl8Emod3a:     Absolute
7770 lbl8Emod3b:     STX16
7771                         NEXTOPCODE
7772 Op8FM0mod3:
7773 lbl8Fmod3a:     AbsoluteLong
7774 lbl8Fmod3b:     STA16
7775                         NEXTOPCODE
7776 Op90mod3:
7777 lbl90mod3:      Op90
7778                         NEXTOPCODE
7779 Op91M0mod3:
7780 lbl91mod3a:     DirectIndirectIndexed0
7781 lbl91mod3b:     STA16
7782                         NEXTOPCODE
7783 Op92M0mod3:
7784 lbl92mod3a:     DirectIndirect
7785 lbl92mod3b:     STA16
7786                         NEXTOPCODE
7787 Op93M0mod3:
7788 lbl93mod3a:     StackasmRelativeIndirectIndexed0
7789 lbl93mod3b:     STA16
7790                         NEXTOPCODE
7791 Op94X0mod3:
7792 lbl94mod3a:     DirectIndexedX0
7793 lbl94mod3b:     STY16
7794                         NEXTOPCODE
7795 Op95M0mod3:
7796 lbl95mod3a:     DirectIndexedX0
7797 lbl95mod3b:     STA16
7798                         NEXTOPCODE
7799 Op96X0mod3:
7800 lbl96mod3a:     DirectIndexedY0
7801 lbl96mod3b:     STX16
7802                         NEXTOPCODE
7803 Op97M0mod3:
7804 lbl97mod3a:     DirectIndirectIndexedLong0
7805 lbl97mod3b:     STA16
7806                         NEXTOPCODE
7807 Op98M0mod3:
7808 lbl98mod3:      Op98M0X0
7809                         NEXTOPCODE
7810 Op99M0mod3:
7811 lbl99mod3a:     AbsoluteIndexedY0
7812 lbl99mod3b:     STA16
7813                         NEXTOPCODE
7814 Op9Amod3:
7815 lbl9Amod3:      Op9AX0
7816                         NEXTOPCODE
7817 Op9BX0mod3:
7818 lbl9Bmod3:      Op9BX0
7819                         NEXTOPCODE
7820 Op9CM0mod3:
7821 lbl9Cmod3a:     Absolute
7822 lbl9Cmod3b:     STZ16
7823                         NEXTOPCODE
7824 Op9DM0mod3:
7825 lbl9Dmod3a:     AbsoluteIndexedX0
7826 lbl9Dmod3b:     STA16
7827                         NEXTOPCODE
7828 Op9EM0mod3:
7829 lbl9Emod3:      AbsoluteIndexedX0
7830                 STZ16
7831                         NEXTOPCODE
7832 Op9FM0mod3:
7833 lbl9Fmod3a:     AbsoluteLongIndexedX0
7834 lbl9Fmod3b:     STA16
7835                         NEXTOPCODE
7836 OpA0X0mod3:
7837 lblA0mod3:      OpA0X0
7838                         NEXTOPCODE
7839 OpA1M0mod3:
7840 lblA1mod3a:     DirectIndexedIndirect0
7841 lblA1mod3b:     LDA16
7842                         NEXTOPCODE
7843 OpA2X0mod3:
7844 lblA2mod3:      OpA2X0
7845                         NEXTOPCODE
7846 OpA3M0mod3:
7847 lblA3mod3a:     StackasmRelative
7848 lblA3mod3b:     LDA16
7849                         NEXTOPCODE
7850 OpA4X0mod3:
7851 lblA4mod3a:     Direct
7852 lblA4mod3b:     LDY16
7853                         NEXTOPCODE
7854 OpA5M0mod3:
7855 lblA5mod3a:     Direct
7856 lblA5mod3b:     LDA16
7857                         NEXTOPCODE
7858 OpA6X0mod3:
7859 lblA6mod3a:     Direct
7860 lblA6mod3b:     LDX16
7861                         NEXTOPCODE
7862 OpA7M0mod3:
7863 lblA7mod3a:     DirectIndirectLong
7864 lblA7mod3b:     LDA16
7865                         NEXTOPCODE
7866 OpA8X0mod3:
7867 lblA8mod3:      OpA8X0M0
7868                         NEXTOPCODE
7869 OpA9M0mod3:
7870 lblA9mod3:      OpA9M0
7871                         NEXTOPCODE
7872 OpAAX0mod3:
7873 lblAAmod3:      OpAAX0M0
7874                         NEXTOPCODE
7875 OpABmod3:
7876 lblABmod3:      OpAB
7877                         NEXTOPCODE
7878 OpACX0mod3:
7879 lblACmod3a:     Absolute
7880 lblACmod3b:     LDY16
7881                         NEXTOPCODE
7882 OpADM0mod3:
7883 lblADmod3a:     Absolute
7884 lblADmod3b:     LDA16
7885                         NEXTOPCODE
7886 OpAEX0mod3:
7887 lblAEmod3a:     Absolute
7888 lblAEmod3b:     LDX16
7889                         NEXTOPCODE
7890 OpAFM0mod3:
7891 lblAFmod3a:     AbsoluteLong
7892 lblAFmod3b:     LDA16
7893                         NEXTOPCODE
7894 OpB0mod3:
7895 lblB0mod3:      OpB0
7896                         NEXTOPCODE
7897 OpB1M0mod3:
7898 lblB1mod3a:     DirectIndirectIndexed0
7899 lblB1mod3b:     LDA16
7900                         NEXTOPCODE
7901 OpB2M0mod3:
7902 lblB2mod3a:     DirectIndirect
7903 lblB2mod3b:     LDA16
7904                         NEXTOPCODE
7905 OpB3M0mod3:
7906 lblB3mod3a:     StackasmRelativeIndirectIndexed0
7907 lblB3mod3b:     LDA16
7908                         NEXTOPCODE
7909 OpB4X0mod3:
7910 lblB4mod3a:     DirectIndexedX0
7911 lblB4mod3b:     LDY16
7912                         NEXTOPCODE
7913 OpB5M0mod3:
7914 lblB5mod3a:     DirectIndexedX0
7915 lblB5mod3b:     LDA16
7916                         NEXTOPCODE
7917 OpB6X0mod3:
7918 lblB6mod3a:     DirectIndexedY0
7919 lblB6mod3b:     LDX16
7920                         NEXTOPCODE
7921 OpB7M0mod3:
7922 lblB7mod3a:     DirectIndirectIndexedLong0
7923 lblB7mod3b:     LDA16
7924                         NEXTOPCODE
7925 OpB8mod3:
7926 lblB8mod3:      OpB8
7927                         NEXTOPCODE
7928 OpB9M0mod3:
7929 lblB9mod3a:     AbsoluteIndexedY0
7930 lblB9mod3b:     LDA16
7931                         NEXTOPCODE
7932 OpBAX0mod3:
7933 lblBAmod3:      OpBAX0
7934                         NEXTOPCODE
7935 OpBBX0mod3:
7936 lblBBmod3:      OpBBX0
7937                         NEXTOPCODE
7938 OpBCX0mod3:
7939 lblBCmod3a:     AbsoluteIndexedX0
7940 lblBCmod3b:     LDY16
7941                         NEXTOPCODE
7942 OpBDM0mod3:
7943 lblBDmod3a:     AbsoluteIndexedX0
7944 lblBDmod3b:     LDA16
7945                         NEXTOPCODE
7946 OpBEX0mod3:
7947 lblBEmod3a:     AbsoluteIndexedY0
7948 lblBEmod3b:     LDX16
7949                         NEXTOPCODE
7950 OpBFM0mod3:
7951 lblBFmod3a:     AbsoluteLongIndexedX0
7952 lblBFmod3b:     LDA16
7953                         NEXTOPCODE
7954 OpC0X0mod3:
7955 lblC0mod3:      OpC0X0
7956                         NEXTOPCODE
7957 OpC1M0mod3:
7958 lblC1mod3a:     DirectIndexedIndirect0
7959 lblC1mod3b:     CMP16
7960                         NEXTOPCODE
7961 OpC2mod3:
7962 lblC2mod3:      OpC2
7963                         NEXTOPCODE
7964 .pool
7965 OpC3M0mod3:
7966 lblC3mod3a:     StackasmRelative
7967 lblC3mod3b:     CMP16
7968                         NEXTOPCODE
7969 OpC4X0mod3:
7970 lblC4mod3a:     Direct
7971 lblC4mod3b:     CMY16
7972                         NEXTOPCODE
7973 OpC5M0mod3:
7974 lblC5mod3a:     Direct
7975 lblC5mod3b:     CMP16
7976                         NEXTOPCODE
7977 OpC6M0mod3:
7978 lblC6mod3a:     Direct
7979 lblC6mod3b:     DEC16
7980                         NEXTOPCODE
7981 OpC7M0mod3:
7982 lblC7mod3a:     DirectIndirectLong
7983 lblC7mod3b:     CMP16
7984                         NEXTOPCODE
7985 OpC8X0mod3:
7986 lblC8mod3:      OpC8X0
7987                         NEXTOPCODE
7988 OpC9M0mod3:
7989 lblC9mod3:      OpC9M0
7990                         NEXTOPCODE
7991 OpCAX0mod3:
7992 lblCAmod3:      OpCAX0
7993                         NEXTOPCODE
7994 OpCBmod3:
7995 lblCBmod3:      OpCB
7996                         NEXTOPCODE
7997 OpCCX0mod3:
7998 lblCCmod3a:     Absolute
7999 lblCCmod3b:     CMY16
8000                         NEXTOPCODE
8001 OpCDM0mod3:
8002 lblCDmod3a:     Absolute
8003 lblCDmod3b:     CMP16
8004                         NEXTOPCODE
8005 OpCEM0mod3:
8006 lblCEmod3a:     Absolute
8007 lblCEmod3b:     DEC16
8008                         NEXTOPCODE
8009 OpCFM0mod3:
8010 lblCFmod3a:     AbsoluteLong
8011 lblCFmod3b:     CMP16
8012                         NEXTOPCODE
8013 OpD0mod3:
8014 lblD0mod3:      OpD0
8015                         NEXTOPCODE
8016 OpD1M0mod3:
8017 lblD1mod3a:     DirectIndirectIndexed0
8018 lblD1mod3b:     CMP16
8019                         NEXTOPCODE
8020 OpD2M0mod3:
8021 lblD2mod3a:     DirectIndirect
8022 lblD2mod3b:     CMP16
8023                         NEXTOPCODE
8024 OpD3M0mod3:
8025 lblD3mod3a:     StackasmRelativeIndirectIndexed0
8026 lblD3mod3b:     CMP16
8027                         NEXTOPCODE
8028 OpD4mod3:
8029 lblD4mod3:      OpD4
8030                         NEXTOPCODE
8031 OpD5M0mod3:
8032 lblD5mod3a:     DirectIndexedX0
8033 lblD5mod3b:     CMP16
8034                         NEXTOPCODE
8035 OpD6M0mod3:
8036 lblD6mod3a:     DirectIndexedX0
8037 lblD6mod3b:     DEC16
8038                         NEXTOPCODE
8039 OpD7M0mod3:
8040 lblD7mod3a:     DirectIndirectIndexedLong0
8041 lblD7mod3b:     CMP16
8042                         NEXTOPCODE
8043 OpD8mod3:
8044 lblD8mod3:      OpD8
8045                         NEXTOPCODE
8046 OpD9M0mod3:
8047 lblD9mod3a:     AbsoluteIndexedY0
8048 lblD9mod3b:     CMP16
8049                         NEXTOPCODE
8050 OpDAX0mod3:
8051 lblDAmod3:      OpDAX0
8052                         NEXTOPCODE
8053 OpDBmod3:
8054 lblDBmod3:      OpDB
8055                         NEXTOPCODE
8056 OpDCmod3:
8057 lblDCmod3:      OpDC
8058                         NEXTOPCODE
8059 OpDDM0mod3:
8060 lblDDmod3a:     AbsoluteIndexedX0
8061 lblDDmod3b:     CMP16
8062                         NEXTOPCODE
8063 OpDEM0mod3:
8064 lblDEmod3a:     AbsoluteIndexedX0
8065 lblDEmod3b:     DEC16
8066                         NEXTOPCODE
8067 OpDFM0mod3:
8068 lblDFmod3a:     AbsoluteLongIndexedX0
8069 lblDFmod3b:     CMP16
8070                         NEXTOPCODE
8071 OpE0X0mod3:
8072 lblE0mod3:      OpE0X0
8073                         NEXTOPCODE
8074 OpE1M0mod3:
8075 lblE1mod3a:     DirectIndexedIndirect0
8076 lblE1mod3b:     SBC16
8077                         NEXTOPCODE
8078 OpE2mod3:
8079 lblE2mod3:      OpE2
8080                         NEXTOPCODE
8081 .pool
8082 OpE3M0mod3:
8083 lblE3mod3a:     StackasmRelative
8084 lblE3mod3b:     SBC16
8085                         NEXTOPCODE
8086 OpE4X0mod3:
8087 lblE4mod3a:     Direct
8088 lblE4mod3b:     CMX16
8089                         NEXTOPCODE
8090 OpE5M0mod3:
8091 lblE5mod3a:     Direct
8092 lblE5mod3b:     SBC16
8093                         NEXTOPCODE
8094 OpE6M0mod3:
8095 lblE6mod3a:     Direct
8096 lblE6mod3b:     INC16
8097                         NEXTOPCODE
8098 OpE7M0mod3:
8099 lblE7mod3a:     DirectIndirectLong
8100 lblE7mod3b:     SBC16
8101                         NEXTOPCODE
8102 OpE8X0mod3:
8103 lblE8mod3:      OpE8X0
8104                         NEXTOPCODE
8105 OpE9M0mod3:
8106 lblE9mod3a:     Immediate16
8107 lblE9mod3b:     SBC16
8108                         NEXTOPCODE
8109 OpEAmod3:
8110 lblEAmod3:      OpEA
8111                         NEXTOPCODE
8112 OpEBmod3:
8113 lblEBmod3:      OpEBM0
8114                         NEXTOPCODE
8115 OpECX0mod3:
8116 lblECmod3a:     Absolute
8117 lblECmod3b:     CMX16
8118                         NEXTOPCODE
8119 OpEDM0mod3:
8120 lblEDmod3a:     Absolute
8121 lblEDmod3b:     SBC16
8122                         NEXTOPCODE
8123 OpEEM0mod3:
8124 lblEEmod3a:     Absolute
8125 lblEEmod3b:     INC16
8126                         NEXTOPCODE
8127 OpEFM0mod3:
8128 lblEFmod3a:     AbsoluteLong
8129 lblEFmod3b:     SBC16
8130                         NEXTOPCODE
8131 OpF0mod3:
8132 lblF0mod3:      OpF0
8133                         NEXTOPCODE
8134 OpF1M0mod3:
8135 lblF1mod3a:     DirectIndirectIndexed0
8136 lblF1mod3b:     SBC16
8137                         NEXTOPCODE
8138 OpF2M0mod3:
8139 lblF2mod3a:     DirectIndirect
8140 lblF2mod3b:     SBC16
8141                         NEXTOPCODE
8142 OpF3M0mod3:
8143 lblF3mod3a:     StackasmRelativeIndirectIndexed0
8144 lblF3mod3b:     SBC16
8145                         NEXTOPCODE
8146 OpF4mod3:
8147 lblF4mod3:      OpF4
8148                         NEXTOPCODE
8149 OpF5M0mod3:
8150 lblF5mod3a:     DirectIndexedX0
8151 lblF5mod3b:     SBC16
8152                         NEXTOPCODE
8153 OpF6M0mod3:
8154 lblF6mod3a:     DirectIndexedX0
8155 lblF6mod3b:     INC16
8156                         NEXTOPCODE
8157 OpF7M0mod3:
8158 lblF7mod3a:     DirectIndirectIndexedLong0
8159 lblF7mod3b:     SBC16
8160                         NEXTOPCODE
8161 OpF8mod3:
8162 lblF8mod3:      OpF8
8163                         NEXTOPCODE
8164 OpF9M0mod3:
8165 lblF9mod3a:     AbsoluteIndexedY0
8166 lblF9mod3b:     SBC16
8167                         NEXTOPCODE
8168 OpFAX0mod3:
8169 lblFAmod3:      OpFAX0
8170                         NEXTOPCODE
8171 OpFBmod3:
8172 lblFBmod3:      OpFB
8173                         NEXTOPCODE
8174 OpFCmod3:
8175 lblFCmod3:      OpFCX0
8176                         NEXTOPCODE
8177 OpFDM0mod3:
8178 lblFDmod3a:     AbsoluteIndexedX0
8179 lblFDmod3b:     SBC16
8180                         NEXTOPCODE
8181 OpFEM0mod3:
8182 lblFEmod3a:     AbsoluteIndexedX0
8183 lblFEmod3b:     INC16
8184                         NEXTOPCODE
8185 OpFFM0mod3:
8186 lblFFmod3a:     AbsoluteLongIndexedX0
8187 lblFFmod3b:     SBC16
8188                         NEXTOPCODE
8189 .pool
8190
8191 jumptable4:             .long   Op00mod4
8192                         .long   Op01M0mod4
8193                         .long   Op02mod4
8194                         .long   Op03M0mod4
8195                         .long   Op04M0mod4
8196                         .long   Op05M0mod4
8197                         .long   Op06M0mod4
8198                         .long   Op07M0mod4
8199                         .long   Op08mod4
8200                         .long   Op09M0mod4
8201                         .long   Op0AM0mod4
8202                         .long   Op0Bmod4
8203                         .long   Op0CM0mod4
8204                         .long   Op0DM0mod4
8205                         .long   Op0EM0mod4
8206                         .long   Op0FM0mod4
8207                         .long   Op10mod4
8208                         .long   Op11M0mod4
8209                         .long   Op12M0mod4
8210                         .long   Op13M0mod4
8211                         .long   Op14M0mod4
8212                         .long   Op15M0mod4
8213                         .long   Op16M0mod4
8214                         .long   Op17M0mod4
8215                         .long   Op18mod4
8216                         .long   Op19M0mod4
8217                         .long   Op1AM0mod4
8218                         .long   Op1Bmod4
8219                         .long   Op1CM0mod4
8220                         .long   Op1DM0mod4
8221                         .long   Op1EM0mod4
8222                         .long   Op1FM0mod4
8223                         .long   Op20mod4
8224                         .long   Op21M0mod4
8225                         .long   Op22mod4
8226                         .long   Op23M0mod4
8227                         .long   Op24M0mod4
8228                         .long   Op25M0mod4
8229                         .long   Op26M0mod4
8230                         .long   Op27M0mod4
8231                         .long   Op28mod4
8232                         .long   Op29M0mod4
8233                         .long   Op2AM0mod4
8234                         .long   Op2Bmod4
8235                         .long   Op2CM0mod4
8236                         .long   Op2DM0mod4
8237                         .long   Op2EM0mod4
8238                         .long   Op2FM0mod4
8239                         .long   Op30mod4
8240                         .long   Op31M0mod4
8241                         .long   Op32M0mod4
8242                         .long   Op33M0mod4
8243                         .long   Op34M0mod4
8244                         .long   Op35M0mod4
8245                         .long   Op36M0mod4
8246                         .long   Op37M0mod4
8247                         .long   Op38mod4
8248                         .long   Op39M0mod4
8249                         .long   Op3AM0mod4
8250                         .long   Op3Bmod4
8251                         .long   Op3CM0mod4
8252                         .long   Op3DM0mod4
8253                         .long   Op3EM0mod4
8254                         .long   Op3FM0mod4
8255                         .long   Op40mod4
8256                         .long   Op41M0mod4
8257                         .long   Op42mod4
8258                         .long   Op43M0mod4
8259                         .long   Op44X1mod4
8260                         .long   Op45M0mod4
8261                         .long   Op46M0mod4
8262                         .long   Op47M0mod4
8263                         .long   Op48M0mod4
8264                         .long   Op49M0mod4
8265                         .long   Op4AM0mod4
8266                         .long   Op4Bmod4
8267                         .long   Op4Cmod4
8268                         .long   Op4DM0mod4
8269                         .long   Op4EM0mod4
8270                         .long   Op4FM0mod4
8271                         .long   Op50mod4
8272                         .long   Op51M0mod4
8273                         .long   Op52M0mod4
8274                         .long   Op53M0mod4
8275                         .long   Op54X1mod4
8276                         .long   Op55M0mod4
8277                         .long   Op56M0mod4
8278                         .long   Op57M0mod4
8279                         .long   Op58mod4
8280                         .long   Op59M0mod4
8281                         .long   Op5AX1mod4
8282                         .long   Op5Bmod4
8283                         .long   Op5Cmod4
8284                         .long   Op5DM0mod4
8285                         .long   Op5EM0mod4
8286                         .long   Op5FM0mod4
8287                         .long   Op60mod4
8288                         .long   Op61M0mod4
8289                         .long   Op62mod4
8290                         .long   Op63M0mod4
8291                         .long   Op64M0mod4
8292                         .long   Op65M0mod4
8293                         .long   Op66M0mod4
8294                         .long   Op67M0mod4
8295                         .long   Op68M0mod4
8296                         .long   Op69M0mod4
8297                         .long   Op6AM0mod4
8298                         .long   Op6Bmod4
8299                         .long   Op6Cmod4
8300                         .long   Op6DM0mod4
8301                         .long   Op6EM0mod4
8302                         .long   Op6FM0mod4
8303                         .long   Op70mod4
8304                         .long   Op71M0mod4
8305                         .long   Op72M0mod4
8306                         .long   Op73M0mod4
8307                         .long   Op74M0mod4
8308                         .long   Op75M0mod4
8309                         .long   Op76M0mod4
8310                         .long   Op77M0mod4
8311                         .long   Op78mod4
8312                         .long   Op79M0mod4
8313                         .long   Op7AX1mod4
8314                         .long   Op7Bmod4
8315                         .long   Op7Cmod4
8316                         .long   Op7DM0mod4
8317                         .long   Op7EM0mod4
8318                         .long   Op7FM0mod4
8319                         .long   Op80mod4
8320                         .long   Op81M0mod4
8321                         .long   Op82mod4
8322                         .long   Op83M0mod4
8323                         .long   Op84X1mod4
8324                         .long   Op85M0mod4
8325                         .long   Op86X1mod4
8326                         .long   Op87M0mod4
8327                         .long   Op88X1mod4
8328                         .long   Op89M0mod4
8329                         .long   Op8AM0mod4
8330                         .long   Op8Bmod4
8331                         .long   Op8CX1mod4
8332                         .long   Op8DM0mod4
8333                         .long   Op8EX1mod4
8334                         .long   Op8FM0mod4
8335                         .long   Op90mod4
8336                         .long   Op91M0mod4
8337                         .long   Op92M0mod4
8338                         .long   Op93M0mod4
8339                         .long   Op94X1mod4
8340                         .long   Op95M0mod4
8341                         .long   Op96X1mod4
8342                         .long   Op97M0mod4
8343                         .long   Op98M0mod4
8344                         .long   Op99M0mod4
8345                         .long   Op9Amod4
8346                         .long   Op9BX1mod4
8347                         .long   Op9CM0mod4
8348                         .long   Op9DM0mod4
8349                         .long   Op9EM0mod4
8350                         .long   Op9FM0mod4
8351                         .long   OpA0X1mod4
8352                         .long   OpA1M0mod4
8353                         .long   OpA2X1mod4
8354                         .long   OpA3M0mod4
8355                         .long   OpA4X1mod4
8356                         .long   OpA5M0mod4
8357                         .long   OpA6X1mod4
8358                         .long   OpA7M0mod4
8359                         .long   OpA8X1mod4
8360                         .long   OpA9M0mod4
8361                         .long   OpAAX1mod4
8362                         .long   OpABmod4
8363                         .long   OpACX1mod4
8364                         .long   OpADM0mod4
8365                         .long   OpAEX1mod4
8366                         .long   OpAFM0mod4
8367                         .long   OpB0mod4
8368                         .long   OpB1M0mod4
8369                         .long   OpB2M0mod4
8370                         .long   OpB3M0mod4
8371                         .long   OpB4X1mod4
8372                         .long   OpB5M0mod4
8373                         .long   OpB6X1mod4
8374                         .long   OpB7M0mod4
8375                         .long   OpB8mod4
8376                         .long   OpB9M0mod4
8377                         .long   OpBAX1mod4
8378                         .long   OpBBX1mod4
8379                         .long   OpBCX1mod4
8380                         .long   OpBDM0mod4
8381                         .long   OpBEX1mod4
8382                         .long   OpBFM0mod4
8383                         .long   OpC0X1mod4
8384                         .long   OpC1M0mod4
8385                         .long   OpC2mod4
8386                         .long   OpC3M0mod4
8387                         .long   OpC4X1mod4
8388                         .long   OpC5M0mod4
8389                         .long   OpC6M0mod4
8390                         .long   OpC7M0mod4
8391                         .long   OpC8X1mod4
8392                         .long   OpC9M0mod4
8393                         .long   OpCAX1mod4
8394                         .long   OpCBmod4
8395                         .long   OpCCX1mod4
8396                         .long   OpCDM0mod4
8397                         .long   OpCEM0mod4
8398                         .long   OpCFM0mod4
8399                         .long   OpD0mod4
8400                         .long   OpD1M0mod4
8401                         .long   OpD2M0mod4
8402                         .long   OpD3M0mod4
8403                         .long   OpD4mod4
8404                         .long   OpD5M0mod4
8405                         .long   OpD6M0mod4
8406                         .long   OpD7M0mod4
8407                         .long   OpD8mod4
8408                         .long   OpD9M0mod4
8409                         .long   OpDAX1mod4
8410                         .long   OpDBmod4
8411                         .long   OpDCmod4
8412                         .long   OpDDM0mod4
8413                         .long   OpDEM0mod4
8414                         .long   OpDFM0mod4
8415                         .long   OpE0X1mod4
8416                         .long   OpE1M0mod4
8417                         .long   OpE2mod4
8418                         .long   OpE3M0mod4
8419                         .long   OpE4X1mod4
8420                         .long   OpE5M0mod4
8421                         .long   OpE6M0mod4
8422                         .long   OpE7M0mod4
8423                         .long   OpE8X1mod4
8424                         .long   OpE9M0mod4
8425                         .long   OpEAmod4
8426                         .long   OpEBmod4
8427                         .long   OpECX1mod4
8428                         .long   OpEDM0mod4
8429                         .long   OpEEM0mod4
8430                         .long   OpEFM0mod4
8431                         .long   OpF0mod4
8432                         .long   OpF1M0mod4
8433                         .long   OpF2M0mod4
8434                         .long   OpF3M0mod4
8435                         .long   OpF4mod4
8436                         .long   OpF5M0mod4
8437                         .long   OpF6M0mod4
8438                         .long   OpF7M0mod4
8439                         .long   OpF8mod4
8440                         .long   OpF9M0mod4
8441                         .long   OpFAX1mod4
8442                         .long   OpFBmod4
8443                         .long   OpFCmod4
8444                         .long   OpFDM0mod4
8445                         .long   OpFEM0mod4
8446                         .long   OpFFM0mod4
8447 Op00mod4:
8448 lbl00mod4:      Op00
8449                         NEXTOPCODE
8450 Op01M0mod4:
8451 lbl01mod4a:     DirectIndexedIndirect1
8452 lbl01mod4b:     ORA16
8453                         NEXTOPCODE
8454 Op02mod4:
8455 lbl02mod4:      Op02
8456                         NEXTOPCODE
8457 Op03M0mod4:
8458 lbl03mod4a:     StackasmRelative
8459 lbl03mod4b:     ORA16
8460                         NEXTOPCODE
8461 Op04M0mod4:
8462 lbl04mod4a:     Direct
8463 lbl04mod4b:     TSB16
8464                         NEXTOPCODE
8465 Op05M0mod4:
8466 lbl05mod4a:     Direct
8467 lbl05mod4b:     ORA16
8468                         NEXTOPCODE
8469 Op06M0mod4:
8470 lbl06mod4a:     Direct
8471 lbl06mod4b:     ASL16
8472                         NEXTOPCODE
8473 Op07M0mod4:
8474 lbl07mod4a:     DirectIndirectLong
8475 lbl07mod4b:     ORA16
8476                         NEXTOPCODE
8477 Op08mod4:
8478 lbl08mod4:      Op08
8479                         NEXTOPCODE
8480 Op09M0mod4:
8481 lbl09mod4:      Op09M0
8482                         NEXTOPCODE
8483 Op0AM0mod4:
8484 lbl0Amod4a:     A_ASL16
8485                         NEXTOPCODE
8486 Op0Bmod4:
8487 lbl0Bmod4:      Op0B
8488                         NEXTOPCODE
8489 Op0CM0mod4:
8490 lbl0Cmod4a:     Absolute
8491 lbl0Cmod4b:     TSB16
8492                         NEXTOPCODE
8493 Op0DM0mod4:
8494 lbl0Dmod4a:     Absolute
8495 lbl0Dmod4b:     ORA16
8496                         NEXTOPCODE
8497 Op0EM0mod4:
8498 lbl0Emod4a:     Absolute
8499 lbl0Emod4b:     ASL16
8500                         NEXTOPCODE
8501 Op0FM0mod4:
8502 lbl0Fmod4a:     AbsoluteLong
8503 lbl0Fmod4b:     ORA16
8504                         NEXTOPCODE
8505 Op10mod4:
8506 lbl10mod4:      Op10
8507                         NEXTOPCODE
8508 Op11M0mod4:
8509 lbl11mod4a:     DirectIndirectIndexed1
8510 lbl11mod4b:     ORA16
8511                         NEXTOPCODE
8512 Op12M0mod4:
8513 lbl12mod4a:     DirectIndirect
8514 lbl12mod4b:     ORA16
8515                         NEXTOPCODE
8516 Op13M0mod4:
8517 lbl13mod4a:     StackasmRelativeIndirectIndexed1
8518 lbl13mod4b:     ORA16
8519                         NEXTOPCODE
8520 Op14M0mod4:
8521 lbl14mod4a:     Direct
8522 lbl14mod4b:     TRB16
8523                         NEXTOPCODE
8524 Op15M0mod4:
8525 lbl15mod4a:     DirectIndexedX1
8526 lbl15mod4b:     ORA16
8527                         NEXTOPCODE
8528 Op16M0mod4:
8529 lbl16mod4a:     DirectIndexedX1
8530 lbl16mod4b:     ASL16
8531                         NEXTOPCODE
8532 Op17M0mod4:
8533 lbl17mod4a:     DirectIndirectIndexedLong1
8534 lbl17mod4b:     ORA16
8535                         NEXTOPCODE
8536 Op18mod4:
8537 lbl18mod4:      Op18
8538                         NEXTOPCODE
8539 Op19M0mod4:
8540 lbl19mod4a:     AbsoluteIndexedY1
8541 lbl19mod4b:     ORA16
8542                         NEXTOPCODE
8543 Op1AM0mod4:
8544 lbl1Amod4a:     A_INC16
8545                         NEXTOPCODE
8546 Op1Bmod4:
8547 lbl1Bmod4:      Op1BM0
8548                         NEXTOPCODE
8549 Op1CM0mod4:
8550 lbl1Cmod4a:     Absolute
8551 lbl1Cmod4b:     TRB16
8552                         NEXTOPCODE
8553 Op1DM0mod4:
8554 lbl1Dmod4a:     AbsoluteIndexedX1
8555 lbl1Dmod4b:     ORA16
8556                         NEXTOPCODE
8557 Op1EM0mod4:
8558 lbl1Emod4a:     AbsoluteIndexedX1
8559 lbl1Emod4b:     ASL16
8560                         NEXTOPCODE
8561 Op1FM0mod4:
8562 lbl1Fmod4a:     AbsoluteLongIndexedX1
8563 lbl1Fmod4b:     ORA16
8564                         NEXTOPCODE
8565 Op20mod4:
8566 lbl20mod4:      Op20
8567                         NEXTOPCODE
8568 Op21M0mod4:
8569 lbl21mod4a:     DirectIndexedIndirect1
8570 lbl21mod4b:     AND16
8571                         NEXTOPCODE
8572 Op22mod4:
8573 lbl22mod4:      Op22
8574                         NEXTOPCODE
8575 Op23M0mod4:
8576 lbl23mod4a:     StackasmRelative
8577 lbl23mod4b:     AND16
8578                         NEXTOPCODE
8579 Op24M0mod4:
8580 lbl24mod4a:     Direct
8581 lbl24mod4b:     BIT16
8582                         NEXTOPCODE
8583 Op25M0mod4:
8584 lbl25mod4a:     Direct
8585 lbl25mod4b:     AND16
8586                         NEXTOPCODE
8587 Op26M0mod4:
8588 lbl26mod4a:     Direct
8589 lbl26mod4b:     ROL16
8590                         NEXTOPCODE
8591 Op27M0mod4:
8592 lbl27mod4a:     DirectIndirectLong
8593 lbl27mod4b:     AND16
8594                         NEXTOPCODE
8595 Op28mod4:
8596 lbl28mod4:      Op28X1M0
8597                         NEXTOPCODE
8598 .pool
8599 Op29M0mod4:
8600 lbl29mod4:      Op29M0
8601                         NEXTOPCODE
8602 Op2AM0mod4:
8603 lbl2Amod4a:     A_ROL16
8604                         NEXTOPCODE
8605 Op2Bmod4:
8606 lbl2Bmod4:      Op2B
8607                         NEXTOPCODE
8608 Op2CM0mod4:
8609 lbl2Cmod4a:     Absolute
8610 lbl2Cmod4b:     BIT16
8611                         NEXTOPCODE
8612 Op2DM0mod4:
8613 lbl2Dmod4a:     Absolute
8614 lbl2Dmod4b:     AND16
8615                         NEXTOPCODE
8616 Op2EM0mod4:
8617 lbl2Emod4a:     Absolute
8618 lbl2Emod4b:     ROL16
8619                         NEXTOPCODE
8620 Op2FM0mod4:
8621 lbl2Fmod4a:     AbsoluteLong
8622 lbl2Fmod4b:     AND16
8623                         NEXTOPCODE
8624 Op30mod4:
8625 lbl30mod4:      Op30
8626                         NEXTOPCODE
8627 Op31M0mod4:
8628 lbl31mod4a:     DirectIndirectIndexed1
8629 lbl31mod4b:     AND16
8630                         NEXTOPCODE
8631 Op32M0mod4:
8632 lbl32mod4a:     DirectIndirect
8633 lbl32mod4b:     AND16
8634                         NEXTOPCODE
8635 Op33M0mod4:
8636 lbl33mod4a:     StackasmRelativeIndirectIndexed1
8637 lbl33mod4b:     AND16
8638                         NEXTOPCODE
8639 Op34M0mod4:
8640 lbl34mod4a:     DirectIndexedX1
8641 lbl34mod4b:     BIT16
8642                         NEXTOPCODE
8643 Op35M0mod4:
8644 lbl35mod4a:     DirectIndexedX1
8645 lbl35mod4b:     AND16
8646                         NEXTOPCODE
8647 Op36M0mod4:
8648 lbl36mod4a:     DirectIndexedX1
8649 lbl36mod4b:     ROL16
8650                         NEXTOPCODE
8651 Op37M0mod4:
8652 lbl37mod4a:     DirectIndirectIndexedLong1
8653 lbl37mod4b:     AND16
8654                         NEXTOPCODE
8655 Op38mod4:
8656 lbl38mod4:      Op38
8657                         NEXTOPCODE
8658 Op39M0mod4:
8659 lbl39mod4a:     AbsoluteIndexedY1
8660 lbl39mod4b:     AND16
8661                         NEXTOPCODE
8662 Op3AM0mod4:
8663 lbl3Amod4a:     A_DEC16
8664                         NEXTOPCODE
8665 Op3Bmod4:
8666 lbl3Bmod4:      Op3BM0
8667                         NEXTOPCODE
8668 Op3CM0mod4:
8669 lbl3Cmod4a:     AbsoluteIndexedX1
8670 lbl3Cmod4b:     BIT16
8671                         NEXTOPCODE
8672 Op3DM0mod4:
8673 lbl3Dmod4a:     AbsoluteIndexedX1
8674 lbl3Dmod4b:     AND16
8675                         NEXTOPCODE
8676 Op3EM0mod4:
8677 lbl3Emod4a:     AbsoluteIndexedX1
8678 lbl3Emod4b:     ROL16
8679                         NEXTOPCODE
8680 Op3FM0mod4:
8681 lbl3Fmod4a:     AbsoluteLongIndexedX1
8682 lbl3Fmod4b:     AND16
8683                         NEXTOPCODE
8684 Op40mod4:
8685 lbl40mod4:      Op40X1M0
8686                         NEXTOPCODE
8687 .pool
8688 Op41M0mod4:
8689 lbl41mod4a:     DirectIndexedIndirect1
8690 lbl41mod4b:     EOR16
8691                         NEXTOPCODE
8692 Op42mod4:
8693 lbl42mod4:      Op42
8694                         NEXTOPCODE
8695 Op43M0mod4:
8696 lbl43mod4a:     StackasmRelative
8697 lbl43mod4b:     EOR16
8698                         NEXTOPCODE
8699 Op44X1mod4:
8700 lbl44mod4:      Op44X1M0
8701                         NEXTOPCODE
8702 Op45M0mod4:
8703 lbl45mod4a:     Direct
8704 lbl45mod4b:     EOR16
8705                         NEXTOPCODE
8706 Op46M0mod4:
8707 lbl46mod4a:     Direct
8708 lbl46mod4b:     LSR16
8709                         NEXTOPCODE
8710 Op47M0mod4:
8711 lbl47mod4a:     DirectIndirectLong
8712 lbl47mod4b:     EOR16
8713                         NEXTOPCODE
8714 Op48M0mod4:
8715 lbl48mod4:      Op48M0
8716                         NEXTOPCODE
8717 Op49M0mod4:
8718 lbl49mod4:      Op49M0
8719                         NEXTOPCODE
8720 Op4AM0mod4:
8721 lbl4Amod4a:     A_LSR16
8722                         NEXTOPCODE
8723 Op4Bmod4:
8724 lbl4Bmod4:      Op4B
8725                         NEXTOPCODE
8726 Op4Cmod4:
8727 lbl4Cmod4:      Op4C
8728                         NEXTOPCODE
8729 Op4DM0mod4:
8730 lbl4Dmod4a:     Absolute
8731 lbl4Dmod4b:     EOR16
8732                         NEXTOPCODE
8733 Op4EM0mod4:
8734 lbl4Emod4a:     Absolute
8735 lbl4Emod4b:     LSR16
8736                         NEXTOPCODE
8737 Op4FM0mod4:
8738 lbl4Fmod4a:     AbsoluteLong
8739 lbl4Fmod4b:     EOR16
8740                         NEXTOPCODE
8741 Op50mod4:
8742 lbl50mod4:      Op50
8743                         NEXTOPCODE
8744 Op51M0mod4:
8745 lbl51mod4a:     DirectIndirectIndexed1
8746 lbl51mod4b:     EOR16
8747                         NEXTOPCODE
8748 Op52M0mod4:
8749 lbl52mod4a:     DirectIndirect
8750 lbl52mod4b:     EOR16
8751                         NEXTOPCODE
8752 Op53M0mod4:
8753 lbl53mod4a:     StackasmRelativeIndirectIndexed1
8754 lbl53mod4b:     EOR16
8755                         NEXTOPCODE
8756 Op54X1mod4:
8757 lbl54mod4:      Op54X1M0
8758                         NEXTOPCODE
8759 Op55M0mod4:
8760 lbl55mod4a:     DirectIndexedX1
8761 lbl55mod4b:     EOR16
8762                         NEXTOPCODE
8763 Op56M0mod4:
8764 lbl56mod4a:     DirectIndexedX1
8765 lbl56mod4b:     LSR16
8766                         NEXTOPCODE
8767 Op57M0mod4:
8768 lbl57mod4a:     DirectIndirectIndexedLong1
8769 lbl57mod4b:     EOR16
8770                         NEXTOPCODE
8771 Op58mod4:
8772 lbl58mod4:      Op58
8773                         NEXTOPCODE
8774 Op59M0mod4:
8775 lbl59mod4a:     AbsoluteIndexedY1
8776 lbl59mod4b:     EOR16
8777                         NEXTOPCODE
8778 Op5AX1mod4:
8779 lbl5Amod4:      Op5AX1
8780                         NEXTOPCODE
8781 Op5Bmod4:
8782 lbl5Bmod4:      Op5BM0
8783                         NEXTOPCODE
8784 Op5Cmod4:
8785 lbl5Cmod4:      Op5C
8786                         NEXTOPCODE
8787 Op5DM0mod4:
8788 lbl5Dmod4a:     AbsoluteIndexedX1
8789 lbl5Dmod4b:     EOR16
8790                         NEXTOPCODE
8791 Op5EM0mod4:
8792 lbl5Emod4a:     AbsoluteIndexedX1
8793 lbl5Emod4b:     LSR16
8794                         NEXTOPCODE
8795 Op5FM0mod4:
8796 lbl5Fmod4a:     AbsoluteLongIndexedX1
8797 lbl5Fmod4b:     EOR16
8798                         NEXTOPCODE
8799 Op60mod4:
8800 lbl60mod4:      Op60
8801                         NEXTOPCODE
8802 Op61M0mod4:
8803 lbl61mod4a:     DirectIndexedIndirect1
8804 lbl61mod4b:     ADC16
8805                         NEXTOPCODE
8806 Op62mod4:
8807 lbl62mod4:      Op62
8808                         NEXTOPCODE
8809 Op63M0mod4:
8810 lbl63mod4a:     StackasmRelative
8811 lbl63mod4b:     ADC16
8812                         NEXTOPCODE
8813 .pool
8814 Op64M0mod4:
8815 lbl64mod4a:     Direct
8816 lbl64mod4b:     STZ16
8817                         NEXTOPCODE
8818 Op65M0mod4:
8819 lbl65mod4a:     Direct
8820 lbl65mod4b:     ADC16
8821                         NEXTOPCODE
8822 .pool
8823 Op66M0mod4:
8824 lbl66mod4a:     Direct
8825 lbl66mod4b:     ROR16
8826                         NEXTOPCODE
8827 Op67M0mod4:
8828 lbl67mod4a:     DirectIndirectLong
8829 lbl67mod4b:     ADC16
8830                         NEXTOPCODE
8831 .pool
8832 Op68M0mod4:
8833 lbl68mod4:      Op68M0
8834                         NEXTOPCODE
8835 Op69M0mod4:
8836 lbl69mod4a:     Immediate16
8837 lbl69mod4b:     ADC16
8838                         NEXTOPCODE
8839 .pool
8840 Op6AM0mod4:
8841 lbl6Amod4a:     A_ROR16
8842                         NEXTOPCODE
8843 Op6Bmod4:
8844 lbl6Bmod4:      Op6B
8845                         NEXTOPCODE
8846 Op6Cmod4:
8847 lbl6Cmod4:      Op6C
8848                         NEXTOPCODE
8849 Op6DM0mod4:
8850 lbl6Dmod4a:     Absolute
8851 lbl6Dmod4b:     ADC16
8852                         NEXTOPCODE
8853 Op6EM0mod4:
8854 lbl6Emod4a:     Absolute
8855 lbl6Emod4b:     ROR16
8856                         NEXTOPCODE
8857 Op6FM0mod4:
8858 lbl6Fmod4a:     AbsoluteLong
8859 lbl6Fmod4b:     ADC16
8860                         NEXTOPCODE
8861 Op70mod4:
8862 lbl70mod4:      Op70
8863                         NEXTOPCODE
8864 Op71M0mod4:
8865 lbl71mod4a:     DirectIndirectIndexed1
8866 lbl71mod4b:     ADC16
8867                         NEXTOPCODE
8868 Op72M0mod4:
8869 lbl72mod4a:     DirectIndirect
8870 lbl72mod4b:     ADC16
8871                         NEXTOPCODE
8872 Op73M0mod4:
8873 lbl73mod4a:     StackasmRelativeIndirectIndexed1
8874 lbl73mod4b:     ADC16
8875                         NEXTOPCODE
8876 .pool
8877 Op74M0mod4:
8878 lbl74mod4a:     DirectIndexedX1
8879 lbl74mod4b:     STZ16
8880                         NEXTOPCODE
8881 Op75M0mod4:
8882 lbl75mod4a:     DirectIndexedX1
8883 lbl75mod4b:     ADC16
8884                         NEXTOPCODE
8885 .pool
8886 Op76M0mod4:
8887 lbl76mod4a:     DirectIndexedX1
8888 lbl76mod4b:     ROR16
8889                         NEXTOPCODE
8890 Op77M0mod4:
8891 lbl77mod4a:     DirectIndirectIndexedLong1
8892 lbl77mod4b:     ADC16
8893                         NEXTOPCODE
8894 Op78mod4:
8895 lbl78mod4:      Op78
8896                         NEXTOPCODE
8897 Op79M0mod4:
8898 lbl79mod4a:     AbsoluteIndexedY1
8899 lbl79mod4b:     ADC16
8900                         NEXTOPCODE
8901 Op7AX1mod4:
8902 lbl7Amod4:      Op7AX1
8903                         NEXTOPCODE
8904 Op7Bmod4:
8905 lbl7Bmod4:      Op7BM0
8906                         NEXTOPCODE
8907 Op7Cmod4:
8908 lbl7Cmod4:      AbsoluteIndexedIndirectX1
8909                 Op7C
8910                         NEXTOPCODE
8911 Op7DM0mod4:
8912 lbl7Dmod4a:     AbsoluteIndexedX1
8913 lbl7Dmod4b:     ADC16
8914                         NEXTOPCODE
8915 Op7EM0mod4:
8916 lbl7Emod4a:     AbsoluteIndexedX1
8917 lbl7Emod4b:     ROR16
8918                         NEXTOPCODE
8919 Op7FM0mod4:
8920 lbl7Fmod4a:     AbsoluteLongIndexedX1
8921 lbl7Fmod4b:     ADC16
8922                         NEXTOPCODE
8923 .pool
8924 Op80mod4:
8925 lbl80mod4:      Op80
8926                         NEXTOPCODE
8927 Op81M0mod4:
8928 lbl81mod4a:     DirectIndexedIndirect1
8929 lbl81mod4b:     Op81M0
8930                         NEXTOPCODE
8931 Op82mod4:
8932 lbl82mod4:      Op82
8933                         NEXTOPCODE
8934 Op83M0mod4:
8935 lbl83mod4a:     StackasmRelative
8936 lbl83mod4b:     STA16
8937                         NEXTOPCODE
8938 Op84X1mod4:
8939 lbl84mod4a:     Direct
8940 lbl84mod4b:     STY8
8941                         NEXTOPCODE
8942 Op85M0mod4:
8943 lbl85mod4a:     Direct
8944 lbl85mod4b:     STA16
8945                         NEXTOPCODE
8946 Op86X1mod4:
8947 lbl86mod4a:     Direct
8948 lbl86mod4b:     STX8
8949                         NEXTOPCODE
8950 Op87M0mod4:
8951 lbl87mod4a:     DirectIndirectLong
8952 lbl87mod4b:     STA16
8953                         NEXTOPCODE
8954 Op88X1mod4:
8955 lbl88mod4:      Op88X1
8956                         NEXTOPCODE
8957 Op89M0mod4:
8958 lbl89mod4:      Op89M0
8959                         NEXTOPCODE
8960 Op8AM0mod4:
8961 lbl8Amod4:      Op8AM0X1
8962                         NEXTOPCODE
8963 Op8Bmod4:
8964 lbl8Bmod4:      Op8B
8965                         NEXTOPCODE
8966 Op8CX1mod4:
8967 lbl8Cmod4a:     Absolute
8968 lbl8Cmod4b:     STY8
8969                         NEXTOPCODE
8970 Op8DM0mod4:
8971 lbl8Dmod4a:     Absolute
8972 lbl8Dmod4b:     STA16
8973                         NEXTOPCODE
8974 Op8EX1mod4:
8975 lbl8Emod4a:     Absolute
8976 lbl8Emod4b:     STX8
8977                         NEXTOPCODE
8978 Op8FM0mod4:
8979 lbl8Fmod4a:     AbsoluteLong
8980 lbl8Fmod4b:     STA16
8981                         NEXTOPCODE
8982 Op90mod4:
8983 lbl90mod4:      Op90
8984                         NEXTOPCODE
8985 Op91M0mod4:
8986 lbl91mod4a:     DirectIndirectIndexed1
8987 lbl91mod4b:     STA16
8988                         NEXTOPCODE
8989 Op92M0mod4:
8990 lbl92mod4a:     DirectIndirect
8991 lbl92mod4b:     STA16
8992                         NEXTOPCODE
8993 Op93M0mod4:
8994 lbl93mod4a:     StackasmRelativeIndirectIndexed1
8995 lbl93mod4b:     STA16
8996                         NEXTOPCODE
8997 Op94X1mod4:
8998 lbl94mod4a:     DirectIndexedX1
8999 lbl94mod4b:     STY8
9000                         NEXTOPCODE
9001 Op95M0mod4:
9002 lbl95mod4a:     DirectIndexedX1
9003 lbl95mod4b:     STA16
9004                         NEXTOPCODE
9005 Op96X1mod4:
9006 lbl96mod4a:     DirectIndexedY1
9007 lbl96mod4b:     STX8
9008                         NEXTOPCODE
9009 Op97M0mod4:
9010 lbl97mod4a:     DirectIndirectIndexedLong1
9011 lbl97mod4b:     STA16
9012                         NEXTOPCODE
9013 Op98M0mod4:
9014 lbl98mod4:      Op98M0X1
9015                         NEXTOPCODE
9016 Op99M0mod4:
9017 lbl99mod4a:     AbsoluteIndexedY1
9018 lbl99mod4b:     STA16
9019                         NEXTOPCODE
9020 Op9Amod4:
9021 lbl9Amod4:      Op9AX1
9022                         NEXTOPCODE
9023 Op9BX1mod4:
9024 lbl9Bmod4:      Op9BX1
9025                         NEXTOPCODE
9026 Op9CM0mod4:
9027 lbl9Cmod4a:     Absolute
9028 lbl9Cmod4b:     STZ16
9029                         NEXTOPCODE
9030 Op9DM0mod4:
9031 lbl9Dmod4a:     AbsoluteIndexedX1
9032 lbl9Dmod4b:     STA16
9033                         NEXTOPCODE
9034 Op9EM0mod4:
9035 lbl9Emod4:      AbsoluteIndexedX1
9036                 STZ16
9037                         NEXTOPCODE
9038 Op9FM0mod4:
9039 lbl9Fmod4a:     AbsoluteLongIndexedX1
9040 lbl9Fmod4b:     STA16
9041                         NEXTOPCODE
9042 OpA0X1mod4:
9043 lblA0mod4:      OpA0X1
9044                         NEXTOPCODE
9045 OpA1M0mod4:
9046 lblA1mod4a:     DirectIndexedIndirect1
9047 lblA1mod4b:     LDA16
9048                         NEXTOPCODE
9049 OpA2X1mod4:
9050 lblA2mod4:      OpA2X1
9051                         NEXTOPCODE
9052 OpA3M0mod4:
9053 lblA3mod4a:     StackasmRelative
9054 lblA3mod4b:     LDA16
9055                         NEXTOPCODE
9056 OpA4X1mod4:
9057 lblA4mod4a:     Direct
9058 lblA4mod4b:     LDY8
9059                         NEXTOPCODE
9060 OpA5M0mod4:
9061 lblA5mod4a:     Direct
9062 lblA5mod4b:     LDA16
9063                         NEXTOPCODE
9064 OpA6X1mod4:
9065 lblA6mod4a:     Direct
9066 lblA6mod4b:     LDX8
9067                         NEXTOPCODE
9068 OpA7M0mod4:
9069 lblA7mod4a:     DirectIndirectLong
9070 lblA7mod4b:     LDA16
9071                         NEXTOPCODE
9072 OpA8X1mod4:
9073 lblA8mod4:      OpA8X1M0
9074                         NEXTOPCODE
9075 OpA9M0mod4:
9076 lblA9mod4:      OpA9M0
9077                         NEXTOPCODE
9078 OpAAX1mod4:
9079 lblAAmod4:      OpAAX1M0
9080                         NEXTOPCODE
9081 OpABmod4:
9082 lblABmod4:      OpAB
9083                         NEXTOPCODE
9084 OpACX1mod4:
9085 lblACmod4a:     Absolute
9086 lblACmod4b:     LDY8
9087                         NEXTOPCODE
9088 OpADM0mod4:
9089 lblADmod4a:     Absolute
9090 lblADmod4b:     LDA16
9091                         NEXTOPCODE
9092 OpAEX1mod4:
9093 lblAEmod4a:     Absolute
9094 lblAEmod4b:     LDX8
9095                         NEXTOPCODE
9096 OpAFM0mod4:
9097 lblAFmod4a:     AbsoluteLong
9098 lblAFmod4b:     LDA16
9099                         NEXTOPCODE
9100 OpB0mod4:
9101 lblB0mod4:      OpB0
9102                         NEXTOPCODE
9103 OpB1M0mod4:
9104 lblB1mod4a:     DirectIndirectIndexed1
9105 lblB1mod4b:     LDA16
9106                         NEXTOPCODE
9107 OpB2M0mod4:
9108 lblB2mod4a:     DirectIndirect
9109 lblB2mod4b:     LDA16
9110                         NEXTOPCODE
9111 OpB3M0mod4:
9112 lblB3mod4a:     StackasmRelativeIndirectIndexed1
9113 lblB3mod4b:     LDA16
9114                         NEXTOPCODE
9115 OpB4X1mod4:
9116 lblB4mod4a:     DirectIndexedX1
9117 lblB4mod4b:     LDY8
9118                         NEXTOPCODE
9119 OpB5M0mod4:
9120 lblB5mod4a:     DirectIndexedX1
9121 lblB5mod4b:     LDA16
9122                         NEXTOPCODE
9123 OpB6X1mod4:
9124 lblB6mod4a:     DirectIndexedY1
9125 lblB6mod4b:     LDX8
9126                         NEXTOPCODE
9127 OpB7M0mod4:
9128 lblB7mod4a:     DirectIndirectIndexedLong1
9129 lblB7mod4b:     LDA16
9130                         NEXTOPCODE
9131 OpB8mod4:
9132 lblB8mod4:      OpB8
9133                         NEXTOPCODE
9134 OpB9M0mod4:
9135 lblB9mod4a:     AbsoluteIndexedY1
9136 lblB9mod4b:     LDA16
9137                         NEXTOPCODE
9138 OpBAX1mod4:
9139 lblBAmod4:      OpBAX1
9140                         NEXTOPCODE
9141 OpBBX1mod4:
9142 lblBBmod4:      OpBBX1
9143                         NEXTOPCODE
9144 OpBCX1mod4:
9145 lblBCmod4a:     AbsoluteIndexedX1
9146 lblBCmod4b:     LDY8
9147                         NEXTOPCODE
9148 OpBDM0mod4:
9149 lblBDmod4a:     AbsoluteIndexedX1
9150 lblBDmod4b:     LDA16
9151                         NEXTOPCODE
9152 OpBEX1mod4:
9153 lblBEmod4a:     AbsoluteIndexedY1
9154 lblBEmod4b:     LDX8
9155                         NEXTOPCODE
9156 OpBFM0mod4:
9157 lblBFmod4a:     AbsoluteLongIndexedX1
9158 lblBFmod4b:     LDA16
9159                         NEXTOPCODE
9160 OpC0X1mod4:
9161 lblC0mod4:      OpC0X1
9162                         NEXTOPCODE
9163 OpC1M0mod4:
9164 lblC1mod4a:     DirectIndexedIndirect1
9165 lblC1mod4b:     CMP16
9166                         NEXTOPCODE
9167 OpC2mod4:
9168 lblC2mod4:      OpC2
9169                         NEXTOPCODE
9170 .pool
9171 OpC3M0mod4:
9172 lblC3mod4a:     StackasmRelative
9173 lblC3mod4b:     CMP16
9174                         NEXTOPCODE
9175 OpC4X1mod4:
9176 lblC4mod4a:     Direct
9177 lblC4mod4b:     CMY8
9178                         NEXTOPCODE
9179 OpC5M0mod4:
9180 lblC5mod4a:     Direct
9181 lblC5mod4b:     CMP16
9182                         NEXTOPCODE
9183 OpC6M0mod4:
9184 lblC6mod4a:     Direct
9185 lblC6mod4b:     DEC16
9186                         NEXTOPCODE
9187 OpC7M0mod4:
9188 lblC7mod4a:     DirectIndirectLong
9189 lblC7mod4b:     CMP16
9190                         NEXTOPCODE
9191 OpC8X1mod4:
9192 lblC8mod4:      OpC8X1
9193                         NEXTOPCODE
9194 OpC9M0mod4:
9195 lblC9mod4:      OpC9M0
9196                         NEXTOPCODE
9197 OpCAX1mod4:
9198 lblCAmod4:      OpCAX1
9199                         NEXTOPCODE
9200 OpCBmod4:
9201 lblCBmod4:      OpCB
9202                         NEXTOPCODE
9203 OpCCX1mod4:
9204 lblCCmod4a:     Absolute
9205 lblCCmod4b:     CMY8
9206                         NEXTOPCODE
9207 OpCDM0mod4:
9208 lblCDmod4a:     Absolute
9209 lblCDmod4b:     CMP16
9210                         NEXTOPCODE
9211 OpCEM0mod4:
9212 lblCEmod4a:     Absolute
9213 lblCEmod4b:     DEC16
9214                         NEXTOPCODE
9215 OpCFM0mod4:
9216 lblCFmod4a:     AbsoluteLong
9217 lblCFmod4b:     CMP16
9218                         NEXTOPCODE
9219 OpD0mod4:
9220 lblD0mod4:      OpD0
9221                         NEXTOPCODE
9222 OpD1M0mod4:
9223 lblD1mod4a:     DirectIndirectIndexed1
9224 lblD1mod4b:     CMP16
9225                         NEXTOPCODE
9226 OpD2M0mod4:
9227 lblD2mod4a:     DirectIndirect
9228 lblD2mod4b:     CMP16
9229                         NEXTOPCODE
9230 OpD3M0mod4:
9231 lblD3mod4a:     StackasmRelativeIndirectIndexed1
9232 lblD3mod4b:     CMP16
9233                         NEXTOPCODE
9234 OpD4mod4:
9235 lblD4mod4:      OpD4
9236                         NEXTOPCODE
9237 OpD5M0mod4:
9238 lblD5mod4a:     DirectIndexedX1
9239 lblD5mod4b:     CMP16
9240                         NEXTOPCODE
9241 OpD6M0mod4:
9242 lblD6mod4a:     DirectIndexedX1
9243 lblD6mod4b:     DEC16
9244                         NEXTOPCODE
9245 OpD7M0mod4:
9246 lblD7mod4a:     DirectIndirectIndexedLong1
9247 lblD7mod4b:     CMP16
9248                         NEXTOPCODE
9249 OpD8mod4:
9250 lblD8mod4:      OpD8
9251                         NEXTOPCODE
9252 OpD9M0mod4:
9253 lblD9mod4a:     AbsoluteIndexedY1
9254 lblD9mod4b:     CMP16
9255                         NEXTOPCODE
9256 OpDAX1mod4:
9257 lblDAmod4:      OpDAX1
9258                         NEXTOPCODE
9259 OpDBmod4:
9260 lblDBmod4:      OpDB
9261                         NEXTOPCODE
9262 OpDCmod4:
9263 lblDCmod4:      OpDC
9264                         NEXTOPCODE
9265 OpDDM0mod4:
9266 lblDDmod4a:     AbsoluteIndexedX1
9267 lblDDmod4b:     CMP16
9268                         NEXTOPCODE
9269 OpDEM0mod4:
9270 lblDEmod4a:     AbsoluteIndexedX1
9271 lblDEmod4b:     DEC16
9272                         NEXTOPCODE
9273 OpDFM0mod4:
9274 lblDFmod4a:     AbsoluteLongIndexedX1
9275 lblDFmod4b:     CMP16
9276                         NEXTOPCODE
9277 OpE0X1mod4:
9278 lblE0mod4:      OpE0X1
9279                         NEXTOPCODE
9280 OpE1M0mod4:
9281 lblE1mod4a:     DirectIndexedIndirect1
9282 lblE1mod4b:     SBC16
9283                         NEXTOPCODE
9284 OpE2mod4:
9285 lblE2mod4:      OpE2
9286                         NEXTOPCODE
9287 .pool
9288 OpE3M0mod4:
9289 lblE3mod4a:     StackasmRelative
9290 lblE3mod4b:     SBC16
9291                         NEXTOPCODE
9292 OpE4X1mod4:
9293 lblE4mod4a:     Direct
9294 lblE4mod4b:     CMX8
9295                         NEXTOPCODE
9296 OpE5M0mod4:
9297 lblE5mod4a:     Direct
9298 lblE5mod4b:     SBC16
9299                         NEXTOPCODE
9300 OpE6M0mod4:
9301 lblE6mod4a:     Direct
9302 lblE6mod4b:     INC16
9303                         NEXTOPCODE
9304 OpE7M0mod4:
9305 lblE7mod4a:     DirectIndirectLong
9306 lblE7mod4b:     SBC16
9307                         NEXTOPCODE
9308 OpE8X1mod4:
9309 lblE8mod4:      OpE8X1
9310                         NEXTOPCODE
9311 OpE9M0mod4:
9312 lblE9mod4a:     Immediate16
9313 lblE9mod4b:     SBC16
9314                         NEXTOPCODE
9315 OpEAmod4:
9316 lblEAmod4:      OpEA
9317                         NEXTOPCODE
9318 OpEBmod4:
9319 lblEBmod4:      OpEBM0
9320                         NEXTOPCODE
9321 OpECX1mod4:
9322 lblECmod4a:     Absolute
9323 lblECmod4b:     CMX8
9324                         NEXTOPCODE
9325 OpEDM0mod4:
9326 lblEDmod4a:     Absolute
9327 lblEDmod4b:     SBC16
9328                         NEXTOPCODE
9329 OpEEM0mod4:
9330 lblEEmod4a:     Absolute
9331 lblEEmod4b:     INC16
9332                         NEXTOPCODE
9333 OpEFM0mod4:
9334 lblEFmod4a:     AbsoluteLong
9335 lblEFmod4b:     SBC16
9336                         NEXTOPCODE
9337 OpF0mod4:
9338 lblF0mod4:      OpF0
9339                         NEXTOPCODE
9340 OpF1M0mod4:
9341 lblF1mod4a:     DirectIndirectIndexed1
9342 lblF1mod4b:     SBC16
9343                         NEXTOPCODE
9344 OpF2M0mod4:
9345 lblF2mod4a:     DirectIndirect
9346 lblF2mod4b:     SBC16
9347                         NEXTOPCODE
9348 OpF3M0mod4:
9349 lblF3mod4a:     StackasmRelativeIndirectIndexed1
9350 lblF3mod4b:     SBC16
9351                         NEXTOPCODE
9352 OpF4mod4:
9353 lblF4mod4:      OpF4
9354                         NEXTOPCODE
9355 OpF5M0mod4:
9356 lblF5mod4a:     DirectIndexedX1
9357 lblF5mod4b:     SBC16
9358                         NEXTOPCODE
9359 OpF6M0mod4:
9360 lblF6mod4a:     DirectIndexedX1
9361 lblF6mod4b:     INC16
9362                         NEXTOPCODE
9363 OpF7M0mod4:
9364 lblF7mod4a:     DirectIndirectIndexedLong1
9365 lblF7mod4b:     SBC16
9366                         NEXTOPCODE
9367 OpF8mod4:
9368 lblF8mod4:      OpF8
9369                         NEXTOPCODE
9370 OpF9M0mod4:
9371 lblF9mod4a:     AbsoluteIndexedY1
9372 lblF9mod4b:     SBC16
9373                         NEXTOPCODE
9374 OpFAX1mod4:
9375 lblFAmod4:      OpFAX1
9376                         NEXTOPCODE
9377 OpFBmod4:
9378 lblFBmod4:      OpFB
9379                         NEXTOPCODE
9380 OpFCmod4:
9381 lblFCmod4:      OpFCX1
9382                         NEXTOPCODE
9383 OpFDM0mod4:
9384 lblFDmod4a:     AbsoluteIndexedX1
9385 lblFDmod4b:     SBC16
9386                         NEXTOPCODE
9387 OpFEM0mod4:
9388 lblFEmod4a:     AbsoluteIndexedX1
9389 lblFEmod4b:     INC16
9390                         NEXTOPCODE
9391 OpFFM0mod4:
9392 lblFFmod4a:     AbsoluteLongIndexedX1
9393 lblFFmod4b:     SBC16
9394                         NEXTOPCODE
9395
9396
9397                         .pool
9398