2 /****************************************************************
3 ****************************************************************/
7 .equiv ASM_SPC700, 1 ;@ 1 = use notaz's ASM_SPC700 core
9 /****************************************************************
11 ****************************************************************/
15 rstatus .req R4 @ format : 0xff800000
16 reg_d_bank .req R4 @ format : 0x000000ll
17 reg_a .req R5 @ format : 0xhhll0000 or 0xll000000
18 reg_d .req R6 @ format : 0xhhll0000
19 reg_p_bank .req R6 @ format : 0x000000ll
20 reg_x .req R7 @ format : 0xhhll0000 or 0xll000000
21 reg_s .req R8 @ format : 0x0000hhll
22 reg_y .req R9 @ format : 0xhhll0000 or 0xll000000
24 rpc .req R10 @ 32bits address
25 reg_cycles .req R11 @ 32bits counter
26 regpcbase .req R12 @ 32bits address
28 rscratch .req R0 @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD
29 regopcode .req R0 @ format : 0x000000ll
30 rscratch2 .req R1 @ format : 0xhhll for calculation and value
32 rscratch4 .req R3 @ ??????
35 rscratch9 .req R10 @ ??????
42 @ R13 @ Pointer 32 bit on a struct.
58 .equ STATUS_SHIFTER, 24
59 .equ MASK_EMUL, (1<<(STATUS_SHIFTER-1))
60 .equ MASK_SHIFTER_CARRY, (STATUS_SHIFTER+1)
61 .equ MASK_CARRY, (1<<(STATUS_SHIFTER)) @ 0
62 .equ MASK_ZERO, (2<<(STATUS_SHIFTER)) @ 1
63 .equ MASK_IRQ, (4<<(STATUS_SHIFTER)) @ 2
64 .equ MASK_DECIMAL, (8<<(STATUS_SHIFTER)) @ 3
65 .equ MASK_INDEX, (16<<(STATUS_SHIFTER)) @ 4 @ 1
66 .equ MASK_MEM, (32<<(STATUS_SHIFTER)) @ 5 @ 2
67 .equ MASK_OVERFLOW, (64<<(STATUS_SHIFTER)) @ 6 @ 4
68 .equ MASK_NEG, (128<<(STATUS_SHIFTER))@ 7 @ 8
71 .equ SLOW_ONE_CYCLE, 8
73 .equ NMI_FLAG, (1 << 7)
74 .equ IRQ_PENDING_FLAG, (1 << 11)
75 .equ SCAN_KEYS_FLAG, (1 << 4)
78 .equ MEMMAP_BLOCK_SIZE, (0x1000)
80 .equ MEMMAP_MASK, (0xFFF)
82 /****************************************************************
84 ****************************************************************/
86 @ #include "os9x_65c816_mac_gen.h"
87 /*****************************************************************/
88 /* Offset in SCPUState structure */
89 /*****************************************************************/
91 .equ BranchSkip_ofs, 4
94 .equ WaitingForInterrupt_ofs, 7
111 .equ PCAtOpcodeStart_ofs, 36
112 .equ WaitAddress_ofs, 40
113 .equ WaitCounter_ofs, 44
114 .equ NextEvent_ofs, 48
115 .equ V_Counter_ofs, 52
116 .equ MemSpeed_ofs, 56
117 .equ MemSpeedx2_ofs, 60
118 .equ FastROMSpeed_ofs, 64
119 .equ AutoSaveTimer_ofs, 68
120 .equ NMITriggerPoint_ofs, 72
121 .equ NMICycleCount_ofs, 76
122 .equ IRQCycleCount_ofs, 80
126 .equ SRAMModified_ofs, 86
127 .equ BRKTriggered_ofs, 87
128 .equ asm_OPTABLE_ofs, 88
129 .equ TriedInterleavedMode2_ofs, 92
132 .equ WriteMap_ofs, 100
133 .equ MemorySpeed_ofs, 104
134 .equ BlockIsRAM_ofs, 108
139 .equ APUExecuting_ofs, 122
143 /*****************************************************************/
146 .macro PREPARE_C_CALL
149 .macro PREPARE_C_CALL_R0
150 STMFD R13!,{R0,R12,R14}
152 .macro PREPARE_C_CALL_R0R1
153 STMFD R13!,{R0,R1,R12,R14}
155 .macro PREPARE_C_CALL_LIGHT
158 .macro PREPARE_C_CALL_LIGHTR12
162 .macro RESTORE_C_CALL
165 .macro RESTORE_C_CALL_R0
166 LDMFD R13!,{R0,R12,R14}
168 .macro RESTORE_C_CALL_R1
169 LDMFD R13!,{R1,R12,R14}
171 .macro RESTORE_C_CALL_LIGHT
174 .macro RESTORE_C_CALL_LIGHTR12
182 add r0,reg_cpu_var,#8
183 ldmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
184 @ rstatus (P) & reg_d_bank
185 mov reg_d_bank,r1,lsl #16
186 mov reg_d_bank,reg_d_bank,lsr #24
188 orrs rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24
189 @ if Carry set, then EMULATION bit was set
190 orrcs rstatus,rstatus,#MASK_EMUL
192 mov reg_d,reg_a,lsr #16
193 mov reg_d,reg_d,lsl #8
194 orr reg_d,reg_d,r1,lsl #24
195 mov reg_d,reg_d,ror #24 @ 0xdddd00pb
197 mov reg_s,reg_x,lsr #16
198 @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
199 tst rstatus,#MASK_INDEX
200 movne reg_x,reg_x,lsl #24
201 movne reg_y,reg_y,lsl #24
202 moveq reg_x,reg_x,lsl #16
203 moveq reg_y,reg_y,lsl #16
204 tst rstatus,#MASK_MEM
205 movne reg_a,reg_a,lsl #24
206 moveq reg_a,reg_a,lsl #16
209 @ reg_d & reg_p_bank share the same register
210 LDRB reg_p_bank,[reg_cpu_var,#RPB_ofs]
211 LDRH rscratch,[reg_cpu_var,#RD_ofs]
212 ORR reg_d,reg_d,rscratch, LSL #16
213 @ rstatus & reg_d_bank share the same register
214 LDRB reg_d_bank,[reg_cpu_var,#RDB_ofs]
215 LDRH rscratch,[reg_cpu_var,#RP_ofs]
216 ORRS rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24
217 @ if Carry set, then EMULATION bit was set
218 ORRCS rstatus,rstatus,#MASK_EMUL
220 LDRH reg_a,[reg_cpu_var,#RA_ofs]
221 LDRH reg_x,[reg_cpu_var,#RX_ofs]
222 LDRH reg_y,[reg_cpu_var,#RY_ofs]
223 LDRH reg_s,[reg_cpu_var,#RS_ofs]
224 @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
225 TST rstatus,#MASK_INDEX
226 MOVNE reg_x,reg_x,LSL #24
227 MOVNE reg_y,reg_y,LSL #24
228 MOVEQ reg_x,reg_x,LSL #16
229 MOVEQ reg_y,reg_y,LSL #16
230 TST rstatus,#MASK_MEM
231 MOVNE reg_a,reg_a,LSL #24
232 MOVEQ reg_a,reg_a,LSL #16
234 LDR regpcbase,[reg_cpu_var,#PCBase_ofs]
235 LDR rpc,[reg_cpu_var,#PC_ofs]
236 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs]
243 @ reg_p_bank, reg_d_bank and rstatus
244 mov r1, rstatus, lsr #16
245 orr r1, r1, reg_p_bank, lsl #24
247 orrcs r1, r1, #0x100 @ EMULATION bit
248 orr r1, r1, reg_d_bank, lsl #24
251 tst rstatus,#MASK_MEM
252 ldrneh r0, [reg_cpu_var,#RA_ofs]
254 orrne reg_a, r0, reg_a,lsr #24
255 moveq reg_a, reg_a, lsr #16
256 mov reg_d, reg_d, lsr #16
257 orr reg_a, reg_a, reg_d, lsl #16
258 @ Shift X&Y according to the current mode (INDEX, MEMORY bits)
259 tst rstatus,#MASK_INDEX
260 movne reg_x,reg_x,LSR #24
261 movne reg_y,reg_y,LSR #24
262 moveq reg_x,reg_x,LSR #16
263 moveq reg_y,reg_y,LSR #16
265 orr reg_x, reg_x, reg_s, lsl #16
267 add r0,reg_cpu_var,#8
268 stmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
271 @ reg_d & reg_p_bank is same register
272 STRB reg_p_bank,[reg_cpu_var,#RPB_ofs]
273 MOV rscratch,reg_d, LSR #16
274 STRH rscratch,[reg_cpu_var,#RD_ofs]
275 @ rstatus & reg_d_bank is same register
276 STRB reg_d_bank,[reg_cpu_var,#RDB_ofs]
277 MOVS rscratch, rstatus, LSR #STATUS_SHIFTER
278 ORRCS rscratch,rscratch,#0x100 @ EMULATION bit
279 STRH rscratch,[reg_cpu_var,#RP_ofs]
281 @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
282 TST rstatus,#MASK_INDEX
283 MOVNE rscratch,reg_x,LSR #24
284 MOVNE rscratch2,reg_y,LSR #24
285 MOVEQ rscratch,reg_x,LSR #16
286 MOVEQ rscratch2,reg_y,LSR #16
287 STRH rscratch,[reg_cpu_var,#RX_ofs]
288 STRH rscratch2,[reg_cpu_var,#RY_ofs]
289 TST rstatus,#MASK_MEM
290 LDRNEH rscratch,[reg_cpu_var,#RA_ofs]
291 BICNE rscratch,rscratch,#0xFF
292 ORRNE rscratch,rscratch,reg_a,LSR #24
293 MOVEQ rscratch,reg_a,LSR #16
294 STRH rscratch,[reg_cpu_var,#RA_ofs]
296 STRH reg_s,[reg_cpu_var,#RS_ofs]
297 STR regpcbase,[reg_cpu_var,#PCBase_ofs]
298 STR rpc,[reg_cpu_var,#PC_ofs]
300 STR reg_cycles,[reg_cpu_var,#Cycles_ofs]
304 /*****************************************************************/
306 add reg_cycles,reg_cycles, #ONE_CYCLE
309 addne reg_cycles,reg_cycles, #ONE_CYCLE
312 addeq reg_cycles,reg_cycles, #ONE_CYCLE
316 add reg_cycles,reg_cycles, #(ONE_CYCLE*2)
319 addne reg_cycles,reg_cycles, #(ONE_CYCLE*2)
322 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
323 add reg_cycles,reg_cycles, #(ONE_CYCLE*2)
324 add reg_cycles, reg_cycles, rscratch, LSL #1
327 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
328 add reg_cycles,reg_cycles, #(ONE_CYCLE*2)
329 add reg_cycles, reg_cycles, rscratch
333 add reg_cycles,reg_cycles, #(ONE_CYCLE*3)
337 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
338 add reg_cycles,reg_cycles, #ONE_CYCLE
339 add reg_cycles, reg_cycles, rscratch
343 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
344 add reg_cycles,reg_cycles, #ONE_CYCLE
345 add reg_cycles, reg_cycles, rscratch, lsl #1
349 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
350 add reg_cycles, reg_cycles, rscratch
354 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
355 add reg_cycles, reg_cycles, rscratch, lsl #1
359 ldr rscratch,[reg_cpu_var,#MemSpeed_ofs]
360 add reg_cycles, rscratch, reg_cycles
361 add reg_cycles, reg_cycles, rscratch, lsl #1
366 BIC rstatus,rstatus,#MASK_DECIMAL
369 ORR rstatus,rstatus,#MASK_DECIMAL
372 ORR rstatus,rstatus,#MASK_IRQ
375 BIC rstatus,rstatus,#MASK_IRQ
379 @ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
380 LDR rscratch,[reg_cpu_var,#WaitAddress_ofs]
383 @ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
384 LDR rscratch,[reg_cpu_var,#Flags_ofs]
385 LDR rscratch2,[reg_cpu_var,#WaitCounter_ofs]
386 TST rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
388 MOVS rscratch2,rscratch2
390 @ CPU.WaitAddress = NULL;
392 STR rscratch,[reg_cpu_var,#WaitAddress_ofs]
394 @ S9xSA1ExecuteDuringSleep (); : TODO
396 @ CPU.Cycles = CPU.NextEvent;
397 LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs]
398 LDRB r0,[reg_cpu_var,#APUExecuting_ofs]
401 @ if (IAPU.APUExecuting)
403 ICPU.CPUExecuting = FALSE;
407 } while (APU.Cycles < CPU.NextEvent);
408 ICPU.CPUExecuting = TRUE;
416 if (CPU.WaitCounter >= 2)
423 @ SUBLS rscratch2,rscratch2,#1
425 STR rscratch2,[reg_cpu_var,#WaitCounter_ofs]
430 /*in rsctach : OpAddress
431 /*destroy rscratch2*/
432 LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
433 MOVS rscratch2,rscratch2
436 STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
437 SUB rscratch2,rpc,regpcbase
438 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
439 CMP rscratch2,rscratch
444 /*in rsctach : OpAddress
445 /*destroy rscratch2*/
446 LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
447 MOVS rscratch2,rscratch2
450 STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
451 SUB rscratch2,rpc,regpcbase
452 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
453 CMP rscratch2,rscratch
458 /*in rsctach : OpAddress
459 /*destroy rscratch2*/
460 LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
461 MOVS rscratch2,rscratch2
464 STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs]
465 SUB rscratch2,rpc,regpcbase
466 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
467 CMP rscratch2,rscratch
473 @ in : rscratch (0x00hhmmll)
477 LDR rpc,[reg_cpu_var,#PC_ofs]
478 LDR regpcbase,[reg_cpu_var,#PCBase_ofs]
482 TST rstatus,#MASK_EMUL
483 LDRNE rscratch, = jumptable1 @ Mode 0 : M=1,X=1
486 TST rstatus,#MASK_MEM
489 TST rstatus,#MASK_INDEX
490 @ INDEX=1 @ Mode 0 : M=1,X=1
491 LDRNE rscratch, = jumptable1
492 @ INDEX=0 @ Mode 1 : M=1,X=0
493 LDREQ rscratch, = jumptable2
496 TST rstatus,#MASK_INDEX
497 @ INDEX=1 @ Mode 3 : M=0,X=1
498 LDRNE rscratch, = jumptable4
499 @ INDEX=0 @ Mode 2 : M=0,X=0
500 LDREQ rscratch, = jumptable3
502 STR rscratch,[reg_cpu_var,#asm_OPTABLE_ofs]
520 .macro S9xDoHBlankProcessing
523 @ BL asm_S9xDoHBlankProcessing
524 BL S9xDoHBlankProcessing
529 /********************************/
531 LDR R1,[reg_cpu_var,#asm_OPTABLE_ofs]
532 STR rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs]
536 LDR PC, [R1,R0, LSL #2]
539 LDR rscratch,[reg_cpu_var,#NextEvent_ofs]
540 CMP reg_cycles,rscratch
542 S9xDoHBlankProcessing
546 .macro asmAPU_EXECUTE
547 LDRB R0,[reg_cpu_var,#APUExecuting_ofs]
548 CMP R0,#1 @ spc700 enabled, hack mode off
550 LDR R0,[reg_cpu_var,#APU_Cycles]
551 SUBS R0,reg_cycles,R0
554 PREPARE_C_CALL_LIGHTR12
556 RESTORE_C_CALL_LIGHTR12
557 SUB R0,reg_cycles,R0 @ sub cycles left
558 STR R0,[reg_cpu_var,#APU_Cycles]
561 STR reg_cycles,[reg_cpu_var,#Cycles_ofs]
562 PREPARE_C_CALL_LIGHTR12
564 RESTORE_C_CALL_LIGHTR12
565 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs]
572 .macro asmAPU_EXECUTE2
574 LDRB R0,[reg_cpu_var,#APUExecuting_ofs]
575 CMP R0,#1 @ spc700 enabled, hack mode off
577 LDR R0,[reg_cpu_var,#APU_Cycles]
578 SUBS R0,reg_cycles,R0 @ reg_cycles == NextEvent
580 PREPARE_C_CALL_LIGHTR12
582 RESTORE_C_CALL_LIGHTR12
583 SUB R0,reg_cycles,R0 @ sub cycles left
584 STR R0,[reg_cpu_var,#APU_Cycles]
588 STR reg_cycles,[reg_cpu_var,#Cycles_ofs]
589 PREPARE_C_CALL_LIGHTR12
591 RESTORE_C_CALL_LIGHTR12
592 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs]
597 @ #include "os9x_65c816_mac_mem.h"
599 @ in : rscratch (0x00hhmmll)
600 @ out : rscratch (0xhhll0000)
601 STMFD R13!,{PC} @ Push return address
607 @ in : rscratch (0x00hhmmll)
608 @ out : rscratch (0x0000hhll)
609 STMFD R13!,{PC} @ Push return address
613 .macro S9xGetWordRegStatus reg
614 @ in : rscratch (0x00hhmmll)
615 @ out : reg (0xhhll0000)
616 @ flags have to be updated with read value
617 STMFD R13!,{PC} @ Push return address
620 MOVS \reg, R0, LSL #16
622 .macro S9xGetWordRegNS reg
623 @ in : rscratch (0x00hhmmll)
624 @ out : reg (0xhhll0000)
625 @ DOES NOT DESTROY rscratch (R0)
627 STMFD R13!,{PC} @ Push return address
630 MOV \reg, R0, LSL #16
633 .macro S9xGetWordLowRegNS reg
634 @ in : rscratch (0x00hhmmll)
635 @ out : reg (0xhhll0000)
636 @ DOES NOT DESTROY rscratch (R0)
638 STMFD R13!,{PC} @ Push return address
646 @ in : rscratch (0x00hhmmll)
647 @ out : rscratch (0xll000000)
648 STMFD R13!,{PC} @ Push return address
654 @ in : rscratch (0x00hhmmll)
655 @ out : rscratch (0x000000ll)
660 .macro S9xGetByteRegStatus reg
661 @ in : rscratch (0x00hhmmll)
662 @ out : reg (0xll000000)
663 @ flags have to be updated with read value
664 STMFD R13!,{PC} @ Push return address
667 MOVS \reg, R0, LSL #24
669 .macro S9xGetByteRegNS reg
670 @ in : rscratch (0x00hhmmll)
671 @ out : reg (0xll000000)
672 @ DOES NOT DESTROY rscratch (R0)
674 STMFD R13!,{PC} @ Push return address
677 MOVS \reg, R0, LSL #24
680 .macro S9xGetByteLowRegNS reg
681 @ in : rscratch (0x00hhmmll)
682 @ out : reg (0x000000ll)
683 @ DOES NOT DESTROY rscratch (R0)
685 STMFD R13!,{PC} @ Push return address
692 .macro S9xSetWord regValue
693 @ in : regValue (0xhhll0000)
694 @ in : rscratch=address (0x00hhmmll)
695 MOV R1,\regValue, LSR #16
696 STMFD R13!,{PC} @ Push return address
700 .macro S9xSetWordZero
701 @ in : rscratch=address (0x00hhmmll)
703 STMFD R13!,{PC} @ Push return address
707 .macro S9xSetWordLow regValue
708 @ in : regValue (0x0000hhll)
709 @ in : rscratch=address (0x00hhmmll)
711 STMFD R13!,{PC} @ Push return address
715 .macro S9xSetByte regValue
716 @ in : regValue (0xll000000)
717 @ in : rscratch=address (0x00hhmmll)
718 MOV R1,\regValue, LSR #24
719 STMFD R13!,{PC} @ Push return address
723 .macro S9xSetByteZero
724 @ in : rscratch=address (0x00hhmmll)
726 STMFD R13!,{PC} @ Push return address
730 .macro S9xSetByteLow regValue
731 @ in : regValue (0x000000ll)
732 @ in : rscratch=address (0x00hhmmll)
734 STMFD R13!,{PC} @ Push return address
740 @ ===========================================
741 @ ===========================================
743 @ ===========================================
744 @ ===========================================
749 LDRB rscratch2 , [rpc, #1]
750 LDRB rscratch , [rpc],#2
751 ORR rscratch , rscratch, rscratch2, LSL #8
752 ORR rscratch , rscratch, reg_d_bank, LSL #16
754 .macro AbsoluteIndexedIndirectX0
756 LDRB rscratch2 , [rpc, #1]
757 LDRB rscratch , [rpc], #2
758 ORR rscratch , rscratch, rscratch2, LSL #8
759 ADD rscratch , reg_x, rscratch, LSL #16
760 MOV rscratch , rscratch, LSR #16
761 ORR rscratch , rscratch, reg_p_bank, LSL #16
765 .macro AbsoluteIndexedIndirectX1
767 LDRB rscratch2 , [rpc, #1]
768 LDRB rscratch , [rpc], #2
769 ORR rscratch , rscratch, rscratch2, LSL #8
770 ADD rscratch , rscratch, reg_x, LSR #24
771 BIC rscratch , rscratch, #0x00FF0000
772 ORR rscratch , rscratch, reg_p_bank, LSL #16
776 .macro AbsoluteIndirectLong
778 LDRB rscratch2 , [rpc, #1]
779 LDRB rscratch , [rpc], #2
780 ORR rscratch , rscratch, rscratch2, LSL #8
781 S9xGetWordLowRegNS rscratch2
782 ADD rscratch , rscratch, #2
783 STMFD r13!,{rscratch2}
785 LDMFD r13!,{rscratch2}
786 ORR rscratch , rscratch2, rscratch, LSL #16
788 .macro AbsoluteIndirect
790 LDRB rscratch2 , [rpc,#1]
791 LDRB rscratch , [rpc], #2
792 ORR rscratch , rscratch, rscratch2, LSL #8
794 ORR rscratch , rscratch, reg_p_bank, LSL #16
796 .macro AbsoluteIndexedX0
798 LDRB rscratch2 , [rpc, #1]
799 LDRB rscratch , [rpc], #2
800 ORR rscratch , rscratch, rscratch2, LSL #8
801 ORR rscratch , rscratch, reg_d_bank, LSL #16
802 ADD rscratch , rscratch, reg_x, LSR #16
804 .macro AbsoluteIndexedX1
806 LDRB rscratch2 , [rpc, #1]
807 LDRB rscratch , [rpc], #2
808 ORR rscratch , rscratch, rscratch2, LSL #8
809 ORR rscratch , rscratch, reg_d_bank, LSL #16
810 ADD rscratch , rscratch, reg_x, LSR #24
814 .macro AbsoluteIndexedY0
816 LDRB rscratch2 , [rpc, #1]
817 LDRB rscratch , [rpc], #2
818 ORR rscratch , rscratch, rscratch2, LSL #8
819 ORR rscratch , rscratch, reg_d_bank, LSL #16
820 ADD rscratch , rscratch, reg_y, LSR #16
822 .macro AbsoluteIndexedY1
824 LDRB rscratch2 , [rpc, #1]
825 LDRB rscratch , [rpc], #2
826 ORR rscratch , rscratch, rscratch2, LSL #8
827 ORR rscratch , rscratch, reg_d_bank, LSL #16
828 ADD rscratch , rscratch, reg_y, LSR #24
832 LDRB rscratch2 , [rpc, #1]
833 LDRB rscratch , [rpc], #2
834 ORR rscratch , rscratch, rscratch2, LSL #8
835 LDRB rscratch2 , [rpc], #1
836 ORR rscratch , rscratch, rscratch2, LSL #16
840 .macro AbsoluteLongIndexedX0
842 LDRB rscratch2 , [rpc, #1]
843 LDRB rscratch , [rpc], #2
844 ORR rscratch , rscratch, rscratch2, LSL #8
845 LDRB rscratch2 , [rpc], #1
846 ORR rscratch , rscratch, rscratch2, LSL #16
847 ADD rscratch , rscratch, reg_x, LSR #16
848 BIC rscratch, rscratch, #0xFF000000
850 .macro AbsoluteLongIndexedX1
852 LDRB rscratch2 , [rpc, #1]
853 LDRB rscratch , [rpc], #2
854 ORR rscratch , rscratch, rscratch2, LSL #8
855 LDRB rscratch2 , [rpc], #1
856 ORR rscratch , rscratch, rscratch2, LSL #16
857 ADD rscratch , rscratch, reg_x, LSR #24
858 BIC rscratch, rscratch, #0xFF000000
862 LDRB rscratch , [rpc], #1
863 ADD rscratch , reg_d, rscratch, LSL #16
864 MOV rscratch, rscratch, LSR #16
866 .macro DirectIndirect
868 LDRB rscratch , [rpc], #1
869 ADD rscratch , reg_d, rscratch, LSL #16
870 MOV rscratch, rscratch, LSR #16
872 ORR rscratch , rscratch, reg_d_bank, LSL #16
874 .macro DirectIndirectLong
876 LDRB rscratch , [rpc], #1
877 ADD rscratch , reg_d, rscratch, LSL #16
878 MOV rscratch, rscratch, LSR #16
879 S9xGetWordLowRegNS rscratch2
880 ADD rscratch , rscratch,#2
881 STMFD r13!,{rscratch2}
883 LDMFD r13!,{rscratch2}
884 ORR rscratch , rscratch2, rscratch, LSL #16
886 .macro DirectIndirectIndexed0
888 LDRB rscratch , [rpc], #1
889 ADD rscratch , reg_d, rscratch, LSL #16
890 MOV rscratch, rscratch, LSR #16
892 ORR rscratch, rscratch,reg_d_bank, LSL #16
893 ADD rscratch, rscratch,reg_y, LSR #16
895 .macro DirectIndirectIndexed1
897 LDRB rscratch , [rpc], #1
898 ADD rscratch , reg_d, rscratch, LSL #16
899 MOV rscratch, rscratch, LSR #16
901 ORR rscratch, rscratch,reg_d_bank, LSL #16
902 ADD rscratch, rscratch,reg_y, LSR #24
904 .macro DirectIndirectIndexedLong0
906 LDRB rscratch , [rpc], #1
907 ADD rscratch , reg_d, rscratch, LSL #16
908 MOV rscratch, rscratch, LSR #16
909 S9xGetWordLowRegNS rscratch2
910 ADD rscratch , rscratch,#2
911 STMFD r13!,{rscratch2}
913 LDMFD r13!,{rscratch2}
914 ORR rscratch , rscratch2, rscratch, LSL #16
915 ADD rscratch, rscratch,reg_y, LSR #16
917 .macro DirectIndirectIndexedLong1
919 LDRB rscratch , [rpc], #1
920 ADD rscratch , reg_d, rscratch, LSL #16
921 MOV rscratch, rscratch, LSR #16
922 S9xGetWordLowRegNS rscratch2
923 ADD rscratch , rscratch,#2
924 STMFD r13!,{rscratch2}
926 LDMFD r13!,{rscratch2}
927 ORR rscratch , rscratch2, rscratch, LSL #16
928 ADD rscratch, rscratch,reg_y, LSR #24
930 .macro DirectIndexedIndirect0
932 LDRB rscratch , [rpc], #1
933 ADD rscratch2 , reg_d , reg_x
934 ADD rscratch , rscratch2 , rscratch, LSL #16
935 MOV rscratch, rscratch, LSR #16
937 ORR rscratch , rscratch , reg_d_bank, LSL #16
939 .macro DirectIndexedIndirect1
941 LDRB rscratch , [rpc], #1
942 ADD rscratch2 , reg_d , reg_x, LSR #8
943 ADD rscratch , rscratch2 , rscratch, LSL #16
944 MOV rscratch, rscratch, LSR #16
946 ORR rscratch , rscratch , reg_d_bank, LSL #16
948 .macro DirectIndexedX0
950 LDRB rscratch , [rpc], #1
951 ADD rscratch2 , reg_d , reg_x
952 ADD rscratch , rscratch2 , rscratch, LSL #16
953 MOV rscratch, rscratch, LSR #16
955 .macro DirectIndexedX1
957 LDRB rscratch , [rpc], #1
958 ADD rscratch2 , reg_d , reg_x, LSR #8
959 ADD rscratch , rscratch2 , rscratch, LSL #16
960 MOV rscratch, rscratch, LSR #16
962 .macro DirectIndexedY0
964 LDRB rscratch , [rpc], #1
965 ADD rscratch2 , reg_d , reg_y
966 ADD rscratch , rscratch2 , rscratch, LSL #16
967 MOV rscratch, rscratch, LSR #16
969 .macro DirectIndexedY1
971 LDRB rscratch , [rpc], #1
972 ADD rscratch2 , reg_d , reg_y, LSR #8
973 ADD rscratch , rscratch2 , rscratch, LSL #16
974 MOV rscratch, rscratch, LSR #16
977 ADD rscratch, rpc, reg_p_bank, LSL #16
978 SUB rscratch, rscratch, regpcbase
982 ADD rscratch, rpc, reg_p_bank, LSL #16
983 SUB rscratch, rscratch, regpcbase
988 LDRSB rscratch , [rpc],#1
989 ADD rscratch , rscratch , rpc
990 SUB rscratch , rscratch, regpcbase
991 UXTH rscratch,rscratch
993 .macro asmRelativeLong
995 LDRB rscratch2 , [rpc, #1]
996 LDRB rscratch , [rpc], #2
997 ORR rscratch , rscratch, rscratch2, LSL #8
998 SUB rscratch2 , rpc, regpcbase
999 ADD rscratch , rscratch2, rscratch
1000 BIC rscratch,rscratch,#0x00FF0000
1004 .macro StackasmRelative
1006 LDRB rscratch , [rpc], #1
1007 ADD rscratch , rscratch, reg_s
1008 BIC rscratch,rscratch,#0x00FF0000
1010 .macro StackasmRelativeIndirectIndexed0
1012 LDRB rscratch , [rpc], #1
1013 ADD rscratch , rscratch, reg_s
1014 BIC rscratch,rscratch,#0x00FF0000
1016 ORR rscratch , rscratch, reg_d_bank, LSL #16
1017 ADD rscratch , rscratch, reg_y, LSR #16
1018 BIC rscratch, rscratch, #0xFF000000
1020 .macro StackasmRelativeIndirectIndexed1
1022 LDRB rscratch , [rpc], #1
1023 ADD rscratch , rscratch, reg_s
1024 BIC rscratch,rscratch,#0x00FF0000
1026 ORR rscratch , rscratch, reg_d_bank, LSL #16
1027 ADD rscratch , rscratch, reg_y, LSR #24
1028 BIC rscratch, rscratch, #0xFF000000
1032 /****************************************/
1044 SUB rscratch,reg_s,#1
1049 MOV rscratch2,rscratch
1050 SUB rscratch,reg_s,#1
1051 S9xSetWordLow rscratch2
1055 SUB rscratch,reg_s,#1
1063 ADD rscratch,reg_s,#1
1066 MOV \reg,rscratch,LSL #24
1069 ADD rscratch,reg_s,#1
1074 ADD rscratch,reg_s,#1
1080 ADD rscratch,reg_s,#1
1085 ADD rscratch,reg_s,#1
1088 MOV \reg,rscratch,LSL #16
1092 ADD rscratch,reg_s,#1
1101 ADD rscratch,reg_s,#1
1104 MOVS \reg,rscratch,LSL #24
1107 ADD rscratch,reg_s,#1
1110 MOVS rscratch,rscratch,LSL #24
1112 .macro PullBLowS reg
1113 ADD rscratch,reg_s,#1
1119 ADD rscratch,reg_s,#1
1122 MOVS rscratch,rscratch
1125 ADD rscratch,reg_s,#1
1128 MOVS \reg,rscratch, LSL #16
1131 ADD rscratch,reg_s,#1
1134 MOVS rscratch,rscratch, LSL #16
1136 .macro PullWLowS reg
1137 ADD rscratch,reg_s,#1
1143 ADD rscratch,reg_s,#1
1146 MOVS rscratch,rscratch
1149 @ START OF PROGRAM CODE
1153 .globl asmS9xGetByte
1154 .globl asmS9xGetWord
1155 .globl asmS9xSetByte
1156 .globl asmS9xSetWord
1158 @ uint8 aaS9xGetByte(uint32 address);
1160 @ in : R0 = 0x00hhmmll
1161 @ out : R0 = 0x000000ll
1162 @ DESTROYED : R1,R2,R3
1163 @ UPDATE : reg_cycles
1165 MOV R1,R0,LSR #MEMMAP_SHIFT
1166 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1167 @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1168 @ so AND MEMMAP_MASK is BIC 0xFF000
1170 @ R2 <= Map[block] (GetAddress)
1171 LDR R2,[reg_cpu_var,#Map_ofs]
1172 LDR R2,[R2,R1,LSL #2]
1174 BLO GBSpecial @ special
1175 @ Direct ROM/RAM acess
1176 @ R2 <= GetAddress + Address & 0xFFFF
1177 @ R3 <= MemorySpeed[block]
1178 LDR R3,[reg_cpu_var,#MemorySpeed_ofs]
1181 ADD R2,R2,R0,LSR #16
1183 ADD reg_cycles,reg_cycles,R3
1184 @ R3 = BlockIsRAM[block]
1185 LDR R3,[reg_cpu_var,#BlockIsRAM_ofs]
1186 @ Get value to return
1190 @ if BlockIsRAM => update for CPUShutdown
1191 LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1192 STRNE R1,[reg_cpu_var,#WaitAddress_ofs]
1194 LDMFD R13!,{PC} @ Return
1197 LDR PC,[PC,R2,LSL #2]
1198 MOV R0,R0 @ nop, for align
1216 LDRB R1,[reg_cpu_var,#InDMA_ofs]
1218 ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles
1219 MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF);
1220 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1225 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1226 LDMFD R13!,{PC} @ Return
1228 ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles
1229 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1230 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1235 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1236 LDMFD R13!,{PC} @ Return
1238 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1239 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1240 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1245 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1246 LDMFD R13!,{PC} @ Return
1248 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1249 LDRH R2,[reg_cpu_var,#SRAMMask]
1250 LDR R1,[reg_cpu_var,#SRAM]
1251 AND R0,R2,R0 @ Address&SRAMMask
1252 LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask
1256 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1260 MOV R1,R1,LSR #17 @ Address&0x7FFF
1261 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1263 LDRH R2,[reg_cpu_var,#SRAMMask]
1264 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1265 LDR R1,[reg_cpu_var,#SRAM]
1266 AND R0,R2,R0 @ Address&SRAMMask
1267 LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask
1268 LDMFD R13!,{PC} @ return
1273 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1277 /*ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1281 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1282 MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1283 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1288 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1289 LDMFD R13!,{PC} @ Return
1293 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1294 MOV R0,R0,LSR #17 @ Address&0x7FFF
1295 LDR R1,[reg_cpu_var,#BWRAM]
1296 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1297 LDRB R0,[R0,R1] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1301 @ uint16 aaS9xGetWord(uint32 address);
1303 @ in : R0 = 0x00hhmmll
1304 @ out : R0 = 0x000000ll
1305 @ DESTROYED : R1,R2,R3
1306 @ UPDATE : reg_cycles
1331 MOV R1,R0,LSR #MEMMAP_SHIFT
1332 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1333 @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1334 @ so AND MEMMAP_MASK is BIC 0xFF000
1336 @ R2 <= Map[block] (GetAddress)
1337 LDR R2,[reg_cpu_var,#Map_ofs]
1338 LDR R2,[R2,R1,LSL #2]
1340 BLO GWSpecial @ special
1341 @ Direct ROM/RAM acess
1345 @ R2 <= GetAddress + Address & 0xFFFF
1346 @ R3 <= MemorySpeed[block]
1347 LDR R3,[reg_cpu_var,#MemorySpeed_ofs]
1352 ADD reg_cycles,reg_cycles,R3, LSL #1
1353 @ R3 = BlockIsRAM[block]
1354 LDR R3,[reg_cpu_var,#BlockIsRAM_ofs]
1355 @ Get value to return
1359 @ if BlockIsRAM => update for CPUShutdown
1360 LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1361 STRNE R1,[reg_cpu_var,#WaitAddress_ofs]
1363 LDMFD R13!,{PC} @ Return
1368 LDRB R3,[R2,R3,LSR #16] @ GetAddress+ (Address+1)&0xFFFF
1369 LDRB R0,[R2,R0,LSR #16] @ GetAddress+ Address&0xFFFF
1372 @ if BlockIsRAM => update for CPUShutdown
1373 LDR R3,[reg_cpu_var,#BlockIsRAM_ofs]
1374 LDR R2,[reg_cpu_var,#MemorySpeed_ofs]
1375 LDRB R3,[R3,R1] @ R3 = BlockIsRAM[block]
1376 LDRB R2,[R2,R1] @ R2 <= MemorySpeed[block]
1377 MOVS R3,R3 @ IsRAM ? CPUShutdown stuff
1378 LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1379 STRNE R1,[reg_cpu_var,#WaitAddress_ofs]
1380 ADD reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles
1381 LDMFD R13!,{PC} @ Return
1383 LDR PC,[PC,R2,LSL #2]
1384 MOV R0,R0 @ nop, for align
1400 /* MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
1401 MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
1402 MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
1406 LDRB R1,[reg_cpu_var,#InDMA_ofs]
1408 ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles
1409 MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF);
1410 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1417 @ BIC R0,R0,#0x10000
1421 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1422 LDMFD R13!,{PC} @ Return
1424 ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles
1425 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1426 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1433 @ BIC R0,R0,#0x10000
1437 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1438 LDMFD R13!,{PC} @ Return
1440 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1441 MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1442 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1449 @ BIC R0,R0,#0x10000
1453 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1454 LDMFD R13!,{PC} @ Return
1456 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1460 LDRH R2,[reg_cpu_var,#SRAMMask]
1461 LDR R1,[reg_cpu_var,#SRAM]
1462 AND R3,R2,R0 @ Address&SRAMMask
1463 LDRH R0,[R3,R1] @ *Memory.SRAM + Address&SRAMMask
1464 LDMFD R13!,{PC} @ return
1466 LDRH R2,[reg_cpu_var,#SRAMMask]
1467 LDR R1,[reg_cpu_var,#SRAM]
1468 AND R3,R2,R0 @ Address&SRAMMask
1470 AND R2,R0,R2 @ Address&SRAMMask
1471 LDRB R3,[R1,R3] @ *Memory.SRAM + Address&SRAMMask
1472 LDRB R2,[R1,R2] @ *Memory.SRAM + Address&SRAMMask
1474 LDMFD R13!,{PC} @ return
1477 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1484 MOV R1,R1,LSR #17 @ Address&0x7FFF
1485 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1487 LDRH R2,[reg_cpu_var,#SRAMMask]
1488 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1489 LDR R1,[reg_cpu_var,#SRAM]
1490 AND R0,R2,R0 @ Address&SRAMMask
1491 LDRH R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask
1492 LDMFD R13!,{PC} @ return
1497 MOV R3,R3,LSR #17 @ Address&0x7FFF
1498 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1501 SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1504 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
1505 MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1507 LDRH R3,[reg_cpu_var,#SRAMMask] @ reload mask
1508 SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1509 AND R2,R3,R2 @ Address...&SRAMMask
1510 AND R0,R3,R0 @ (Address+1...)&SRAMMask
1512 LDR R3,[reg_cpu_var,#SRAM]
1513 LDRB R0,[R0,R3] @ *Memory.SRAM + (Address...)&SRAMMask
1514 LDRB R2,[R2,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask
1517 LDMFD R13!,{PC} @ return
1522 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1527 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1531 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1532 MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1533 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1540 @ BIC R0,R0,#0x10000
1544 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1545 LDMFD R13!,{PC} @ Return
1550 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1551 MOV R0,R0,LSR #17 @ Address&0x7FFF
1552 LDR R1,[reg_cpu_var,#BWRAM]
1553 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1554 LDRH R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1555 LDMFD R13!,{PC} @ return
1558 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1560 MOV R0,R0,LSR #17 @ Address&0x7FFF
1561 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
1562 LDR R1,[reg_cpu_var,#BWRAM]
1563 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1564 SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
1565 LDRB R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1566 LDRB R3,[R1,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1568 LDMFD R13!,{PC} @ return
1573 @ void aaS9xSetByte(uint32 address,uint8 val);
1575 @ in : R0=0x00hhmmll R1=0x000000ll
1576 @ DESTROYED : R0,R1,R2,R3
1577 @ UPDATE : reg_cycles
1580 STR R2,[reg_cpu_var,#WaitAddress_ofs]
1584 MOV R3,R0,LSR #MEMMAP_SHIFT
1585 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1586 @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1587 @ so AND MEMMAP_MASK is BIC 0xFF000
1589 @ R2 <= Map[block] (SetAddress)
1590 LDR R2,[reg_cpu_var,#WriteMap_ofs]
1591 LDR R2,[R2,R3,LSL #2]
1593 BLO SBSpecial @ special
1594 @ Direct ROM/RAM acess
1596 @ R2 <= SetAddress + Address & 0xFFFF
1598 ADD R2,R2,R0,LSR #16
1599 LDR R0,[reg_cpu_var,#MemorySpeed_ofs]
1602 @ R0 <= MemorySpeed[block]
1605 ADD reg_cycles,reg_cycles,R0
1607 @ only SA1 here : TODO
1611 LDR PC,[PC,R2,LSL #2]
1612 MOV R0,R0 @ nop, for align
1630 LDRB R2,[reg_cpu_var,#InDMA_ofs]
1632 ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles
1634 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1642 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1643 LDMFD R13!,{PC} @ Return
1645 ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles
1647 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1648 MOV R0,R0,LSR #16 @ Address&0xFFFF
1655 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1656 LDMFD R13!,{PC} @ Return
1658 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1660 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1661 MOV R0,R0,LSR #16 @ Address&0xFFFF
1668 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1669 LDMFD R13!,{PC} @ Return
1671 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1672 LDRH R2,[reg_cpu_var,#SRAMMask]
1674 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1675 LDR R3,[reg_cpu_var,#SRAM]
1676 AND R0,R2,R0 @ Address&SRAMMask
1677 STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1680 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1681 LDMFD R13!,{PC} @ return
1684 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1688 MOV R3,R3,LSR #17 @ Address&0x7FFF
1689 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1692 LDRH R2,[reg_cpu_var,#SRAMMask]
1694 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1696 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1697 LDR R3,[reg_cpu_var,#SRAM]
1698 AND R0,R2,R0 @ Address&SRAMMask
1699 STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1702 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1703 LDMFD R13!,{PC} @ return
1708 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1711 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1713 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1714 MOV R0,R0,LSR #16 @ Address&0xFFFF
1721 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1722 LDMFD R13!,{PC} @ Return
1725 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1726 MOV R0,R0,LSR #17 @ Address&0x7FFF
1727 LDR R2,[reg_cpu_var,#BWRAM]
1728 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1729 STRB R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1732 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1738 @ void aaS9xSetWord(uint32 address,uint16 val);
1740 @ in : R0 = 0x00hhmmll R1=0x0000hhll
1741 @ DESTROYED : R0,R1,R2,R3
1742 @ UPDATE : reg_cycles
1766 STR R2,[reg_cpu_var,#WaitAddress_ofs]
1769 MOV R3,R0,LSR #MEMMAP_SHIFT
1770 @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1771 @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1772 @ so AND MEMMAP_MASK is BIC 0xFF000
1774 @ R2 <= Map[block] (SetAddress)
1775 LDR R2,[reg_cpu_var,#WriteMap_ofs]
1776 LDR R2,[R2,R3,LSL #2]
1778 BLO SWSpecial @ special
1779 @ Direct ROM/RAM acess
1782 @ check if address is 16bits aligned or not
1787 ADD R2,R2,R0,LSR #16 @ address & 0xFFFF + SetAddress
1788 LDR R0,[reg_cpu_var,#MemorySpeed_ofs]
1791 @ R1 <= MemorySpeed[block]
1794 ADD reg_cycles,reg_cycles,R0, LSL #1
1796 @ only SA1 here : TODO
1801 @ R1 = (Address&0xFFFF)<<16
1803 @ First write @address
1804 STRB R1,[R2,R0,LSR #16]
1807 @ Second write @address+1
1808 STRB R1,[R2,R0,LSR #16]
1809 @ R1 <= MemorySpeed[block]
1810 LDR R0,[reg_cpu_var,#MemorySpeed_ofs]
1813 ADD reg_cycles,reg_cycles,R0,LSL #1
1815 @ only SA1 here : TODO
1819 LDR PC,[PC,R2,LSL #2]
1820 MOV R0,R0 @ nop, for align
1838 LDRB R2,[reg_cpu_var,#InDMA_ofs]
1840 ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles
1842 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1856 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1857 LDMFD R13!,{PC} @ Return
1859 ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles
1861 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1862 MOV R0,R0,LSR #16 @ Address&0xFFFF
1871 UXTB R0,R0,ROR #8 @ ((R0 >> 8) & 0xFF)
1875 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1876 LDMFD R13!,{PC} @ Return
1878 ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles
1880 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1881 MOV R0,R0,LSR #16 @ Address&0xFFFF
1894 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1895 LDMFD R13!,{PC} @ Return
1897 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1898 LDRH R2,[reg_cpu_var,#SRAMMask]
1900 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1902 AND R3,R2,R0 @ Address&SRAMMask
1906 LDR R0,[reg_cpu_var,#SRAM]
1907 STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1909 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1910 LDMFD R13!,{PC} @ return
1914 AND R2,R2,R0 @ (Address+1)&SRAMMask
1915 LDR R0,[reg_cpu_var,#SRAM]
1916 STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1918 STRB R1,[R0,R2] @ *Memory.SRAM + (Address+1)&SRAMMask
1920 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1921 LDMFD R13!,{PC} @ return
1924 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1926 LDRH R2,[reg_cpu_var,#SRAMMask]
1928 LDMEQFD R13!,{PC} @ return if SRAMMask=0
1935 MOV R3,R3,LSR #17 @ Address&0x7FFF
1936 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1938 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1939 LDRH R2,[reg_cpu_var,#SRAMMask]
1940 LDR R3,[reg_cpu_var,#SRAM]
1941 AND R0,R2,R0 @ Address&SRAMMask
1942 STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask
1944 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1945 LDMFD R13!,{PC} @ return
1949 MOV R3,R3,LSR #17 @ Address&0x7FFF
1950 MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1952 SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1957 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
1958 MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1960 LDRH R3,[reg_cpu_var,#SRAMMask] @ reload mask
1961 SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1962 AND R2,R3,R2 @ Address...&SRAMMask
1963 AND R0,R3,R0 @ (Address+1...)&SRAMMask
1965 LDR R3,[reg_cpu_var,#SRAM]
1966 STRB R1,[R2,R3] @ *Memory.SRAM + (Address...)&SRAMMask
1968 STRB R1,[R0,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask
1971 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
1972 LDMFD R13!,{PC} @ return
1977 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1978 LDMFD R13!,{PC} @ return
1980 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
1982 STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1983 MOV R0,R0,LSR #16 @ Address&0xFFFF
1996 LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1997 LDMFD R13!,{PC} @ Return
1999 ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles
2004 LDR R2,[reg_cpu_var,#BWRAM]
2005 MOV R0,R0,LSR #17 @ Address&0x7FFF
2006 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2008 STRH R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2009 STRB R3,[reg_cpu_var,#SRAMModified_ofs]
2010 LDMFD R13!,{PC} @ return
2014 MOV R0,R0,LSR #17 @ Address&0x7FFF
2015 MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF
2016 LDR R2,[reg_cpu_var,#BWRAM]
2017 SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2018 SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
2019 STRB R1,[R2,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2021 STRB R1,[R2,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
2023 STRB R0,[reg_cpu_var,#SRAMModified_ofs]
2024 LDMFD R13!,{PC} @ return
2030 /*****************************************************************
2032 *****************************************************************/
2035 @ CC : ARM Carry Clear
2036 BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2037 @ CS : ARM Carry Set
2038 ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2041 @ NE : ARM Zero Clear
2042 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2044 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2047 @ NE : ARM Zero Clear
2048 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2050 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2051 @ PL : ARM Neg Clear
2052 BICPL rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2054 ORRMI rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one
2057 /*****************************************************************
2059 *****************************************************************/
2065 TST rstatus, #MASK_DECIMAL
2070 STMFD R13!,{rscratch}
2071 MOV rscratch4,#0x0F000000
2072 @ rscratch2=xxW1xxxxxxxxxxxx
2073 AND rscratch2, rscratch, rscratch4
2074 @ rscratch=xxW2xxxxxxxxxxxx
2075 AND rscratch, rscratch4, rscratch, LSR #4
2076 @ rscratch3=xxA2xxxxxxxxxxxx
2077 AND rscratch3, rscratch4, reg_a, LSR #4
2078 @ rscratch4=xxA1xxxxxxxxxxxx
2079 AND rscratch4,reg_a,rscratch4
2081 TST rstatus, #MASK_CARRY
2082 ADDNE rscratch2, rscratch2, #0x01000000
2083 ADD rscratch2,rscratch2,rscratch4
2085 CMP rscratch2, #0x09000000
2087 SUBGT rscratch2, rscratch2, #0x0A000000
2089 ADDGT rscratch3, rscratch3, #0x01000000
2091 ADD rscratch3, rscratch3, rscratch
2093 CMP rscratch3, #0x09000000
2095 SUBGT rscratch3, rscratch3, #0x0A000000
2097 ORRGT rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2099 BICLE rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2100 @ gather rscratch3 and rscratch2 into ans8
2101 @ rscratch3 : 0R2000000
2102 @ rscratch2 : 0R1000000
2104 ORR rscratch2, rscratch2, rscratch3, LSL #4
2105 LDMFD R13!,{rscratch}
2107 AND rscratch,rscratch,#0x80000000
2108 @ (register.AL ^ Work8)
2109 EORS rscratch3, reg_a, rscratch
2110 BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2113 EORS rscratch3, rscratch2, rscratch
2115 TSTNE rscratch3,#0x80000000
2116 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2117 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2119 MOVS reg_a, rscratch2
2124 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2125 SUBCS rscratch, rscratch, #0x100
2126 ADCS reg_a, reg_a, rscratch, ROR #8
2128 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2129 BICVC rstatus, rstatus, #MASK_OVERFLOW
2133 ANDS reg_a, reg_a, #0xFF000000
2140 TST rstatus, #MASK_DECIMAL
2144 @ rscratch = W3W2W1W0........
2145 LDR rscratch4, = 0x0F0F0000
2146 @ rscratch2 = xxW2xxW0xxxxxx
2147 @ rscratch3 = xxW3xxW1xxxxxx
2148 AND rscratch2, rscratch4, rscratch
2149 AND rscratch3, rscratch4, rscratch, LSR #4
2150 @ rscratch2 = xxW3xxW1xxW2xxW0
2151 ORR rscratch2, rscratch3, rscratch2, LSR #16
2152 @ rscratch3 = xxA2xxA0xxxxxx
2153 @ rscratch4 = xxA3xxA1xxxxxx
2154 @ rscratch2 = xxA3xxA1xxA2xxA0
2155 AND rscratch3, rscratch4, reg_a
2156 AND rscratch4, rscratch4, reg_a, LSR #4
2157 ORR rscratch3, rscratch4, rscratch3, LSR #16
2158 ADD rscratch2, rscratch3, rscratch2
2159 LDR rscratch4, = 0x0F0F0000
2161 TST rstatus, #MASK_CARRY
2162 ADDNE rscratch2, rscratch2, #0x1
2163 @ rscratch2 = A + W + C
2165 AND rscratch3, rscratch2, #0x0000001F
2166 CMP rscratch3, #0x00000009
2167 ADDHI rscratch2, rscratch2, #0x00010000
2168 SUBHI rscratch2, rscratch2, #0x0000000A
2170 AND rscratch3, rscratch2, #0x001F0000
2171 CMP rscratch3, #0x00090000
2172 ADDHI rscratch2, rscratch2, #0x00000100
2173 SUBHI rscratch2, rscratch2, #0x000A0000
2175 AND rscratch3, rscratch2, #0x00001F00
2176 CMP rscratch3, #0x00000900
2177 SUBHI rscratch2, rscratch2, #0x00000A00
2178 ADDHI rscratch2, rscratch2, #0x01000000
2180 AND rscratch3, rscratch2, #0x1F000000
2181 CMP rscratch3, #0x09000000
2182 SUBHI rscratch2, rscratch2, #0x0A000000
2184 ORRHI rstatus, rstatus, #MASK_CARRY
2186 BICLS rstatus, rstatus, #MASK_CARRY
2187 @ rscratch2 = xxR3xxR1xxR2xxR0
2189 @ rscratch3 = xxR3xxR1xxxxxxxx
2190 AND rscratch3, rscratch4, rscratch2
2191 @ rscratch2 = xxR2xxR0xxxxxxxx
2192 AND rscratch2, rscratch4, rscratch2,LSL #16
2193 @ rscratch2 = R3R2R1R0xxxxxxxx
2194 ORR rscratch2, rscratch2,rscratch3,LSL #4
2196 AND rscratch,rscratch,#0x80000000
2197 @ (register.AL ^ Work8)
2198 EORS rscratch3, reg_a, rscratch
2199 BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2202 EORS rscratch3, rscratch2, rscratch
2203 TSTNE rscratch3,#0x80000000
2204 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2205 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2207 MOVS reg_a, rscratch2
2212 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2213 SUBCS rscratch, rscratch, #0x10000
2214 ADCS reg_a, reg_a,rscratch, ROR #16
2216 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2217 BICVC rstatus, rstatus, #MASK_OVERFLOW
2218 MOV reg_a, reg_a, LSR #16
2222 MOVS reg_a, reg_a, LSL #16
2231 ANDS reg_a, reg_a, rscratch
2236 ANDS reg_a, reg_a, rscratch
2241 MOVS reg_a, reg_a, LSL #1
2248 MOVS reg_a, reg_a, LSL #1
2254 S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch
2255 MOVS rscratch2, rscratch2, LSL #1
2258 S9xSetWord rscratch2
2262 S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch
2263 MOVS rscratch2, rscratch2, LSL #1
2266 S9xSetByte rscratch2
2271 MOVS rscratch2, rscratch, LSL #1
2272 @ Trick in ASM : shift one more bit : ARM C = Snes N
2274 @ If Carry Set, then Set Neg in SNES
2275 BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set C to zero
2276 ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set C to one
2277 @ If Neg Set, then Set Overflow in SNES
2278 BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set N to zero
2279 ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set N to one
2281 @ Now do a real AND with A register
2282 @ Set Zero Flag, bit test
2283 ANDS rscratch2, reg_a, rscratch
2284 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2285 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2290 MOVS rscratch2, rscratch, LSL #1
2291 @ Trick in ASM : shift one more bit : ARM C = Snes N
2293 @ If Carry Set, then Set Neg in SNES
2294 BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2295 ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one
2296 @ If Neg Set, then Set Overflow in SNES
2297 BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2298 ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2299 @ Now do a real AND with A register
2300 @ Set Zero Flag, bit test
2301 ANDS rscratch2, reg_a, rscratch
2302 @ Bit set ->Z=0->xxxNE Clear flag
2303 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2304 @ Bit clear->Z=1->xxxEQ Set flag
2305 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2309 SUBS rscratch2,reg_a,rscratch
2310 BICCC rstatus, rstatus, #MASK_CARRY
2311 ORRCS rstatus, rstatus, #MASK_CARRY
2317 SUBS rscratch2,reg_a,rscratch
2318 BICCC rstatus, rstatus, #MASK_CARRY
2319 ORRCS rstatus, rstatus, #MASK_CARRY
2325 SUBS rscratch2,reg_x,rscratch
2326 BICCC rstatus, rstatus, #MASK_CARRY
2327 ORRCS rstatus, rstatus, #MASK_CARRY
2332 SUBS rscratch2,reg_x,rscratch
2333 BICCC rstatus, rstatus, #MASK_CARRY
2334 ORRCS rstatus, rstatus, #MASK_CARRY
2339 SUBS rscratch2,reg_y,rscratch
2340 BICCC rstatus, rstatus, #MASK_CARRY
2341 ORRCS rstatus, rstatus, #MASK_CARRY
2346 SUBS rscratch2,reg_y,rscratch
2347 BICCC rstatus, rstatus, #MASK_CARRY
2348 ORRCS rstatus, rstatus, #MASK_CARRY
2353 SUBS reg_a, reg_a, #0x01000000
2354 STR rscratch,[reg_cpu_var,#WaitAddress_ofs]
2360 SUBS reg_a, reg_a, #0x00010000
2361 STR rscratch,[reg_cpu_var,#WaitAddress_ofs]
2366 S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch
2368 SUBS rscratch2, rscratch2, #0x00010000
2369 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2371 S9xSetWord rscratch2
2375 S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch
2377 SUBS rscratch2, rscratch2, #0x01000000
2378 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2380 S9xSetByte rscratch2
2385 EORS reg_a, reg_a, rscratch
2390 EORS reg_a, reg_a, rscratch
2395 ADDS reg_a, reg_a, #0x01000000
2396 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2402 ADDS reg_a, reg_a, #0x00010000
2403 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2408 S9xGetWordRegNS rscratch2
2410 ADDS rscratch2, rscratch2, #0x00010000
2411 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2413 S9xSetWord rscratch2
2417 S9xGetByteRegNS rscratch2
2419 ADDS rscratch2, rscratch2, #0x01000000
2420 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2422 S9xSetByte rscratch2
2426 S9xGetWordRegStatus reg_a
2430 S9xGetByteRegStatus reg_a
2434 S9xGetWordRegStatus reg_x
2438 S9xGetByteRegStatus reg_x
2442 S9xGetWordRegStatus reg_y
2446 S9xGetByteRegStatus reg_y
2450 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2451 MOVS reg_a, reg_a, LSR #17 @ hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
2453 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2454 MOV reg_a, reg_a, LSL #16 @ -> 0lllllll 00000000 00000000 00000000
2455 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2456 @ Note : the two MOV are included between instruction, to optimize
2462 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2463 MOVS reg_a, reg_a, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2465 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2466 MOV reg_a, reg_a, LSL #24 @ -> 00000000 00000000 00000000 0lllllll
2467 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2468 @ Note : the two MOV are included between instruction, to optimize
2474 S9xGetWordRegNS rscratch2
2475 @ N set to zero by >> 1 LSR
2476 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2477 MOVS rscratch2, rscratch2, LSR #17 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2479 BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2480 ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2482 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2483 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2484 S9xSetWordLow rscratch2
2488 S9xGetByteRegNS rscratch2
2489 @ N set to zero by >> 1 LSR
2490 BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero
2491 MOVS rscratch2, rscratch2, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2493 BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2494 ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2496 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2497 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2498 S9xSetByteLow rscratch2
2503 ORRS reg_a, reg_a, rscratch
2508 ORRS reg_a, reg_a, rscratch
2512 TST rstatus, #MASK_CARRY
2513 ORRNE reg_a, reg_a, #0x00008000
2514 MOVS reg_a, reg_a, LSL #1
2520 TST rstatus, #MASK_CARRY
2521 ORRNE reg_a, reg_a, #0x00800000
2522 MOVS reg_a, reg_a, LSL #1
2528 S9xGetWordRegNS rscratch2
2529 TST rstatus, #MASK_CARRY
2530 ORRNE rscratch2, rscratch2, #0x00008000
2531 MOVS rscratch2, rscratch2, LSL #1
2534 S9xSetWord rscratch2
2538 S9xGetByteRegNS rscratch2
2539 TST rstatus, #MASK_CARRY
2540 ORRNE rscratch2, rscratch2, #0x00800000
2541 MOVS rscratch2, rscratch2, LSL #1
2544 S9xSetByte rscratch2
2548 MOV reg_a,reg_a, LSR #16
2549 TST rstatus, #MASK_CARRY
2550 ORRNE reg_a, reg_a, #0x00010000
2551 ORRNE rstatus,rstatus,#MASK_NEG
2552 BICEQ rstatus,rstatus,#MASK_NEG
2553 MOVS reg_a,reg_a,LSR #1
2556 MOV reg_a,reg_a, LSL #16
2560 MOV reg_a,reg_a, LSR #24
2561 TST rstatus, #MASK_CARRY
2562 ORRNE reg_a, reg_a, #0x00000100
2563 ORRNE rstatus,rstatus,#MASK_NEG
2564 BICEQ rstatus,rstatus,#MASK_NEG
2565 MOVS reg_a,reg_a,LSR #1
2568 MOV reg_a,reg_a, LSL #24
2572 S9xGetWordLowRegNS rscratch2
2573 TST rstatus, #MASK_CARRY
2574 ORRNE rscratch2, rscratch2, #0x00010000
2575 ORRNE rstatus,rstatus,#MASK_NEG
2576 BICEQ rstatus,rstatus,#MASK_NEG
2577 MOVS rscratch2,rscratch2,LSR #1
2580 S9xSetWordLow rscratch2
2585 S9xGetByteLowRegNS rscratch2
2586 TST rstatus, #MASK_CARRY
2587 ORRNE rscratch2, rscratch2, #0x00000100
2588 ORRNE rstatus,rstatus,#MASK_NEG
2589 BICEQ rstatus,rstatus,#MASK_NEG
2590 MOVS rscratch2,rscratch2,LSR #1
2593 S9xSetByteLow rscratch2
2598 TST rstatus, #MASK_DECIMAL
2603 STMFD R13!,{rscratch9}
2604 MOV rscratch9,#0x000F0000
2605 @ rscratch2 - result
2606 @ rscratch3 - scratch
2607 @ rscratch4 - scratch
2608 @ rscratch9 - pattern
2610 AND rscratch2, rscratch, #0x000F0000
2611 TST rstatus, #MASK_CARRY
2612 ADDEQ rscratch2, rscratch2, #0x00010000 @ W1=W1+!Carry
2613 AND rscratch4, reg_a, #0x000F0000
2614 SUB rscratch2, rscratch4,rscratch2 @ R1=A1-W1-!Carry
2615 CMP rscratch2, #0x00090000 @ if R1 > 9
2616 ADDHI rscratch2, rscratch2, #0x000A0000 @ then R1 += 10
2617 AND rscratch2, rscratch2, #0x000F0000
2619 AND rscratch3, rscratch9, rscratch, LSR #4
2620 ADDHI rscratch3, rscratch3, #0x00010000 @ then (W2++)
2622 AND rscratch4, rscratch9, reg_a, LSR #4
2623 SUB rscratch3, rscratch4, rscratch3 @ R2=A2-W2
2624 CMP rscratch3, #0x00090000 @ if R2 > 9
2625 ADDHI rscratch3, rscratch3, #0x000A0000 @ then R2 += 10
2626 AND rscratch3, rscratch3, #0x000F0000
2627 ORR rscratch2, rscratch2, rscratch3,LSL #4
2629 AND rscratch3, rscratch9, rscratch, LSR #8
2630 ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++)
2632 AND rscratch4, rscratch9, reg_a, LSR #8
2633 SUB rscratch3, rscratch4, rscratch3 @ R3=A3-W3
2634 CMP rscratch3, #0x00090000 @ if R3 > 9
2635 ADDHI rscratch3, rscratch3, #0x000A0000 @ then R3 += 10
2636 AND rscratch3, rscratch3, #0x000F0000
2637 ORR rscratch2, rscratch2, rscratch3,LSL #8
2639 AND rscratch3, rscratch9, rscratch, LSR #12
2640 ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++)
2642 AND rscratch4, rscratch9, reg_a, LSR #12
2643 SUB rscratch3, rscratch4, rscratch3 @ R4=A4-W4
2644 CMP rscratch3, #0x00090000 @ if R4 > 9
2645 ADDHI rscratch3, rscratch3, #0x000A0000 @ then R4 += 10
2646 BICHI rstatus, rstatus, #MASK_CARRY @ then ClearCarry
2647 ORRLS rstatus, rstatus, #MASK_CARRY @ else SetCarry
2649 AND rscratch3,rscratch3,#0x000F0000
2650 ORR rscratch2,rscratch2,rscratch3,LSL #12
2652 LDMFD R13!,{rscratch9}
2654 AND reg_a,reg_a,#0x80000000
2655 @ (register.A.W ^ Work8)
2656 EORS rscratch3, reg_a, rscratch
2657 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2659 @ (register.A.W ^ Ans8)
2660 EORS rscratch3, reg_a, rscratch2
2662 TSTNE rscratch3,#0x80000000
2663 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2664 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2666 MOVS reg_a, rscratch2
2671 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2672 SBCS reg_a, reg_a, rscratch, LSL #16
2674 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2675 BICVC rstatus, rstatus, #MASK_OVERFLOW
2676 MOV reg_a, reg_a, LSR #16
2679 MOVS reg_a, reg_a, LSL #16
2686 TST rstatus, #MASK_DECIMAL
2689 STMFD R13!,{rscratch}
2690 MOV rscratch4,#0x0F000000
2691 @ rscratch2=xxW1xxxxxxxxxxxx
2692 AND rscratch2, rscratch, rscratch4
2693 @ rscratch=xxW2xxxxxxxxxxxx
2694 AND rscratch, rscratch4, rscratch, LSR #4
2695 @ rscratch3=xxA2xxxxxxxxxxxx
2696 AND rscratch3, rscratch4, reg_a, LSR #4
2697 @ rscratch4=xxA1xxxxxxxxxxxx
2698 AND rscratch4,reg_a,rscratch4
2700 TST rstatus, #MASK_CARRY
2701 ADDEQ rscratch2, rscratch2, #0x01000000
2702 SUB rscratch2,rscratch4,rscratch2
2704 CMP rscratch2, #0x09000000
2706 ADDHI rscratch2, rscratch2, #0x0A000000
2708 ADDHI rscratch, rscratch, #0x01000000
2710 SUB rscratch3, rscratch3, rscratch
2712 CMP rscratch3, #0x09000000
2714 ADDHI rscratch3, rscratch3, #0x0A000000
2716 BICHI rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2718 ORRLS rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero
2719 @ gather rscratch3 and rscratch2 into ans8
2720 AND rscratch3,rscratch3,#0x0F000000
2721 AND rscratch2,rscratch2,#0x0F000000
2722 @ rscratch3 : 0R2000000
2723 @ rscratch2 : 0R1000000
2725 ORR rscratch2, rscratch2, rscratch3, LSL #4
2726 LDMFD R13!,{rscratch}
2728 AND reg_a,reg_a,#0x80000000
2729 @ (register.AL ^ Work8)
2730 EORS rscratch3, reg_a, rscratch
2731 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2733 @ (register.AL ^ Ans8)
2734 EORS rscratch3, reg_a, rscratch2
2736 TSTNE rscratch3,#0x80000000
2737 BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero
2738 ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one
2740 MOVS reg_a, rscratch2
2745 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2746 SBCS reg_a, reg_a, rscratch, LSL #24
2748 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2749 BICVC rstatus, rstatus, #MASK_OVERFLOW
2753 ANDS reg_a, reg_a, #0xFF000000
2783 S9xGetWordRegNS rscratch2
2784 TST reg_a, rscratch2
2785 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2786 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2787 ORR rscratch2, reg_a, rscratch2
2788 S9xSetWord rscratch2
2792 S9xGetByteRegNS rscratch2
2793 TST reg_a, rscratch2
2794 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2795 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2796 ORR rscratch2, reg_a, rscratch2
2797 S9xSetByte rscratch2
2801 S9xGetWordRegNS rscratch2
2802 TST reg_a, rscratch2
2803 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2804 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2805 MVN rscratch3, reg_a
2806 AND rscratch2, rscratch3, rscratch2
2807 S9xSetWord rscratch2
2811 S9xGetByteRegNS rscratch2
2812 TST reg_a, rscratch2
2813 BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero
2814 ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one
2815 MVN rscratch3, reg_a
2816 AND rscratch2, rscratch3, rscratch2
2817 S9xSetByte rscratch2
2820 /**************************************************************************/
2823 /**************************************************************************/
2825 .macro Op09M0 /*ORA*/
2826 LDRB rscratch2, [rpc,#1]
2827 LDRB rscratch, [rpc], #2
2828 ORR rscratch2,rscratch,rscratch2,LSL #8
2829 ORRS reg_a,reg_a,rscratch2,LSL #16
2833 .macro Op09M1 /*ORA*/
2834 LDRB rscratch, [rpc], #1
2835 ORRS reg_a,reg_a,rscratch,LSL #24
2839 /***********************************************************************/
2843 TST rstatus, #MASK_CARRY
2845 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2853 TST rstatus, #MASK_CARRY
2855 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2863 TST rstatus, #MASK_ZERO
2865 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2873 TST rstatus, #MASK_ZERO
2875 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2883 TST rstatus, #MASK_NEG
2885 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
2893 TST rstatus, #MASK_NEG @ neg, z!=0, NE
2895 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2903 TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE
2905 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2913 TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE
2915 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2922 ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase
2927 /*******************************************************************************************/
2928 /************************************************************/
2929 /* SetFlag Instructions ********************************************************************** */
2931 ORR rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one
2944 /****************************************************************************************/
2945 /* ClearFlag Instructions ******************************************************************** */
2947 BIC rstatus, rstatus, #MASK_CARRY
2960 BIC rstatus, rstatus, #MASK_OVERFLOW
2964 /******************************************************************************************/
2965 /* DEX/DEY *********************************************************************************** */
2967 .macro OpCAX1 /*DEX*/
2969 SUBS reg_x, reg_x, #0x01000000
2970 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2974 .macro OpCAX0 /*DEX*/
2976 SUBS reg_x, reg_x, #0x00010000
2977 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2981 .macro Op88X1 /*DEY*/
2983 SUBS reg_y, reg_y, #0x01000000
2984 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2988 .macro Op88X0 /*DEY*/
2990 SUBS reg_y, reg_y, #0x00010000
2991 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2996 /******************************************************************************************/
2997 /* INX/INY *********************************************************************************** */
3000 ADDS reg_x, reg_x, #0x01000000
3001 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3007 ADDS reg_x, reg_x, #0x00010000
3008 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3014 ADDS reg_y, reg_y, #0x01000000
3015 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3021 ADDS reg_y, reg_y, #0x00010000
3022 STR rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3027 /**********************************************************************************************/
3029 /* NOP *************************************************************************************** */
3034 /**************************************************************************/
3035 /* PUSH Instructions **************************************************** */
3057 AND rscratch2, reg_d_bank, #0xFF
3089 /**************************************************************************/
3090 /* PULL Instructions **************************************************** */
3102 BIC reg_d_bank,reg_d_bank, #0xFF
3104 ORR reg_d_bank,reg_d_bank,rscratch, LSR #24
3109 BIC reg_d,reg_d, #0xFF000000
3110 BIC reg_d,reg_d, #0x00FF0000
3112 ORR reg_d,rscratch,reg_d
3116 .macro Op28X1M1 /*PLP*/
3117 @ INDEX set, MEMORY set
3118 BIC rstatus,rstatus,#0xFF000000
3120 ORR rstatus,rscratch,rstatus
3121 TST rstatus, #MASK_INDEX
3122 @ INDEX clear & was set : 8->16
3123 MOVEQ reg_x,reg_x,LSR #8
3124 MOVEQ reg_y,reg_y,LSR #8
3125 TST rstatus, #MASK_MEM
3126 @ MEMORY cleared & was set : 8->16
3127 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
3128 MOVEQ reg_a,reg_a,LSR #8
3129 ORREQ reg_a,reg_a,rscratch, LSL #24
3133 .macro Op28X0M1 /*PLP*/
3134 @ INDEX cleared, MEMORY set
3135 BIC rstatus,rstatus,#0xFF000000
3137 ORR rstatus,rscratch,rstatus
3138 TST rstatus, #MASK_INDEX
3139 @ INDEX set & was cleared : 16->8
3140 MOVNE reg_x,reg_x,LSL #8
3141 MOVNE reg_y,reg_y,LSL #8
3142 TST rstatus, #MASK_MEM
3143 @ MEMORY cleared & was set : 8->16
3144 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
3145 MOVEQ reg_a,reg_a,LSR #8
3146 ORREQ reg_a,reg_a,rscratch, LSL #24
3150 .macro Op28X1M0 /*PLP*/
3151 @ INDEX set, MEMORY set
3152 BIC rstatus,rstatus,#0xFF000000
3154 ORR rstatus,rscratch,rstatus
3155 TST rstatus, #MASK_INDEX
3156 @ INDEX clear & was set : 8->16
3157 MOVEQ reg_x,reg_x,LSR #8
3158 MOVEQ reg_y,reg_y,LSR #8
3159 TST rstatus, #MASK_MEM
3160 @ MEMORY set & was cleared : 16->8
3161 MOVNE rscratch,reg_a,LSR #24
3162 MOVNE reg_a,reg_a,LSL #8
3163 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
3167 .macro Op28X0M0 /*PLP*/
3168 @ INDEX set, MEMORY set
3169 BIC rstatus,rstatus,#0xFF000000
3171 ORR rstatus,rscratch,rstatus
3172 TST rstatus, #MASK_INDEX
3173 @ INDEX set & was cleared : 16->8
3174 MOVNE reg_x,reg_x,LSL #8
3175 MOVNE reg_y,reg_y,LSL #8
3176 TST rstatus, #MASK_MEM
3177 @ MEMORY set & was cleared : 16->8
3178 MOVNE rscratch,reg_a,LSR #24
3179 MOVNE reg_a,reg_a,LSL #8
3180 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
3205 /**********************************************************************************************/
3206 /* Transfer Instructions ********************************************************************* */
3207 .macro OpAAX1M1 /*TAX8*/
3212 .macro OpAAX0M1 /*TAX16*/
3213 LDRB reg_x, [reg_cpu_var,#RAH_ofs]
3214 MOV reg_x, reg_x,LSL #24
3215 ORRS reg_x, reg_x,reg_a, LSR #8
3219 .macro OpAAX1M0 /*TAX8*/
3220 MOVS reg_x, reg_a, LSL #8
3224 .macro OpAAX0M0 /*TAX16*/
3229 .macro OpA8X1M1 /*TAY8*/
3234 .macro OpA8X0M1 /*TAY16*/
3235 LDRB reg_y, [reg_cpu_var,#RAH_ofs]
3236 MOV reg_y, reg_y,LSL #24
3237 ORRS reg_y, reg_y,reg_a, LSR #8
3241 .macro OpA8X1M0 /*TAY8*/
3242 MOVS reg_y, reg_a, LSL #8
3246 .macro OpA8X0M0 /*TAY16*/
3252 LDRB rscratch, [reg_cpu_var,#RAH_ofs]
3253 MOV reg_d,reg_d,LSL #16
3254 MOV rscratch,rscratch,LSL #24
3255 ORRS rscratch,rscratch,reg_a, LSR #8
3257 ORR reg_d,rscratch,reg_d,LSR #16
3261 MOV reg_d,reg_d,LSL #16
3264 ORR reg_d,reg_a,reg_d,LSR #16
3268 TST rstatus, #MASK_EMUL
3269 MOVNE reg_s, reg_a, LSR #24
3270 ORRNE reg_s, reg_s, #0x100
3271 LDREQB reg_s, [reg_cpu_var,#RAH_ofs]
3272 ORREQ reg_s, reg_s, reg_a
3273 MOVEQ reg_s, reg_s, ROR #24
3277 MOV reg_s, reg_a, LSR #16
3281 MOVS reg_a, reg_d, ASR #16
3283 MOV rscratch,reg_a,LSR #8
3284 MOV reg_a,reg_a, LSL #24
3285 STRB rscratch, [reg_cpu_var,#RAH_ofs]
3289 MOVS reg_a, reg_d, ASR #16
3291 MOV reg_a,reg_a, LSL #16
3295 MOV rscratch,reg_s, LSR #8
3296 MOVS reg_a, reg_s, LSL #16
3297 STRB rscratch, [reg_cpu_var,#RAH_ofs]
3299 MOV reg_a,reg_a, LSL #8
3303 MOVS reg_a, reg_s, LSL #16
3308 MOVS reg_x, reg_s, LSL #24
3313 MOVS reg_x, reg_s, LSL #16
3323 MOVS reg_a, reg_x, LSL #8
3328 MOVS reg_a, reg_x, LSR #8
3338 MOV reg_s, reg_x, LSR #24
3339 TST rstatus, #MASK_EMUL
3340 ORRNE reg_s, reg_s, #0x100
3344 MOV reg_s, reg_x, LSR #16
3363 MOVS reg_a, reg_y, LSL #8
3368 MOVS reg_a, reg_y, LSR #8
3388 /**********************************************************************************************/
3389 /* XCE *************************************************************************************** */
3392 TST rstatus,#MASK_CARRY
3395 TST rstatus,#MASK_EMUL
3398 BIC rstatus,rstatus,#(MASK_CARRY)
3399 TST rstatus,#MASK_INDEX
3400 @ X & Y were 16bits before
3401 MOVEQ reg_x,reg_x,LSL #8
3402 MOVEQ reg_y,reg_y,LSL #8
3403 TST rstatus,#MASK_MEM
3404 @ A was 16bits before
3406 MOVEQ rscratch,reg_a,LSR #24
3407 STREQB rscratch,[reg_cpu_var,#RAH_ofs]
3408 MOVEQ reg_a,reg_a,LSL #8
3409 ORR rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
3410 AND reg_s,reg_s,#0xFF
3411 ORR reg_s,reg_s,#0x100
3415 TST rstatus,#MASK_INDEX
3416 @ X & Y were 16bits before
3417 MOVEQ reg_x,reg_x,LSL #8
3418 MOVEQ reg_y,reg_y,LSL #8
3419 TST rstatus,#MASK_MEM
3420 @ A was 16bits before
3422 MOVEQ rscratch,reg_a,LSR #24
3423 STREQB rscratch,[reg_cpu_var,#RAH_ofs]
3424 MOVEQ reg_a,reg_a,LSL #8
3425 ORR rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
3426 AND reg_s,reg_s,#0xFF
3427 ORR reg_s,reg_s,#0x100
3431 TST rstatus,#MASK_EMUL
3433 @ EMUL was set : X,Y & A were 8bits
3434 @ Now have to check MEMORY & INDEX for potential conversions to 16bits
3435 TST rstatus,#MASK_INDEX
3436 @ X & Y are now 16bits
3437 MOVEQ reg_x,reg_x,LSR #8
3438 MOVEQ reg_y,reg_y,LSR #8
3439 TST rstatus,#MASK_MEM
3441 MOVEQ reg_a,reg_a,LSR #8
3443 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
3444 ORREQ reg_a,reg_a,rscratch,LSL #24
3446 BIC rstatus,rstatus,#(MASK_EMUL)
3447 ORR rstatus,rstatus,#(MASK_CARRY)
3453 /*******************************************************************************/
3454 /* BRK *************************************************************************/
3457 STRB rscratch,[reg_cpu_var,#BRKTriggered_ofs]
3459 TST rstatus, #MASK_EMUL
3460 @ EQ is flag to zero (!CheckEmu)
3463 SUB rscratch, rpc, regpcbase
3464 ADD rscratch2, rscratch, #1
3470 BIC reg_p_bank, reg_p_bank, #0xFF
3472 ORR rscratch, rscratch, #0xFF00
3478 SUB rscratch2, rpc, regpcbase
3484 BIC reg_p_bank,reg_p_bank, #0xFF
3486 ORR rscratch, rscratch, #0xFF00
3494 /**********************************************************************************************/
3495 /* BRL ************************************************************************************** */
3498 ORR rscratch, rscratch, reg_p_bank, LSL #16
3501 /**********************************************************************************************/
3502 /* IRQ *************************************************************************************** */
3503 @ void S9xOpcode_IRQ (void)
3504 .macro S9xOpcode_IRQ @ IRQ
3505 TST rstatus, #MASK_EMUL
3506 @ EQ is flag to zero (!CheckEmu)
3509 SUB rscratch2, rpc, regpcbase
3515 BIC reg_p_bank, reg_p_bank,#0xFF
3517 ORR rscratch, rscratch, #0xFF00
3523 SUB rscratch2, rpc, regpcbase
3529 BIC reg_p_bank,reg_p_bank, #0xFF
3531 ORR rscratch, rscratch, #0xFF00
3539 void asm_S9xOpcode_IRQ(void)
3541 if (!CheckEmulation())
3543 PushB (Registers.PB);
3544 PushW (CPU.PC - CPU.PCBase);
3545 PushB (Registers.PL);
3550 S9xSetPCBase (S9xGetWord (0xFFEE));
3551 CPU.Cycles += TWO_CYCLES;
3555 PushW (CPU.PC - CPU.PCBase);
3556 PushB (Registers.PL);
3561 S9xSetPCBase (S9xGetWord (0xFFFE));
3562 CPU.Cycles += ONE_CYCLE;
3567 /**********************************************************************************************/
3568 /* NMI *************************************************************************************** */
3569 @ void S9xOpcode_NMI (void)
3570 .macro S9xOpcode_NMI @ NMI
3571 TST rstatus, #MASK_EMUL
3572 @ EQ is flag to zero (!CheckEmu)
3575 SUB rscratch2, rpc, regpcbase
3581 BIC reg_p_bank, reg_p_bank,#0xFF
3583 ORR rscratch, rscratch, #0xFF00
3589 SUB rscratch2, rpc, regpcbase
3595 BIC reg_p_bank,reg_p_bank, #0xFF
3597 ORR rscratch, rscratch, #0xFF00
3604 void asm_S9xOpcode_NMI(void)
3606 if (!CheckEmulation())
3608 PushB (Registers.PB);
3609 PushW (CPU.PC - CPU.PCBase);
3610 PushB (Registers.PL);
3615 S9xSetPCBase (S9xGetWord (0xFFEA));
3616 CPU.Cycles += TWO_CYCLES;
3620 PushW (CPU.PC - CPU.PCBase);
3621 PushB (Registers.PL);
3626 S9xSetPCBase (S9xGetWord (0xFFFA));
3627 CPU.Cycles += ONE_CYCLE;
3632 /**********************************************************************************************/
3633 /* COP *************************************************************************************** */
3635 TST rstatus, #MASK_EMUL
3636 @ EQ is flag to zero (!CheckEmu)
3639 SUB rscratch, rpc, regpcbase
3640 ADD rscratch2, rscratch, #1
3646 BIC reg_p_bank, reg_p_bank,#0xFF
3648 ORR rscratch, rscratch, #0xFF00
3654 SUB rscratch2, rpc, regpcbase
3660 BIC reg_p_bank,reg_p_bank, #0xFF
3662 ORR rscratch, rscratch, #0xFF00
3669 /**********************************************************************************************/
3670 /* JML *************************************************************************************** */
3672 AbsoluteIndirectLong
3673 BIC reg_p_bank,reg_p_bank,#0xFF
3674 ORR reg_p_bank,reg_p_bank, rscratch, LSR #16
3680 BIC reg_p_bank,reg_p_bank,#0xFF
3681 ORR reg_p_bank,reg_p_bank, rscratch, LSR #16
3685 /**********************************************************************************************/
3686 /* JMP *************************************************************************************** */
3689 BIC rscratch, rscratch, #0xFF0000
3690 ORR rscratch, rscratch, reg_p_bank, LSL #16
3696 BIC rscratch, rscratch, #0xFF0000
3697 ORR rscratch, rscratch, reg_p_bank, LSL #16
3701 ADD rscratch, rscratch, reg_p_bank, LSL #16
3706 /**********************************************************************************************/
3707 /* JSL/RTL *********************************************************************************** */
3710 SUB rscratch, rpc, regpcbase
3711 @ SUB rscratch2, rscratch2, #1
3712 ADD rscratch2, rscratch, #2
3715 BIC reg_p_bank,reg_p_bank,#0xFF
3716 ORR reg_p_bank, reg_p_bank, rscratch, LSR #16
3721 BIC reg_p_bank,reg_p_bank,#0xFF
3723 ORR reg_p_bank, reg_p_bank, rscratch
3724 ADD rscratch, rpc, #1
3725 BIC rscratch, rscratch,#0xFF0000
3726 ORR rscratch, rscratch, reg_p_bank, LSL #16
3730 /**********************************************************************************************/
3731 /* JSR/RTS *********************************************************************************** */
3733 SUB rscratch, rpc, regpcbase
3734 @ SUB rscratch2, rscratch2, #1
3735 ADD rscratch2, rscratch, #1
3738 BIC rscratch, rscratch, #0xFF0000
3739 ORR rscratch, rscratch, reg_p_bank, LSL #16
3744 SUB rscratch, rpc, regpcbase
3745 @ SUB rscratch2, rscratch2, #1
3746 ADD rscratch2, rscratch, #1
3748 AbsoluteIndexedIndirectX0
3749 ORR rscratch, rscratch, reg_p_bank, LSL #16
3754 SUB rscratch, rpc, regpcbase
3755 @ SUB rscratch2, rscratch2, #1
3756 ADD rscratch2, rscratch, #1
3758 AbsoluteIndexedIndirectX1
3759 ORR rscratch, rscratch, reg_p_bank, LSL #16
3765 ADD rscratch, rpc, #1
3766 BIC rscratch, rscratch,#0x10000
3767 ORR rscratch, rscratch, reg_p_bank, LSL #16
3772 /**********************************************************************************************/
3773 /* MVN/MVP *********************************************************************************** */
3775 @ Save RegStatus = reg_d_bank >> 24
3776 MOV rscratch, reg_d_bank, LSR #16
3777 LDRB reg_d_bank , [rpc], #1
3778 LDRB rscratch2 , [rpc], #1
3779 @ Restore RegStatus = reg_d_bank >> 24
3780 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3781 MOV rscratch , reg_x, LSR #24
3782 ORR rscratch , rscratch, rscratch2, LSL #16
3784 MOV rscratch2, rscratch
3785 MOV rscratch , reg_y, LSR #24
3786 ORR rscratch , rscratch, reg_d_bank, LSL #16
3787 S9xSetByteLow rscratch2
3789 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3790 MOV reg_a,reg_a,LSR #8
3791 ORR reg_a,reg_a,rscratch, LSL #24
3792 ADD reg_x, reg_x, #0x01000000
3793 SUB reg_a, reg_a, #0x00010000
3794 ADD reg_y, reg_y, #0x01000000
3795 CMP reg_a, #0xFFFF0000
3798 MOV rscratch, reg_a, LSR #24
3799 MOV reg_a,reg_a,LSL #8
3800 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3804 @ Save RegStatus = reg_d_bank >> 24
3805 MOV rscratch, reg_d_bank, LSR #16
3806 LDRB reg_d_bank , [rpc], #1
3807 LDRB rscratch2 , [rpc], #1
3808 @ Restore RegStatus = reg_d_bank >> 24
3809 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3810 MOV rscratch , reg_x, LSR #24
3811 ORR rscratch , rscratch, rscratch2, LSL #16
3813 MOV rscratch2, rscratch
3814 MOV rscratch , reg_y, LSR #24
3815 ORR rscratch , rscratch, reg_d_bank, LSL #16
3816 S9xSetByteLow rscratch2
3817 ADD reg_x, reg_x, #0x01000000
3818 SUB reg_a, reg_a, #0x00010000
3819 ADD reg_y, reg_y, #0x01000000
3820 CMP reg_a, #0xFFFF0000
3825 @ Save RegStatus = reg_d_bank >> 24
3826 MOV rscratch, reg_d_bank, LSR #16
3827 LDRB reg_d_bank , [rpc], #1
3828 LDRB rscratch2 , [rpc], #1
3829 @ Restore RegStatus = reg_d_bank >> 24
3830 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3831 MOV rscratch , reg_x, LSR #16
3832 ORR rscratch , rscratch, rscratch2, LSL #16
3834 MOV rscratch2, rscratch
3835 MOV rscratch , reg_y, LSR #16
3836 ORR rscratch , rscratch, reg_d_bank, LSL #16
3837 S9xSetByteLow rscratch2
3839 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3840 MOV reg_a,reg_a,LSR #8
3841 ORR reg_a,reg_a,rscratch, LSL #24
3842 ADD reg_x, reg_x, #0x00010000
3843 SUB reg_a, reg_a, #0x00010000
3844 ADD reg_y, reg_y, #0x00010000
3845 CMP reg_a, #0xFFFF0000
3848 MOV rscratch, reg_a, LSR #24
3849 MOV reg_a,reg_a,LSL #8
3850 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3854 @ Save RegStatus = reg_d_bank >> 24
3855 MOV rscratch, reg_d_bank, LSR #16
3856 LDRB reg_d_bank , [rpc], #1
3857 LDRB rscratch2 , [rpc], #1
3858 @ Restore RegStatus = reg_d_bank >> 24
3859 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3860 MOV rscratch , reg_x, LSR #16
3861 ORR rscratch , rscratch, rscratch2, LSL #16
3863 MOV rscratch2, rscratch
3864 MOV rscratch , reg_y, LSR #16
3865 ORR rscratch , rscratch, reg_d_bank, LSL #16
3866 S9xSetByteLow rscratch2
3867 ADD reg_x, reg_x, #0x00010000
3868 SUB reg_a, reg_a, #0x00010000
3869 ADD reg_y, reg_y, #0x00010000
3870 CMP reg_a, #0xFFFF0000
3876 @ Save RegStatus = reg_d_bank >> 24
3877 MOV rscratch, reg_d_bank, LSR #16
3878 LDRB reg_d_bank , [rpc], #1
3879 LDRB rscratch2 , [rpc], #1
3880 @ Restore RegStatus = reg_d_bank >> 24
3881 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3882 MOV rscratch , reg_x, LSR #24
3883 ORR rscratch , rscratch, rscratch2, LSL #16
3885 MOV rscratch2, rscratch
3886 MOV rscratch , reg_y, LSR #24
3887 ORR rscratch , rscratch, reg_d_bank, LSL #16
3888 S9xSetByteLow rscratch2
3890 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3891 MOV reg_a,reg_a,LSR #8
3892 ORR reg_a,reg_a,rscratch, LSL #24
3893 SUB reg_x, reg_x, #0x01000000
3894 SUB reg_a, reg_a, #0x00010000
3895 SUB reg_y, reg_y, #0x01000000
3896 CMP reg_a, #0xFFFF0000
3899 MOV rscratch, reg_a, LSR #24
3900 MOV reg_a,reg_a,LSL #8
3901 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3905 @ Save RegStatus = reg_d_bank >> 24
3906 MOV rscratch, reg_d_bank, LSR #16
3907 LDRB reg_d_bank , [rpc], #1
3908 LDRB rscratch2 , [rpc], #1
3909 @ Restore RegStatus = reg_d_bank >> 24
3910 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3911 MOV rscratch , reg_x, LSR #24
3912 ORR rscratch , rscratch, rscratch2, LSL #16
3914 MOV rscratch2, rscratch
3915 MOV rscratch , reg_y, LSR #24
3916 ORR rscratch , rscratch, reg_d_bank, LSL #16
3917 S9xSetByteLow rscratch2
3918 SUB reg_x, reg_x, #0x01000000
3919 SUB reg_a, reg_a, #0x00010000
3920 SUB reg_y, reg_y, #0x01000000
3921 CMP reg_a, #0xFFFF0000
3926 @ Save RegStatus = reg_d_bank >> 24
3927 MOV rscratch, reg_d_bank, LSR #16
3928 LDRB reg_d_bank , [rpc], #1
3929 LDRB rscratch2 , [rpc], #1
3930 @ Restore RegStatus = reg_d_bank >> 24
3931 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3932 MOV rscratch , reg_x, LSR #16
3933 ORR rscratch , rscratch, rscratch2, LSL #16
3935 MOV rscratch2, rscratch
3936 MOV rscratch , reg_y, LSR #16
3937 ORR rscratch , rscratch, reg_d_bank, LSL #16
3938 S9xSetByteLow rscratch2
3940 LDRB rscratch,[reg_cpu_var,#RAH_ofs]
3941 MOV reg_a,reg_a,LSR #8
3942 ORR reg_a,reg_a,rscratch, LSL #24
3943 SUB reg_x, reg_x, #0x00010000
3944 SUB reg_a, reg_a, #0x00010000
3945 SUB reg_y, reg_y, #0x00010000
3946 CMP reg_a, #0xFFFF0000
3949 MOV rscratch, reg_a, LSR #24
3950 MOV reg_a,reg_a,LSL #8
3951 STRB rscratch,[reg_cpu_var,#RAH_ofs]
3955 @ Save RegStatus = reg_d_bank >> 24
3956 MOV rscratch, reg_d_bank, LSR #16
3957 LDRB reg_d_bank , [rpc], #1
3958 LDRB rscratch2 , [rpc], #1
3959 @ Restore RegStatus = reg_d_bank >> 24
3960 ORR reg_d_bank, reg_d_bank, rscratch, LSL #16
3961 MOV rscratch , reg_x, LSR #16
3962 ORR rscratch , rscratch, rscratch2, LSL #16
3964 MOV rscratch2, rscratch
3965 MOV rscratch , reg_y, LSR #16
3966 ORR rscratch , rscratch, reg_d_bank, LSL #16
3967 S9xSetByteLow rscratch2
3968 SUB reg_x, reg_x, #0x00010000
3969 SUB reg_a, reg_a, #0x00010000
3970 SUB reg_y, reg_y, #0x00010000
3971 CMP reg_a, #0xFFFF0000
3976 /**********************************************************************************************/
3977 /* REP/SEP *********************************************************************************** */
3979 @ status&=~(*rpc++);
3980 @ so possible changes are :
3981 @ INDEX = 1 -> 0 : X,Y 8bits -> 16bits
3982 @ MEM = 1 -> 0 : A 8bits -> 16bits
3983 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
3984 MOV rscratch3, rstatus
3985 LDRB rscratch, [rpc], #1
3986 MVN rscratch, rscratch
3987 AND rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
3988 TST rstatus,#MASK_EMUL
3990 @ emulation mode on : no changes since it was on before opcode
3991 @ just be sure to reset MEM & INDEX accordingly
3992 ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
3995 @ NOT in Emulation mode, check INDEX & MEMORY bits
3997 TST rscratch3,#MASK_INDEX
3999 @ X & Y were 8bit before
4000 TST rstatus,#MASK_INDEX
4002 @ X & Y are now 16bits
4003 MOV reg_x,reg_x,LSR #8
4004 MOV reg_y,reg_y,LSR #8
4005 1113: @ X & Y still in 16bits
4007 TST rscratch3,#MASK_MEM
4010 TST rstatus,#MASK_MEM
4013 MOV reg_a,reg_a,LSR #8
4015 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
4016 ORREQ reg_a,reg_a,rscratch,LSL #24
4023 @ so possible changes are :
4024 @ INDEX = 0 -> 1 : X,Y 16bits -> 8bits
4025 @ MEM = 0 -> 1 : A 16bits -> 8bits
4026 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
4027 MOV rscratch3, rstatus
4028 LDRB rscratch, [rpc], #1
4029 ORR rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
4030 TST rstatus,#MASK_EMUL
4032 @ emulation mode on : no changes sinc eit was on before opcode
4033 @ just be sure to have mem & index set accordingly
4034 ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
4037 @ NOT in Emulation mode, check INDEX & MEMORY bits
4039 TST rscratch3,#MASK_INDEX
4041 @ X & Y were 16bit before
4042 TST rstatus,#MASK_INDEX
4044 @ X & Y are now 8bits
4045 MOV reg_x,reg_x,LSL #8
4046 MOV reg_y,reg_y,LSL #8
4047 10113: @ X & Y still in 16bits
4049 TST rscratch3,#MASK_MEM
4051 @ A was 16bit before
4052 TST rstatus,#MASK_MEM
4056 MOV rscratch,reg_a,LSR #24
4057 MOV reg_a,reg_a,LSL #8
4058 STRB rscratch,[reg_cpu_var,#RAH_ofs]
4064 /**********************************************************************************************/
4065 /* XBA *************************************************************************************** */
4068 ADD rscratch,reg_cpu_var,#RAH_ofs
4069 MOV reg_a,reg_a, LSR #24
4070 SWPB reg_a,reg_a,[rscratch]
4071 MOVS reg_a,reg_a, LSL #24
4077 MOV rscratch, reg_a, ROR #24 @ ll0000hh
4078 ORR rscratch, rscratch, reg_a, LSR #8@ ll0000hh + 00hhll00 -> llhhllhh
4079 MOV reg_a, rscratch, LSL #16@ llhhllhh -> llhh0000
4080 MOVS rscratch,rscratch,LSL #24 @ to set Z & N flags with AL
4086 /**********************************************************************************************/
4087 /* RTI *************************************************************************************** */
4089 @ INDEX set, MEMORY set
4090 BIC rstatus,rstatus,#0xFF000000
4092 ORR rstatus,rscratch,rstatus
4094 TST rstatus, #MASK_EMUL
4095 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4098 BIC reg_p_bank,reg_p_bank,#0xFF
4099 ORR reg_p_bank,reg_p_bank,rscratch
4101 ADD rscratch, rpc, reg_p_bank, LSL #16
4103 TST rstatus, #MASK_INDEX
4104 @ INDEX cleared & was set : 8->16
4105 MOVEQ reg_x,reg_x,LSR #8
4106 MOVEQ reg_y,reg_y,LSR #8
4107 TST rstatus, #MASK_MEM
4108 @ MEMORY cleared & was set : 8->16
4109 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
4110 MOVEQ reg_a,reg_a,LSR #8
4111 ORREQ reg_a,reg_a,rscratch, LSL #24
4116 @ INDEX cleared, MEMORY set
4117 BIC rstatus,rstatus,#0xFF000000
4119 ORR rstatus,rscratch,rstatus
4121 TST rstatus, #MASK_EMUL
4122 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4125 BIC reg_p_bank,reg_p_bank,#0xFF
4126 ORR reg_p_bank,reg_p_bank,rscratch
4128 ADD rscratch, rpc, reg_p_bank, LSL #16
4130 TST rstatus, #MASK_INDEX
4131 @ INDEX set & was cleared : 16->8
4132 MOVNE reg_x,reg_x,LSL #8
4133 MOVNE reg_y,reg_y,LSL #8
4134 TST rstatus, #MASK_MEM
4135 @ MEMORY cleared & was set : 8->16
4136 LDREQB rscratch,[reg_cpu_var,#RAH_ofs]
4137 MOVEQ reg_a,reg_a,LSR #8
4138 ORREQ reg_a,reg_a,rscratch, LSL #24
4143 @ INDEX set, MEMORY cleared
4144 BIC rstatus,rstatus,#0xFF000000
4146 ORR rstatus,rscratch,rstatus
4148 TST rstatus, #MASK_EMUL
4149 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4152 BIC reg_p_bank,reg_p_bank,#0xFF
4153 ORR reg_p_bank,reg_p_bank,rscratch
4155 ADD rscratch, rpc, reg_p_bank, LSL #16
4157 TST rstatus, #MASK_INDEX
4158 @ INDEX cleared & was set : 8->16
4159 MOVEQ reg_x,reg_x,LSR #8
4160 MOVEQ reg_y,reg_y,LSR #8
4161 TST rstatus, #MASK_MEM
4162 @ MEMORY set & was cleared : 16->8
4163 MOVNE rscratch,reg_a,LSR #24
4164 MOVNE reg_a,reg_a,LSL #8
4165 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
4170 @ INDEX cleared, MEMORY cleared
4171 BIC rstatus,rstatus,#0xFF000000
4173 ORR rstatus,rscratch,rstatus
4175 TST rstatus, #MASK_EMUL
4176 ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4179 BIC reg_p_bank,reg_p_bank,#0xFF
4180 ORR reg_p_bank,reg_p_bank,rscratch
4182 ADD rscratch, rpc, reg_p_bank, LSL #16
4184 TST rstatus, #MASK_INDEX
4185 @ INDEX set & was cleared : 16->8
4186 MOVNE reg_x,reg_x,LSL #8
4187 MOVNE reg_y,reg_y,LSL #8
4188 TST rstatus, #MASK_MEM
4189 @ MEMORY set & was cleared : 16->8
4190 @ MEMORY set & was cleared : 16->8
4191 MOVNE rscratch,reg_a,LSR #24
4192 MOVNE reg_a,reg_a,LSL #8
4193 STRNEB rscratch,[reg_cpu_var,#RAH_ofs]
4199 /**********************************************************************************************/
4200 /* STP/WAI/DB ******************************************************************************** */
4203 LDRB rscratch,[reg_cpu_var,#IRQActive_ofs]
4204 MOVS rscratch,rscratch
4209 CPU.WaitingForInterrupt = TRUE;
4215 CPU.Cycles = CPU.NextEvent;
4217 STRB rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs]
4218 LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs]
4220 if (IAPU.APUExecuting)
4222 ICPU.CPUExecuting = FALSE;
4226 } while (APU.Cycles < CPU.NextEvent);
4227 ICPU.CPUExecuting = TRUE;
4230 LDRB rscratch,[reg_cpu_var,#APUExecuting_ofs]
4231 MOVS rscratch,rscratch
4239 @ CPU.Flags |= DEBUG_MODE_FLAG;
4241 .macro Op42 /*Reserved Snes9X: SNESAdvance SpeedHack */
4242 @ Explanation: this is a reserved opcode turned into special "idle"/hlt opcode.
4243 @ This means we should do an hblank now.
4245 CPU.Cycles = CPU.NextEvent;
4246 */ ldr reg_cycles, [reg_cpu_var,#NextEvent_ofs]
4247 @ Now execute the shadowed branch
4248 @ Equivalent to "asmRelative":
4250 ldrb rscratch, [rpc], #1
4251 and rscratch2, rscratch, #0xf0 @branch type
4252 orr rscratch, rscratch, #0xf0 @branch dest (always negative, so sign ext)
4253 sxtb rscratch, rscratch
4254 add rscratch, rscratch, rpc
4255 sub rscratch, rscratch, regpcbase
4256 uxth rscratch, rscratch
4257 @ TODO: Do something with rscratch2 before BranchCheck clobbers it.
4258 @ Currently hardcoded to BEQ
4260 TST rstatus, #MASK_ZERO
4262 ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase
4267 /**********************************************************************************************/
4268 /* AND ******************************************************************************** */
4270 LDRB rscratch , [rpc], #1
4271 ANDS reg_a , reg_a, rscratch, LSL #24
4276 LDRB rscratch2 , [rpc,#1]
4277 LDRB rscratch , [rpc], #2
4278 ORR rscratch, rscratch, rscratch2, LSL #8
4279 ANDS reg_a , reg_a, rscratch, LSL #16
4298 /**********************************************************************************************/
4299 /* EOR ******************************************************************************** */
4301 LDRB rscratch2 , [rpc, #1]
4302 LDRB rscratch , [rpc], #2
4303 ORR rscratch, rscratch, rscratch2,LSL #8
4304 EORS reg_a, reg_a, rscratch,LSL #16
4311 LDRB rscratch , [rpc], #1
4312 EORS reg_a, reg_a, rscratch,LSL #24
4318 /**********************************************************************************************/
4319 /* STA *************************************************************************************** */
4322 @ TST rstatus, #MASK_INDEX
4327 @ TST rstatus, #MASK_INDEX
4332 /**********************************************************************************************/
4333 /* BIT *************************************************************************************** */
4335 LDRB rscratch , [rpc], #1
4336 TST reg_a, rscratch, LSL #24
4341 LDRB rscratch2 , [rpc, #1]
4342 LDRB rscratch , [rpc], #2
4343 ORR rscratch, rscratch, rscratch2, LSL #8
4344 TST reg_a, rscratch, LSL #16
4354 /**********************************************************************************************/
4355 /* LDY *************************************************************************************** */
4357 LDRB rscratch , [rpc], #1
4358 MOVS reg_y, rscratch, LSL #24
4363 LDRB rscratch2 , [rpc, #1]
4364 LDRB rscratch , [rpc], #2
4365 ORR rscratch, rscratch, rscratch2, LSL #8
4366 MOVS reg_y, rscratch, LSL #16
4371 /**********************************************************************************************/
4372 /* LDX *************************************************************************************** */
4374 LDRB rscratch , [rpc], #1
4375 MOVS reg_x, rscratch, LSL #24
4380 LDRB rscratch2 , [rpc, #1]
4381 LDRB rscratch , [rpc], #2
4382 ORR rscratch, rscratch, rscratch2, LSL #8
4383 MOVS reg_x, rscratch, LSL #16
4388 /**********************************************************************************************/
4389 /* LDA *************************************************************************************** */
4391 LDRB rscratch , [rpc], #1
4392 MOVS reg_a, rscratch, LSL #24
4397 LDRB rscratch2 , [rpc, #1]
4398 LDRB rscratch , [rpc], #2
4399 ORR rscratch, rscratch, rscratch2, LSL #8
4400 MOVS reg_a, rscratch, LSL #16
4405 /**********************************************************************************************/
4406 /* CMY *************************************************************************************** */
4408 LDRB rscratch , [rpc], #1
4409 SUBS rscratch2 , reg_y , rscratch, LSL #24
4410 BICCC rstatus, rstatus, #MASK_CARRY
4411 ORRCS rstatus, rstatus, #MASK_CARRY
4416 LDRB rscratch2 , [rpc, #1]
4417 LDRB rscratch , [rpc], #2
4418 ORR rscratch, rscratch, rscratch2, LSL #8
4419 SUBS rscratch2 , reg_y, rscratch, LSL #16
4420 BICCC rstatus, rstatus, #MASK_CARRY
4421 ORRCS rstatus, rstatus, #MASK_CARRY
4430 /**********************************************************************************************/
4431 /* CMP *************************************************************************************** */
4433 LDRB rscratch , [rpc], #1
4434 SUBS rscratch2 , reg_a , rscratch, LSL #24
4435 BICCC rstatus, rstatus, #MASK_CARRY
4436 ORRCS rstatus, rstatus, #MASK_CARRY
4441 LDRB rscratch2 , [rpc,#1]
4442 LDRB rscratch , [rpc], #2
4443 ORR rscratch, rscratch, rscratch2, LSL #8
4444 SUBS rscratch2 , reg_a, rscratch, LSL #16
4445 BICCC rstatus, rstatus, #MASK_CARRY
4446 ORRCS rstatus, rstatus, #MASK_CARRY
4451 /**********************************************************************************************/
4452 /* CMX *************************************************************************************** */
4454 LDRB rscratch , [rpc], #1
4455 SUBS rscratch2 , reg_x , rscratch, LSL #24
4456 BICCC rstatus, rstatus, #MASK_CARRY
4457 ORRCS rstatus, rstatus, #MASK_CARRY
4462 LDRB rscratch2 , [rpc,#1]
4463 LDRB rscratch , [rpc], #2
4464 ORR rscratch, rscratch, rscratch2, LSL #8
4465 SUBS rscratch2 , reg_x, rscratch, LSL #16
4466 BICCC rstatus, rstatus, #MASK_CARRY
4467 ORRCS rstatus, rstatus, #MASK_CARRY
4473 /****************************************************************
4475 ****************************************************************/
4477 .type asmMainLoop, function
4479 @ void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
4482 STMFD R13!,{R4-R11, LR}
4483 @ init pointer to CPUvar structure
4487 @ get cpu mode from flag and init jump table
4495 LDR rscratch,[reg_cpu_var,#Flags_ofs]
4496 MOVS rscratch,rscratch
4497 BNE CPUFlags_set @ If flags => check for irq/nmi/scan_keys...
4499 EXEC_OP @ Execute next opcode
4501 CPUFlags_set: @ Check flags (!=0)
4502 TST rscratch,#NMI_FLAG @ Check NMI
4503 BEQ CPUFlagsNMI_FLAG_cleared
4504 LDR rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4505 SUBS rscratch2,rscratch2,#1
4506 STR rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4507 BNE CPUFlagsNMI_FLAG_cleared
4508 BIC rscratch,rscratch,#NMI_FLAG
4509 STR rscratch,[reg_cpu_var,#Flags_ofs]
4510 LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4511 MOVS rscratch2,rscratch2
4512 BEQ NotCPUaitingForInterruptNMI
4515 STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4516 NotCPUaitingForInterruptNMI:
4518 LDR rscratch,[reg_cpu_var,#Flags_ofs]
4519 CPUFlagsNMI_FLAG_cleared:
4520 TST rscratch,#IRQ_PENDING_FLAG @ Check IRQ_PENDING_FLAG
4521 BEQ CPUFlagsIRQ_PENDING_FLAG_cleared
4522 LDR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4523 MOVS rscratch2,rscratch2
4524 BNE CPUIRQCycleCount_NotZero
4525 LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4526 MOVS rscratch2,rscratch2
4527 BEQ NotCPUaitingForInterruptIRQ
4530 STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4531 NotCPUaitingForInterruptIRQ:
4532 LDRB rscratch2,[reg_cpu_var,#IRQActive_ofs]
4533 MOVS rscratch2,rscratch2
4534 BEQ CPUIRQActive_cleared
4535 TST rstatus,#MASK_IRQ
4536 BNE CPUFlagsIRQ_PENDING_FLAG_cleared
4538 LDR rscratch,[reg_cpu_var,#Flags_ofs]
4539 B CPUFlagsIRQ_PENDING_FLAG_cleared
4540 CPUIRQActive_cleared:
4541 BIC rscratch,rscratch,#IRQ_PENDING_FLAG
4542 STR rscratch,[reg_cpu_var,#Flags_ofs]
4543 B CPUFlagsIRQ_PENDING_FLAG_cleared
4544 CPUIRQCycleCount_NotZero:
4545 SUB rscratch2,rscratch2,#1
4546 STR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4547 CPUFlagsIRQ_PENDING_FLAG_cleared:
4549 TST rscratch,#SCAN_KEYS_FLAG @ Check SCAN_KEYS_FLAG
4552 EXEC_OP @ Execute next opcode
4555 /*Registers.PC = CPU.PC - CPU.PCBase;
4557 APURegisters.PC = IAPU.PC - IAPU.RAM;
4558 S9xAPUPackStatus ();
4560 if (CPU.Flags & SCAN_KEYS_FLAG)
4563 CPU.Flags &= ~SCAN_KEYS_FLAG;
4567 LDMFD R13!,{R4-R11, LR}
4570 .size asmMainLoop, asmMainLoop-.
4572 @ void test_opcode(struct asm_cpu_var *asm_var);
4575 STMFD R13!,{R4-R11,LR}
4576 @ init pointer to CPUvar structure
4580 @ get cpu mode from flag and init jump table
4586 /*****************************************************************
4588 *****************************************************************/
4591 jumptable1: .long Op00mod1
4852 lbl01mod1a: DirectIndexedIndirect1
4859 lbl03mod1a: StackasmRelative
4875 lbl07mod1a: DirectIndirectLong
4891 lbl0Cmod1a: Absolute
4895 lbl0Dmod1a: Absolute
4899 lbl0Emod1a: Absolute
4903 lbl0Fmod1a: AbsoluteLong
4910 lbl11mod1a: DirectIndirectIndexed1
4914 lbl12mod1a: DirectIndirect
4918 lbl13mod1a: StackasmRelativeIndirectIndexed1
4926 lbl15mod1a: DirectIndexedX1
4930 lbl16mod1a: DirectIndexedX1
4934 lbl17mod1a: DirectIndirectIndexedLong1
4941 lbl19mod1a: AbsoluteIndexedY1
4951 lbl1Cmod1a: Absolute
4955 lbl1Dmod1a: AbsoluteIndexedX1
4959 lbl1Emod1a: AbsoluteIndexedX1
4963 lbl1Fmod1a: AbsoluteLongIndexedX1
4970 lbl21mod1a: DirectIndexedIndirect1
4977 lbl23mod1a: StackasmRelative
4993 lbl27mod1a: DirectIndirectLong
5010 lbl2Cmod1a: Absolute
5014 lbl2Dmod1a: Absolute
5018 lbl2Emod1a: Absolute
5022 lbl2Fmod1a: AbsoluteLong
5029 lbl31mod1a: DirectIndirectIndexed1
5033 lbl32mod1a: DirectIndirect
5037 lbl33mod1a: StackasmRelativeIndirectIndexed1
5041 lbl34mod1a: DirectIndexedX1
5045 lbl35mod1a: DirectIndexedX1
5049 lbl36mod1a: DirectIndexedX1
5053 lbl37mod1a: DirectIndirectIndexedLong1
5060 lbl39mod1a: AbsoluteIndexedY1
5070 lbl3Cmod1a: AbsoluteIndexedX1
5074 lbl3Dmod1a: AbsoluteIndexedX1
5078 lbl3Emod1a: AbsoluteIndexedX1
5082 lbl3Fmod1a: AbsoluteLongIndexedX1
5090 lbl41mod1a: DirectIndexedIndirect1
5097 lbl43mod1a: StackasmRelative
5112 lbl47mod1a: DirectIndirectLong
5131 lbl4Dmod1a: Absolute
5135 lbl4Emod1a: Absolute
5139 lbl4Fmod1a: AbsoluteLong
5146 lbl51mod1a: DirectIndirectIndexed1
5150 lbl52mod1a: DirectIndirect
5154 lbl53mod1a: StackasmRelativeIndirectIndexed1
5161 lbl55mod1a: DirectIndexedX1
5165 lbl56mod1a: DirectIndexedX1
5169 lbl57mod1a: DirectIndirectIndexedLong1
5176 lbl59mod1a: AbsoluteIndexedY1
5189 lbl5Dmod1a: AbsoluteIndexedX1
5193 lbl5Emod1a: AbsoluteIndexedX1
5197 lbl5Fmod1a: AbsoluteLongIndexedX1
5204 lbl61mod1a: DirectIndexedIndirect1
5211 lbl63mod1a: StackasmRelative
5227 lbl67mod1a: DirectIndirectLong
5234 lbl69mod1a: Immediate8
5247 lbl6Dmod1a: Absolute
5251 lbl6Emod1a: Absolute
5255 lbl6Fmod1a: AbsoluteLong
5262 lbl71mod1a: DirectIndirectIndexed1
5266 lbl72mod1a: DirectIndirect
5270 lbl73mod1a: StackasmRelativeIndirectIndexed1
5275 lbl74mod1a: DirectIndexedX1
5279 lbl75mod1a: DirectIndexedX1
5283 lbl76mod1a: DirectIndexedX1
5287 lbl77mod1a: DirectIndirectIndexedLong1
5294 lbl79mod1a: AbsoluteIndexedY1
5304 lbl7Cmod1: AbsoluteIndexedIndirectX1
5308 lbl7Dmod1a: AbsoluteIndexedX1
5312 lbl7Emod1a: AbsoluteIndexedX1
5316 lbl7Fmod1a: AbsoluteLongIndexedX1
5325 lbl81mod1a: DirectIndexedIndirect1
5332 lbl83mod1a: StackasmRelative
5348 lbl87mod1a: DirectIndirectLong
5364 lbl8Cmod1a: Absolute
5368 lbl8Dmod1a: Absolute
5372 lbl8Emod1a: Absolute
5376 lbl8Fmod1a: AbsoluteLong
5383 lbl91mod1a: DirectIndirectIndexed1
5387 lbl92mod1a: DirectIndirect
5391 lbl93mod1a: StackasmRelativeIndirectIndexed1
5395 lbl94mod1a: DirectIndexedX1
5399 lbl95mod1a: DirectIndexedX1
5403 lbl96mod1a: DirectIndexedY1
5407 lbl97mod1a: DirectIndirectIndexedLong1
5414 lbl99mod1a: AbsoluteIndexedY1
5424 lbl9Cmod1a: Absolute
5428 lbl9Dmod1a: AbsoluteIndexedX1
5432 lbl9Emod1: AbsoluteIndexedX1
5436 lbl9Fmod1a: AbsoluteLongIndexedX1
5443 lblA1mod1a: DirectIndexedIndirect1
5450 lblA3mod1a: StackasmRelative
5466 lblA7mod1a: DirectIndirectLong
5482 lblACmod1a: Absolute
5486 lblADmod1a: Absolute
5490 lblAEmod1a: Absolute
5494 lblAFmod1a: AbsoluteLong
5501 lblB1mod1a: DirectIndirectIndexed1
5505 lblB2mod1a: DirectIndirect
5509 lblB3mod1a: StackasmRelativeIndirectIndexed1
5513 lblB4mod1a: DirectIndexedX1
5517 lblB5mod1a: DirectIndexedX1
5521 lblB6mod1a: DirectIndexedY1
5525 lblB7mod1a: DirectIndirectIndexedLong1
5532 lblB9mod1a: AbsoluteIndexedY1
5542 lblBCmod1a: AbsoluteIndexedX1
5546 lblBDmod1a: AbsoluteIndexedX1
5550 lblBEmod1a: AbsoluteIndexedY1
5554 lblBFmod1a: AbsoluteLongIndexedX1
5561 lblC1mod1a: DirectIndexedIndirect1
5569 lblC3mod1a: StackasmRelative
5585 lblC7mod1a: DirectIndirectLong
5601 lblCCmod1a: Absolute
5605 lblCDmod1a: Absolute
5609 lblCEmod1a: Absolute
5613 lblCFmod1a: AbsoluteLong
5620 lblD1mod1a: DirectIndirectIndexed1
5624 lblD2mod1a: DirectIndirect
5628 lblD3mod1a: StackasmRelativeIndirectIndexed1
5635 lblD5mod1a: DirectIndexedX1
5639 lblD6mod1a: DirectIndexedX1
5643 lblD7mod1a: DirectIndirectIndexedLong1
5650 lblD9mod1a: AbsoluteIndexedY1
5663 lblDDmod1a: AbsoluteIndexedX1
5667 lblDEmod1a: AbsoluteIndexedX1
5671 lblDFmod1a: AbsoluteLongIndexedX1
5678 lblE1mod1a: DirectIndexedIndirect1
5686 lblE3mod1a: StackasmRelative
5702 lblE7mod1a: DirectIndirectLong
5709 lblE9mod1a: Immediate8
5719 lblECmod1a: Absolute
5723 lblEDmod1a: Absolute
5727 lblEEmod1a: Absolute
5731 lblEFmod1a: AbsoluteLong
5738 lblF1mod1a: DirectIndirectIndexed1
5742 lblF2mod1a: DirectIndirect
5746 lblF3mod1a: StackasmRelativeIndirectIndexed1
5753 lblF5mod1a: DirectIndexedX1
5757 lblF6mod1a: DirectIndexedX1
5761 lblF7mod1a: DirectIndirectIndexedLong1
5768 lblF9mod1a: AbsoluteIndexedY1
5781 lblFDmod1a: AbsoluteIndexedX1
5785 lblFEmod1a: AbsoluteIndexedX1
5789 lblFFmod1a: AbsoluteLongIndexedX1
5795 jumptable2: .long Op00mod2
6055 lbl01mod2a: DirectIndexedIndirect0
6062 lbl03mod2a: StackasmRelative
6078 lbl07mod2a: DirectIndirectLong
6094 lbl0Cmod2a: Absolute
6098 lbl0Dmod2a: Absolute
6102 lbl0Emod2a: Absolute
6106 lbl0Fmod2a: AbsoluteLong
6113 lbl11mod2a: DirectIndirectIndexed0
6117 lbl12mod2a: DirectIndirect
6121 lbl13mod2a: StackasmRelativeIndirectIndexed0
6129 lbl15mod2a: DirectIndexedX0
6133 lbl16mod2a: DirectIndexedX0
6137 lbl17mod2a: DirectIndirectIndexedLong0
6144 lbl19mod2a: AbsoluteIndexedY0
6154 lbl1Cmod2a: Absolute
6158 lbl1Dmod2a: AbsoluteIndexedX0
6162 lbl1Emod2a: AbsoluteIndexedX0
6166 lbl1Fmod2a: AbsoluteLongIndexedX0
6173 lbl21mod2a: DirectIndexedIndirect0
6180 lbl23mod2a: StackasmRelative
6196 lbl27mod2a: DirectIndirectLong
6213 lbl2Cmod2a: Absolute
6217 lbl2Dmod2a: Absolute
6221 lbl2Emod2a: Absolute
6225 lbl2Fmod2a: AbsoluteLong
6232 lbl31mod2a: DirectIndirectIndexed0
6236 lbl32mod2a: DirectIndirect
6240 lbl33mod2a: StackasmRelativeIndirectIndexed0
6244 lbl34mod2a: DirectIndexedX0
6248 lbl35mod2a: DirectIndexedX0
6252 lbl36mod2a: DirectIndexedX0
6256 lbl37mod2a: DirectIndirectIndexedLong0
6263 lbl39mod2a: AbsoluteIndexedY0
6273 lbl3Cmod2a: AbsoluteIndexedX0
6277 lbl3Dmod2a: AbsoluteIndexedX0
6281 lbl3Emod2a: AbsoluteIndexedX0
6285 lbl3Fmod2a: AbsoluteLongIndexedX0
6293 lbl41mod2a: DirectIndexedIndirect0
6300 lbl43mod2a: StackasmRelative
6315 lbl47mod2a: DirectIndirectLong
6334 lbl4Dmod2a: Absolute
6338 lbl4Emod2a: Absolute
6342 lbl4Fmod2a: AbsoluteLong
6349 lbl51mod2a: DirectIndirectIndexed0
6353 lbl52mod2a: DirectIndirect
6357 lbl53mod2a: StackasmRelativeIndirectIndexed0
6364 lbl55mod2a: DirectIndexedX0
6368 lbl56mod2a: DirectIndexedX0
6372 lbl57mod2a: DirectIndirectIndexedLong0
6379 lbl59mod2a: AbsoluteIndexedY0
6392 lbl5Dmod2a: AbsoluteIndexedX0
6396 lbl5Emod2a: AbsoluteIndexedX0
6400 lbl5Fmod2a: AbsoluteLongIndexedX0
6407 lbl61mod2a: DirectIndexedIndirect0
6414 lbl63mod2a: StackasmRelative
6430 lbl67mod2a: DirectIndirectLong
6437 lbl69mod2a: Immediate8
6450 lbl6Dmod2a: Absolute
6454 lbl6Emod2a: Absolute
6458 lbl6Fmod2a: AbsoluteLong
6465 lbl71mod2a: DirectIndirectIndexed0
6469 lbl72mod2a: DirectIndirect
6473 lbl73mod2a: StackasmRelativeIndirectIndexed0
6477 lbl74mod2a: DirectIndexedX0
6481 lbl75mod2a: DirectIndexedX0
6485 lbl76mod2a: DirectIndexedX0
6489 lbl77mod2a: DirectIndirectIndexedLong0
6496 lbl79mod2a: AbsoluteIndexedY0
6506 lbl7Cmod2: AbsoluteIndexedIndirectX0
6510 lbl7Dmod2a: AbsoluteIndexedX0
6514 lbl7Emod2a: AbsoluteIndexedX0
6518 lbl7Fmod2a: AbsoluteLongIndexedX0
6527 lbl81mod2a: DirectIndexedIndirect0
6534 lbl83mod2a: StackasmRelative
6550 lbl87mod2a: DirectIndirectLong
6566 lbl8Cmod2a: Absolute
6570 lbl8Dmod2a: Absolute
6574 lbl8Emod2a: Absolute
6578 lbl8Fmod2a: AbsoluteLong
6585 lbl91mod2a: DirectIndirectIndexed0
6589 lbl92mod2a: DirectIndirect
6593 lbl93mod2a: StackasmRelativeIndirectIndexed0
6597 lbl94mod2a: DirectIndexedX0
6601 lbl95mod2a: DirectIndexedX0
6605 lbl96mod2a: DirectIndexedY0
6609 lbl97mod2a: DirectIndirectIndexedLong0
6616 lbl99mod2a: AbsoluteIndexedY0
6626 lbl9Cmod2a: Absolute
6630 lbl9Dmod2a: AbsoluteIndexedX0
6634 lbl9Emod2: AbsoluteIndexedX0
6638 lbl9Fmod2a: AbsoluteLongIndexedX0
6645 lblA1mod2a: DirectIndexedIndirect0
6652 lblA3mod2a: StackasmRelative
6668 lblA7mod2a: DirectIndirectLong
6684 lblACmod2a: Absolute
6688 lblADmod2a: Absolute
6692 lblAEmod2a: Absolute
6696 lblAFmod2a: AbsoluteLong
6703 lblB1mod2a: DirectIndirectIndexed0
6707 lblB2mod2a: DirectIndirect
6711 lblB3mod2a: StackasmRelativeIndirectIndexed0
6715 lblB4mod2a: DirectIndexedX0
6719 lblB5mod2a: DirectIndexedX0
6723 lblB6mod2a: DirectIndexedY0
6727 lblB7mod2a: DirectIndirectIndexedLong0
6734 lblB9mod2a: AbsoluteIndexedY0
6744 lblBCmod2a: AbsoluteIndexedX0
6748 lblBDmod2a: AbsoluteIndexedX0
6752 lblBEmod2a: AbsoluteIndexedY0
6756 lblBFmod2a: AbsoluteLongIndexedX0
6763 lblC1mod2a: DirectIndexedIndirect0
6771 lblC3mod2a: StackasmRelative
6787 lblC7mod2a: DirectIndirectLong
6803 lblCCmod2a: Absolute
6807 lblCDmod2a: Absolute
6811 lblCEmod2a: Absolute
6815 lblCFmod2a: AbsoluteLong
6822 lblD1mod2a: DirectIndirectIndexed0
6826 lblD2mod2a: DirectIndirect
6830 lblD3mod2a: StackasmRelativeIndirectIndexed0
6837 lblD5mod2a: DirectIndexedX0
6841 lblD6mod2a: DirectIndexedX0
6845 lblD7mod2a: DirectIndirectIndexedLong0
6852 lblD9mod2a: AbsoluteIndexedY0
6865 lblDDmod2a: AbsoluteIndexedX0
6869 lblDEmod2a: AbsoluteIndexedX0
6873 lblDFmod2a: AbsoluteLongIndexedX0
6880 lblE1mod2a: DirectIndexedIndirect0
6888 lblE3mod2a: StackasmRelative
6904 lblE7mod2a: DirectIndirectLong
6911 lblE9mod2a: Immediate8
6921 lblECmod2a: Absolute
6925 lblEDmod2a: Absolute
6929 lblEEmod2a: Absolute
6933 lblEFmod2a: AbsoluteLong
6940 lblF1mod2a: DirectIndirectIndexed0
6944 lblF2mod2a: DirectIndirect
6948 lblF3mod2a: StackasmRelativeIndirectIndexed0
6955 lblF5mod2a: DirectIndexedX0
6959 lblF6mod2a: DirectIndexedX0
6963 lblF7mod2a: DirectIndirectIndexedLong0
6970 lblF9mod2a: AbsoluteIndexedY0
6983 lblFDmod2a: AbsoluteIndexedX0
6987 lblFEmod2a: AbsoluteIndexedX0
6991 lblFFmod2a: AbsoluteLongIndexedX0
6998 jumptable3: .long Op00mod3
7258 lbl01mod3a: DirectIndexedIndirect0
7265 lbl03mod3a: StackasmRelative
7281 lbl07mod3a: DirectIndirectLong
7297 lbl0Cmod3a: Absolute
7301 lbl0Dmod3a: Absolute
7305 lbl0Emod3a: Absolute
7309 lbl0Fmod3a: AbsoluteLong
7316 lbl11mod3a: DirectIndirectIndexed0
7320 lbl12mod3a: DirectIndirect
7324 lbl13mod3a: StackasmRelativeIndirectIndexed0
7332 lbl15mod3a: DirectIndexedX0
7336 lbl16mod3a: DirectIndexedX0
7340 lbl17mod3a: DirectIndirectIndexedLong0
7347 lbl19mod3a: AbsoluteIndexedY0
7357 lbl1Cmod3a: Absolute
7361 lbl1Dmod3a: AbsoluteIndexedX0
7365 lbl1Emod3a: AbsoluteIndexedX0
7369 lbl1Fmod3a: AbsoluteLongIndexedX0
7376 lbl21mod3a: DirectIndexedIndirect0
7383 lbl23mod3a: StackasmRelative
7399 lbl27mod3a: DirectIndirectLong
7416 lbl2Cmod3a: Absolute
7420 lbl2Dmod3a: Absolute
7424 lbl2Emod3a: Absolute
7428 lbl2Fmod3a: AbsoluteLong
7435 lbl31mod3a: DirectIndirectIndexed0
7439 lbl32mod3a: DirectIndirect
7443 lbl33mod3a: StackasmRelativeIndirectIndexed0
7447 lbl34mod3a: DirectIndexedX0
7451 lbl35mod3a: DirectIndexedX0
7455 lbl36mod3a: DirectIndexedX0
7459 lbl37mod3a: DirectIndirectIndexedLong0
7466 lbl39mod3a: AbsoluteIndexedY0
7476 lbl3Cmod3a: AbsoluteIndexedX0
7480 lbl3Dmod3a: AbsoluteIndexedX0
7484 lbl3Emod3a: AbsoluteIndexedX0
7488 lbl3Fmod3a: AbsoluteLongIndexedX0
7496 lbl41mod3a: DirectIndexedIndirect0
7503 lbl43mod3a: StackasmRelative
7518 lbl47mod3a: DirectIndirectLong
7537 lbl4Dmod3a: Absolute
7541 lbl4Emod3a: Absolute
7545 lbl4Fmod3a: AbsoluteLong
7552 lbl51mod3a: DirectIndirectIndexed0
7556 lbl52mod3a: DirectIndirect
7560 lbl53mod3a: StackasmRelativeIndirectIndexed0
7567 lbl55mod3a: DirectIndexedX0
7571 lbl56mod3a: DirectIndexedX0
7575 lbl57mod3a: DirectIndirectIndexedLong0
7582 lbl59mod3a: AbsoluteIndexedY0
7595 lbl5Dmod3a: AbsoluteIndexedX0
7599 lbl5Emod3a: AbsoluteIndexedX0
7603 lbl5Fmod3a: AbsoluteLongIndexedX0
7610 lbl61mod3a: DirectIndexedIndirect0
7617 lbl63mod3a: StackasmRelative
7635 lbl67mod3a: DirectIndirectLong
7643 lbl69mod3a: Immediate16
7657 lbl6Dmod3a: Absolute
7661 lbl6Emod3a: Absolute
7665 lbl6Fmod3a: AbsoluteLong
7672 lbl71mod3a: DirectIndirectIndexed0
7676 lbl72mod3a: DirectIndirect
7680 lbl73mod3a: StackasmRelativeIndirectIndexed0
7685 lbl74mod3a: DirectIndexedX0
7689 lbl75mod3a: DirectIndexedX0
7694 lbl76mod3a: DirectIndexedX0
7698 lbl77mod3a: DirectIndirectIndexedLong0
7705 lbl79mod3a: AbsoluteIndexedY0
7715 lbl7Cmod3: AbsoluteIndexedIndirectX0
7719 lbl7Dmod3a: AbsoluteIndexedX0
7723 lbl7Emod3a: AbsoluteIndexedX0
7727 lbl7Fmod3a: AbsoluteLongIndexedX0
7735 lbl81mod3a: DirectIndexedIndirect0
7742 lbl83mod3a: StackasmRelative
7758 lbl87mod3a: DirectIndirectLong
7774 lbl8Cmod3a: Absolute
7778 lbl8Dmod3a: Absolute
7782 lbl8Emod3a: Absolute
7786 lbl8Fmod3a: AbsoluteLong
7793 lbl91mod3a: DirectIndirectIndexed0
7797 lbl92mod3a: DirectIndirect
7801 lbl93mod3a: StackasmRelativeIndirectIndexed0
7805 lbl94mod3a: DirectIndexedX0
7809 lbl95mod3a: DirectIndexedX0
7813 lbl96mod3a: DirectIndexedY0
7817 lbl97mod3a: DirectIndirectIndexedLong0
7824 lbl99mod3a: AbsoluteIndexedY0
7834 lbl9Cmod3a: Absolute
7838 lbl9Dmod3a: AbsoluteIndexedX0
7842 lbl9Emod3: AbsoluteIndexedX0
7846 lbl9Fmod3a: AbsoluteLongIndexedX0
7853 lblA1mod3a: DirectIndexedIndirect0
7860 lblA3mod3a: StackasmRelative
7876 lblA7mod3a: DirectIndirectLong
7892 lblACmod3a: Absolute
7896 lblADmod3a: Absolute
7900 lblAEmod3a: Absolute
7904 lblAFmod3a: AbsoluteLong
7911 lblB1mod3a: DirectIndirectIndexed0
7915 lblB2mod3a: DirectIndirect
7919 lblB3mod3a: StackasmRelativeIndirectIndexed0
7923 lblB4mod3a: DirectIndexedX0
7927 lblB5mod3a: DirectIndexedX0
7931 lblB6mod3a: DirectIndexedY0
7935 lblB7mod3a: DirectIndirectIndexedLong0
7942 lblB9mod3a: AbsoluteIndexedY0
7952 lblBCmod3a: AbsoluteIndexedX0
7956 lblBDmod3a: AbsoluteIndexedX0
7960 lblBEmod3a: AbsoluteIndexedY0
7964 lblBFmod3a: AbsoluteLongIndexedX0
7971 lblC1mod3a: DirectIndexedIndirect0
7979 lblC3mod3a: StackasmRelative
7995 lblC7mod3a: DirectIndirectLong
8011 lblCCmod3a: Absolute
8015 lblCDmod3a: Absolute
8019 lblCEmod3a: Absolute
8023 lblCFmod3a: AbsoluteLong
8030 lblD1mod3a: DirectIndirectIndexed0
8034 lblD2mod3a: DirectIndirect
8038 lblD3mod3a: StackasmRelativeIndirectIndexed0
8045 lblD5mod3a: DirectIndexedX0
8049 lblD6mod3a: DirectIndexedX0
8053 lblD7mod3a: DirectIndirectIndexedLong0
8060 lblD9mod3a: AbsoluteIndexedY0
8073 lblDDmod3a: AbsoluteIndexedX0
8077 lblDEmod3a: AbsoluteIndexedX0
8081 lblDFmod3a: AbsoluteLongIndexedX0
8088 lblE1mod3a: DirectIndexedIndirect0
8096 lblE3mod3a: StackasmRelative
8112 lblE7mod3a: DirectIndirectLong
8119 lblE9mod3a: Immediate16
8129 lblECmod3a: Absolute
8133 lblEDmod3a: Absolute
8137 lblEEmod3a: Absolute
8141 lblEFmod3a: AbsoluteLong
8148 lblF1mod3a: DirectIndirectIndexed0
8152 lblF2mod3a: DirectIndirect
8156 lblF3mod3a: StackasmRelativeIndirectIndexed0
8163 lblF5mod3a: DirectIndexedX0
8167 lblF6mod3a: DirectIndexedX0
8171 lblF7mod3a: DirectIndirectIndexedLong0
8178 lblF9mod3a: AbsoluteIndexedY0
8191 lblFDmod3a: AbsoluteIndexedX0
8195 lblFEmod3a: AbsoluteIndexedX0
8199 lblFFmod3a: AbsoluteLongIndexedX0
8204 jumptable4: .long Op00mod4
8464 lbl01mod4a: DirectIndexedIndirect1
8471 lbl03mod4a: StackasmRelative
8487 lbl07mod4a: DirectIndirectLong
8503 lbl0Cmod4a: Absolute
8507 lbl0Dmod4a: Absolute
8511 lbl0Emod4a: Absolute
8515 lbl0Fmod4a: AbsoluteLong
8522 lbl11mod4a: DirectIndirectIndexed1
8526 lbl12mod4a: DirectIndirect
8530 lbl13mod4a: StackasmRelativeIndirectIndexed1
8538 lbl15mod4a: DirectIndexedX1
8542 lbl16mod4a: DirectIndexedX1
8546 lbl17mod4a: DirectIndirectIndexedLong1
8553 lbl19mod4a: AbsoluteIndexedY1
8563 lbl1Cmod4a: Absolute
8567 lbl1Dmod4a: AbsoluteIndexedX1
8571 lbl1Emod4a: AbsoluteIndexedX1
8575 lbl1Fmod4a: AbsoluteLongIndexedX1
8582 lbl21mod4a: DirectIndexedIndirect1
8589 lbl23mod4a: StackasmRelative
8605 lbl27mod4a: DirectIndirectLong
8622 lbl2Cmod4a: Absolute
8626 lbl2Dmod4a: Absolute
8630 lbl2Emod4a: Absolute
8634 lbl2Fmod4a: AbsoluteLong
8641 lbl31mod4a: DirectIndirectIndexed1
8645 lbl32mod4a: DirectIndirect
8649 lbl33mod4a: StackasmRelativeIndirectIndexed1
8653 lbl34mod4a: DirectIndexedX1
8657 lbl35mod4a: DirectIndexedX1
8661 lbl36mod4a: DirectIndexedX1
8665 lbl37mod4a: DirectIndirectIndexedLong1
8672 lbl39mod4a: AbsoluteIndexedY1
8682 lbl3Cmod4a: AbsoluteIndexedX1
8686 lbl3Dmod4a: AbsoluteIndexedX1
8690 lbl3Emod4a: AbsoluteIndexedX1
8694 lbl3Fmod4a: AbsoluteLongIndexedX1
8702 lbl41mod4a: DirectIndexedIndirect1
8709 lbl43mod4a: StackasmRelative
8724 lbl47mod4a: DirectIndirectLong
8743 lbl4Dmod4a: Absolute
8747 lbl4Emod4a: Absolute
8751 lbl4Fmod4a: AbsoluteLong
8758 lbl51mod4a: DirectIndirectIndexed1
8762 lbl52mod4a: DirectIndirect
8766 lbl53mod4a: StackasmRelativeIndirectIndexed1
8773 lbl55mod4a: DirectIndexedX1
8777 lbl56mod4a: DirectIndexedX1
8781 lbl57mod4a: DirectIndirectIndexedLong1
8788 lbl59mod4a: AbsoluteIndexedY1
8801 lbl5Dmod4a: AbsoluteIndexedX1
8805 lbl5Emod4a: AbsoluteIndexedX1
8809 lbl5Fmod4a: AbsoluteLongIndexedX1
8816 lbl61mod4a: DirectIndexedIndirect1
8823 lbl63mod4a: StackasmRelative
8841 lbl67mod4a: DirectIndirectLong
8849 lbl69mod4a: Immediate16
8863 lbl6Dmod4a: Absolute
8867 lbl6Emod4a: Absolute
8871 lbl6Fmod4a: AbsoluteLong
8878 lbl71mod4a: DirectIndirectIndexed1
8882 lbl72mod4a: DirectIndirect
8886 lbl73mod4a: StackasmRelativeIndirectIndexed1
8891 lbl74mod4a: DirectIndexedX1
8895 lbl75mod4a: DirectIndexedX1
8900 lbl76mod4a: DirectIndexedX1
8904 lbl77mod4a: DirectIndirectIndexedLong1
8911 lbl79mod4a: AbsoluteIndexedY1
8921 lbl7Cmod4: AbsoluteIndexedIndirectX1
8925 lbl7Dmod4a: AbsoluteIndexedX1
8929 lbl7Emod4a: AbsoluteIndexedX1
8933 lbl7Fmod4a: AbsoluteLongIndexedX1
8941 lbl81mod4a: DirectIndexedIndirect1
8948 lbl83mod4a: StackasmRelative
8964 lbl87mod4a: DirectIndirectLong
8980 lbl8Cmod4a: Absolute
8984 lbl8Dmod4a: Absolute
8988 lbl8Emod4a: Absolute
8992 lbl8Fmod4a: AbsoluteLong
8999 lbl91mod4a: DirectIndirectIndexed1
9003 lbl92mod4a: DirectIndirect
9007 lbl93mod4a: StackasmRelativeIndirectIndexed1
9011 lbl94mod4a: DirectIndexedX1
9015 lbl95mod4a: DirectIndexedX1
9019 lbl96mod4a: DirectIndexedY1
9023 lbl97mod4a: DirectIndirectIndexedLong1
9030 lbl99mod4a: AbsoluteIndexedY1
9040 lbl9Cmod4a: Absolute
9044 lbl9Dmod4a: AbsoluteIndexedX1
9048 lbl9Emod4: AbsoluteIndexedX1
9052 lbl9Fmod4a: AbsoluteLongIndexedX1
9059 lblA1mod4a: DirectIndexedIndirect1
9066 lblA3mod4a: StackasmRelative
9082 lblA7mod4a: DirectIndirectLong
9098 lblACmod4a: Absolute
9102 lblADmod4a: Absolute
9106 lblAEmod4a: Absolute
9110 lblAFmod4a: AbsoluteLong
9117 lblB1mod4a: DirectIndirectIndexed1
9121 lblB2mod4a: DirectIndirect
9125 lblB3mod4a: StackasmRelativeIndirectIndexed1
9129 lblB4mod4a: DirectIndexedX1
9133 lblB5mod4a: DirectIndexedX1
9137 lblB6mod4a: DirectIndexedY1
9141 lblB7mod4a: DirectIndirectIndexedLong1
9148 lblB9mod4a: AbsoluteIndexedY1
9158 lblBCmod4a: AbsoluteIndexedX1
9162 lblBDmod4a: AbsoluteIndexedX1
9166 lblBEmod4a: AbsoluteIndexedY1
9170 lblBFmod4a: AbsoluteLongIndexedX1
9177 lblC1mod4a: DirectIndexedIndirect1
9185 lblC3mod4a: StackasmRelative
9201 lblC7mod4a: DirectIndirectLong
9217 lblCCmod4a: Absolute
9221 lblCDmod4a: Absolute
9225 lblCEmod4a: Absolute
9229 lblCFmod4a: AbsoluteLong
9236 lblD1mod4a: DirectIndirectIndexed1
9240 lblD2mod4a: DirectIndirect
9244 lblD3mod4a: StackasmRelativeIndirectIndexed1
9251 lblD5mod4a: DirectIndexedX1
9255 lblD6mod4a: DirectIndexedX1
9259 lblD7mod4a: DirectIndirectIndexedLong1
9266 lblD9mod4a: AbsoluteIndexedY1
9279 lblDDmod4a: AbsoluteIndexedX1
9283 lblDEmod4a: AbsoluteIndexedX1
9287 lblDFmod4a: AbsoluteLongIndexedX1
9294 lblE1mod4a: DirectIndexedIndirect1
9302 lblE3mod4a: StackasmRelative
9318 lblE7mod4a: DirectIndirectLong
9325 lblE9mod4a: Immediate16
9335 lblECmod4a: Absolute
9339 lblEDmod4a: Absolute
9343 lblEEmod4a: Absolute
9347 lblEFmod4a: AbsoluteLong
9354 lblF1mod4a: DirectIndirectIndexed1
9358 lblF2mod4a: DirectIndirect
9362 lblF3mod4a: StackasmRelativeIndirectIndexed1
9369 lblF5mod4a: DirectIndexedX1
9373 lblF6mod4a: DirectIndexedX1
9377 lblF7mod4a: DirectIndirectIndexedLong1
9384 lblF9mod4a: AbsoluteIndexedY1
9397 lblFDmod4a: AbsoluteIndexedX1
9401 lblFEmod4a: AbsoluteIndexedX1
9405 lblFFmod4a: AbsoluteLongIndexedX1