1 --- kernel-power-2.6.28.orig/arch/arm/Kconfig
2 +++ kernel-power-2.6.28/arch/arm/Kconfig
5 source "drivers/pcmcia/Kconfig"
7 +config ARM_ERRATA_430973
8 + bool "ARM errata: Stale prediction on replaced interworking branch"
11 + This option enables the workaround for the 430973 Cortex-A8
12 + (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
13 + interworking branch is replaced with another code sequence at the
14 + same virtual address, whether due to self-modifying code or virtual
15 + to physical address re-mapping, Cortex-A8 does not recover from the
16 + stale interworking branch prediction. This results in Cortex-A8
17 + executing the new code sequence in the incorrect ARM or Thumb state.
18 + The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
19 + and also flushes the branch target cache at every context switch.
20 + Note that setting specific bits in the ACTLR register may not be
21 + available in non-secure mode.
25 menu "Kernel Features"
26 --- kernel-power-2.6.28.orig/arch/arm/mm/proc-v7.S
27 +++ kernel-power-2.6.28/arch/arm/mm/proc-v7.S
31 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
32 - orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
33 + orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
34 +#ifdef CONFIG_ARM_ERRATA_430973
35 + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
37 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
39 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
41 stmia r12, {r0-r5, r7, r9, r11, lr}
42 bl v7_flush_dcache_all
43 ldmia r12, {r0-r5, r7, r9, r11, lr}
44 +#ifdef CONFIG_ARM_ERRATA_430973
45 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register
46 + orr r10, r10, #(1 << 6) @ set IBE to 1
47 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register
51 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate