2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 #define HW_MOUSE_ACCEL
39 struct vmsvga_state_s {
61 ram_addr_t vram_offset;
64 target_phys_addr_t vram_base;
81 struct __attribute__((__packed__)) {
86 /* Add registers here when adding capabilities. */
91 #define REDRAW_FIFO_LEN 512
92 struct vmsvga_rect_s {
94 } redraw_fifo[REDRAW_FIFO_LEN];
95 int redraw_fifo_first, redraw_fifo_last;
98 struct pci_vmsvga_state_s {
100 struct vmsvga_state_s chip;
103 #define SVGA_MAGIC 0x900000UL
104 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
105 #define SVGA_ID_0 SVGA_MAKE_ID(0)
106 #define SVGA_ID_1 SVGA_MAKE_ID(1)
107 #define SVGA_ID_2 SVGA_MAKE_ID(2)
109 #define SVGA_LEGACY_BASE_PORT 0x4560
110 #define SVGA_INDEX_PORT 0x0
111 #define SVGA_VALUE_PORT 0x1
112 #define SVGA_BIOS_PORT 0x2
114 #define SVGA_VERSION_2
116 #ifdef SVGA_VERSION_2
117 # define SVGA_ID SVGA_ID_2
118 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
119 # define SVGA_IO_MUL 1
120 # define SVGA_FIFO_SIZE 0x10000
121 # define SVGA_MEM_BASE 0xe0000000
122 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
124 # define SVGA_ID SVGA_ID_1
125 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
126 # define SVGA_IO_MUL 4
127 # define SVGA_FIFO_SIZE 0x10000
128 # define SVGA_MEM_BASE 0xe0000000
129 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
133 /* ID 0, 1 and 2 registers */
138 SVGA_REG_MAX_WIDTH = 4,
139 SVGA_REG_MAX_HEIGHT = 5,
141 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
142 SVGA_REG_PSEUDOCOLOR = 8,
143 SVGA_REG_RED_MASK = 9,
144 SVGA_REG_GREEN_MASK = 10,
145 SVGA_REG_BLUE_MASK = 11,
146 SVGA_REG_BYTES_PER_LINE = 12,
147 SVGA_REG_FB_START = 13,
148 SVGA_REG_FB_OFFSET = 14,
149 SVGA_REG_VRAM_SIZE = 15,
150 SVGA_REG_FB_SIZE = 16,
152 /* ID 1 and 2 registers */
153 SVGA_REG_CAPABILITIES = 17,
154 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
155 SVGA_REG_MEM_SIZE = 19,
156 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
157 SVGA_REG_SYNC = 21, /* Write to force synchronization */
158 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
159 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
160 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
161 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
162 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
163 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
164 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
165 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
166 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
167 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
168 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
170 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
171 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
172 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
175 #define SVGA_CAP_NONE 0
176 #define SVGA_CAP_RECT_FILL (1 << 0)
177 #define SVGA_CAP_RECT_COPY (1 << 1)
178 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
179 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
180 #define SVGA_CAP_RASTER_OP (1 << 4)
181 #define SVGA_CAP_CURSOR (1 << 5)
182 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
183 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
184 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
185 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
186 #define SVGA_CAP_GLYPH (1 << 10)
187 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
188 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
189 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
190 #define SVGA_CAP_3D (1 << 14)
191 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
192 #define SVGA_CAP_MULTIMON (1 << 16)
193 #define SVGA_CAP_PITCHLOCK (1 << 17)
196 * FIFO offsets (seen as an array of 32-bit words)
200 * The original defined FIFO offsets
203 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
208 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
210 SVGA_FIFO_CAPABILITIES = 4,
213 SVGA_FIFO_3D_HWVERSION,
217 #define SVGA_FIFO_CAP_NONE 0
218 #define SVGA_FIFO_CAP_FENCE (1 << 0)
219 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
220 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
222 #define SVGA_FIFO_FLAG_NONE 0
223 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
225 /* These values can probably be changed arbitrarily. */
226 #define SVGA_SCRATCH_SIZE 0x8000
227 #define SVGA_MAX_WIDTH 2360
228 #define SVGA_MAX_HEIGHT 1770
231 # define GUEST_OS_BASE 0x5001
232 static const char *vmsvga_guest_id[] = {
233 [0x00 ... 0x15] = "an unknown OS",
235 [0x01] = "Windows 3.1",
236 [0x02] = "Windows 95",
237 [0x03] = "Windows 98",
238 [0x04] = "Windows ME",
239 [0x05] = "Windows NT",
240 [0x06] = "Windows 2000",
245 [0x15] = "Windows 2003",
250 SVGA_CMD_INVALID_CMD = 0,
252 SVGA_CMD_RECT_FILL = 2,
253 SVGA_CMD_RECT_COPY = 3,
254 SVGA_CMD_DEFINE_BITMAP = 4,
255 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
256 SVGA_CMD_DEFINE_PIXMAP = 6,
257 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
258 SVGA_CMD_RECT_BITMAP_FILL = 8,
259 SVGA_CMD_RECT_PIXMAP_FILL = 9,
260 SVGA_CMD_RECT_BITMAP_COPY = 10,
261 SVGA_CMD_RECT_PIXMAP_COPY = 11,
262 SVGA_CMD_FREE_OBJECT = 12,
263 SVGA_CMD_RECT_ROP_FILL = 13,
264 SVGA_CMD_RECT_ROP_COPY = 14,
265 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
266 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
267 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
268 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
269 SVGA_CMD_DEFINE_CURSOR = 19,
270 SVGA_CMD_DISPLAY_CURSOR = 20,
271 SVGA_CMD_MOVE_CURSOR = 21,
272 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
273 SVGA_CMD_DRAW_GLYPH = 23,
274 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
275 SVGA_CMD_UPDATE_VERBOSE = 25,
276 SVGA_CMD_SURFACE_FILL = 26,
277 SVGA_CMD_SURFACE_COPY = 27,
278 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
279 SVGA_CMD_FRONT_ROP_FILL = 29,
283 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
285 SVGA_CURSOR_ON_HIDE = 0,
286 SVGA_CURSOR_ON_SHOW = 1,
287 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
288 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
291 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
292 int x, int y, int w, int h)
302 if (x + w > s->width) {
303 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
305 x = MIN(x, s->width);
309 if (y + h > s->height) {
310 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
312 y = MIN(y, s->height);
317 bypl = s->bypp * s->width;
319 start = s->bypp * x + bypl * y;
320 src = s->vram + start;
321 dst = s->ds->data + start;
323 for (; line > 0; line --, src += bypl, dst += bypl)
324 memcpy(dst, src, width);
327 dpy_update(s->ds, x, y, w, h);
330 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
333 memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
336 dpy_update(s->ds, 0, 0, s->width, s->height);
340 # define vmsvga_update_rect_delayed vmsvga_update_rect
342 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
343 int x, int y, int w, int h)
345 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
346 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
354 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
356 struct vmsvga_rect_s *rect;
357 if (s->invalidated) {
358 s->redraw_fifo_first = s->redraw_fifo_last;
361 /* Overlapping region updates can be optimised out here - if someone
362 * knows a smart algorithm to do that, please share. */
363 while (s->redraw_fifo_first != s->redraw_fifo_last) {
364 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
365 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
366 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
371 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
372 int x0, int y0, int x1, int y1, int w, int h)
375 uint8_t *vram = s->ds->data;
377 uint8_t *vram = s->vram;
379 int bypl = s->bypp * s->width;
380 int width = s->bypp * w;
386 s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
391 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
392 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
393 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
394 memmove(ptr[1], ptr[0], width);
396 ptr[0] = vram + s->bypp * x0 + bypl * y0;
397 ptr[1] = vram + s->bypp * x1 + bypl * y1;
398 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
399 memmove(ptr[1], ptr[0], width);
403 vmsvga_update_rect_delayed(s, x1, y1, w, h);
408 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
409 uint32_t c, int x, int y, int w, int h)
412 uint8_t *vram = s->ds->data;
414 uint8_t *vram = s->vram;
417 int bypl = bypp * s->width;
418 int width = bypp * w;
421 uint8_t *fst = vram + bypp * x + bypl * y;
428 s->ds->dpy_fill(s->ds, x, y, w, h, c);
440 for (column = width; column > 0; column --) {
441 *(dst ++) = *(src ++);
442 if (src - col == bypp)
446 for (; line > 0; line --) {
448 memcpy(dst, fst, width);
453 vmsvga_update_rect_delayed(s, x, y, w, h);
457 struct vmsvga_cursor_definition_s {
465 uint32_t image[1024];
468 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
469 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
471 #ifdef HW_MOUSE_ACCEL
472 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
473 struct vmsvga_cursor_definition_s *c)
476 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
477 c->mask[i] = ~c->mask[i];
479 if (s->ds->cursor_define)
480 s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
481 (uint8_t *) c->image, (uint8_t *) c->mask);
485 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
487 if (!s->config || !s->enable)
489 return (s->cmd->next_cmd == s->cmd->stop);
492 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
494 uint32_t cmd = s->fifo[s->cmd->stop >> 2];
496 if (s->cmd->stop >= s->cmd->max)
497 s->cmd->stop = s->cmd->min;
501 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
503 uint32_t cmd, colour;
505 int x, y, dx, dy, width, height;
506 struct vmsvga_cursor_definition_s cursor;
507 while (!vmsvga_fifo_empty(s))
508 switch (cmd = vmsvga_fifo_read(s)) {
509 case SVGA_CMD_UPDATE:
510 case SVGA_CMD_UPDATE_VERBOSE:
511 x = vmsvga_fifo_read(s);
512 y = vmsvga_fifo_read(s);
513 width = vmsvga_fifo_read(s);
514 height = vmsvga_fifo_read(s);
515 vmsvga_update_rect_delayed(s, x, y, width, height);
518 case SVGA_CMD_RECT_FILL:
519 colour = vmsvga_fifo_read(s);
520 x = vmsvga_fifo_read(s);
521 y = vmsvga_fifo_read(s);
522 width = vmsvga_fifo_read(s);
523 height = vmsvga_fifo_read(s);
525 vmsvga_fill_rect(s, colour, x, y, width, height);
531 case SVGA_CMD_RECT_COPY:
532 x = vmsvga_fifo_read(s);
533 y = vmsvga_fifo_read(s);
534 dx = vmsvga_fifo_read(s);
535 dy = vmsvga_fifo_read(s);
536 width = vmsvga_fifo_read(s);
537 height = vmsvga_fifo_read(s);
539 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
545 case SVGA_CMD_DEFINE_CURSOR:
546 cursor.id = vmsvga_fifo_read(s);
547 cursor.hot_x = vmsvga_fifo_read(s);
548 cursor.hot_y = vmsvga_fifo_read(s);
549 cursor.width = x = vmsvga_fifo_read(s);
550 cursor.height = y = vmsvga_fifo_read(s);
552 cursor.bpp = vmsvga_fifo_read(s);
553 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
554 cursor.mask[args] = vmsvga_fifo_read(s);
555 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
556 cursor.image[args] = vmsvga_fifo_read(s);
557 #ifdef HW_MOUSE_ACCEL
558 vmsvga_cursor_define(s, &cursor);
566 * Other commands that we at least know the number of arguments
567 * for so we can avoid FIFO desync if driver uses them illegally.
569 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
573 x = vmsvga_fifo_read(s);
574 y = vmsvga_fifo_read(s);
577 case SVGA_CMD_RECT_ROP_FILL:
580 case SVGA_CMD_RECT_ROP_COPY:
583 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
586 args = 7 + (vmsvga_fifo_read(s) >> 2);
588 case SVGA_CMD_SURFACE_ALPHA_BLEND:
593 * Other commands that are not listed as depending on any
594 * CAPABILITIES bits, but are not described in the README either.
596 case SVGA_CMD_SURFACE_FILL:
597 case SVGA_CMD_SURFACE_COPY:
598 case SVGA_CMD_FRONT_ROP_FILL:
600 case SVGA_CMD_INVALID_CMD:
607 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
615 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
617 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
621 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
623 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
627 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
630 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
635 case SVGA_REG_ENABLE:
641 case SVGA_REG_HEIGHT:
644 case SVGA_REG_MAX_WIDTH:
645 return SVGA_MAX_WIDTH;
647 case SVGA_REG_MAX_HEIGHT:
648 return SVGA_MAX_HEIGHT;
653 case SVGA_REG_BITS_PER_PIXEL:
654 return (s->depth + 7) & ~7;
656 case SVGA_REG_PSEUDOCOLOR:
659 case SVGA_REG_RED_MASK:
661 case SVGA_REG_GREEN_MASK:
663 case SVGA_REG_BLUE_MASK:
666 case SVGA_REG_BYTES_PER_LINE:
667 return ((s->depth + 7) >> 3) * s->new_width;
669 case SVGA_REG_FB_START:
672 case SVGA_REG_FB_OFFSET:
675 case SVGA_REG_VRAM_SIZE:
676 return s->vram_size - SVGA_FIFO_SIZE;
678 case SVGA_REG_FB_SIZE:
681 case SVGA_REG_CAPABILITIES:
682 caps = SVGA_CAP_NONE;
684 caps |= SVGA_CAP_RECT_COPY;
687 caps |= SVGA_CAP_RECT_FILL;
689 #ifdef HW_MOUSE_ACCEL
690 if (s->ds->mouse_set)
691 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
692 SVGA_CAP_CURSOR_BYPASS;
696 case SVGA_REG_MEM_START:
697 return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
699 case SVGA_REG_MEM_SIZE:
700 return SVGA_FIFO_SIZE;
702 case SVGA_REG_CONFIG_DONE:
709 case SVGA_REG_GUEST_ID:
712 case SVGA_REG_CURSOR_ID:
715 case SVGA_REG_CURSOR_X:
718 case SVGA_REG_CURSOR_Y:
721 case SVGA_REG_CURSOR_ON:
724 case SVGA_REG_HOST_BITS_PER_PIXEL:
725 return (s->depth + 7) & ~7;
727 case SVGA_REG_SCRATCH_SIZE:
728 return s->scratch_size;
730 case SVGA_REG_MEM_REGS:
731 case SVGA_REG_NUM_DISPLAYS:
732 case SVGA_REG_PITCHLOCK:
733 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
737 if (s->index >= SVGA_SCRATCH_BASE &&
738 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
739 return s->scratch[s->index - SVGA_SCRATCH_BASE];
740 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
746 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
748 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
751 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
755 case SVGA_REG_ENABLE:
757 s->config &= !!value;
762 s->invalidate(opaque);
765 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
769 s->new_width = value;
773 case SVGA_REG_HEIGHT:
774 s->new_height = value;
779 case SVGA_REG_BITS_PER_PIXEL:
780 if (value != s->depth) {
781 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
786 case SVGA_REG_CONFIG_DONE:
788 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
789 /* Check range and alignment. */
790 if ((s->cmd->min | s->cmd->max |
791 s->cmd->next_cmd | s->cmd->stop) & 3)
793 if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
795 if (s->cmd->max > SVGA_FIFO_SIZE)
797 if (s->cmd->max < s->cmd->min + 10 * 1024)
805 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
808 case SVGA_REG_GUEST_ID:
811 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
812 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
813 printf("%s: guest runs %s.\n", __FUNCTION__,
814 vmsvga_guest_id[value - GUEST_OS_BASE]);
818 case SVGA_REG_CURSOR_ID:
819 s->cursor.id = value;
822 case SVGA_REG_CURSOR_X:
826 case SVGA_REG_CURSOR_Y:
830 case SVGA_REG_CURSOR_ON:
831 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
832 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
833 #ifdef HW_MOUSE_ACCEL
834 if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
835 s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
839 case SVGA_REG_MEM_REGS:
840 case SVGA_REG_NUM_DISPLAYS:
841 case SVGA_REG_PITCHLOCK:
842 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
846 if (s->index >= SVGA_SCRATCH_BASE &&
847 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
848 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
851 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
855 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
857 printf("%s: what are we supposed to return?\n", __FUNCTION__);
861 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
863 printf("%s: what are we supposed to do with (%08x)?\n",
867 static inline void vmsvga_size(struct vmsvga_state_s *s)
869 if (s->new_width != s->width || s->new_height != s->height) {
870 s->width = s->new_width;
871 s->height = s->new_height;
872 dpy_resize(s->ds, s->width, s->height);
877 static void vmsvga_update_display(void *opaque)
879 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
890 vmsvga_update_rect_flush(s);
893 * Is it more efficient to look at vram VGA-dirty bits or wait
894 * for the driver to issue SVGA_CMD_UPDATE?
896 if (s->invalidated) {
898 vmsvga_update_screen(s);
902 static void vmsvga_reset(struct vmsvga_state_s *s)
910 s->depth = s->ds->depth ? s->ds->depth : 24;
911 s->bypp = (s->depth + 7) >> 3;
913 s->redraw_fifo_first = 0;
914 s->redraw_fifo_last = 0;
917 s->wred = 0x00000007;
918 s->wgreen = 0x00000038;
919 s->wblue = 0x000000c0;
922 s->wred = 0x0000001f;
923 s->wgreen = 0x000003e0;
924 s->wblue = 0x00007c00;
927 s->wred = 0x0000001f;
928 s->wgreen = 0x000007e0;
929 s->wblue = 0x0000f800;
932 s->wred = 0x00ff0000;
933 s->wgreen = 0x0000ff00;
934 s->wblue = 0x000000ff;
937 s->wred = 0x00ff0000;
938 s->wgreen = 0x0000ff00;
939 s->wblue = 0x000000ff;
945 static void vmsvga_invalidate_display(void *opaque)
947 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
950 s->invalidate(opaque);
958 /* save the vga display in a PPM image even if no display is
960 static void vmsvga_screen_dump(void *opaque, const char *filename)
962 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
965 s->screen_dump(opaque, filename);
970 if (s->depth == 32) {
971 ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
975 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
977 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
980 s->text_update(opaque, chardata);
984 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
986 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
987 addr -= s->vram_base;
988 if (addr < s->fb_size)
989 return *(uint8_t *) (s->ds->data + addr);
991 return *(uint8_t *) (s->vram + addr);
994 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
996 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
997 addr -= s->vram_base;
998 if (addr < s->fb_size)
999 return *(uint16_t *) (s->ds->data + addr);
1001 return *(uint16_t *) (s->vram + addr);
1004 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1006 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1007 addr -= s->vram_base;
1008 if (addr < s->fb_size)
1009 return *(uint32_t *) (s->ds->data + addr);
1011 return *(uint32_t *) (s->vram + addr);
1014 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1017 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1018 addr -= s->vram_base;
1019 if (addr < s->fb_size)
1020 *(uint8_t *) (s->ds->data + addr) = value;
1022 *(uint8_t *) (s->vram + addr) = value;
1025 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1028 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1029 addr -= s->vram_base;
1030 if (addr < s->fb_size)
1031 *(uint16_t *) (s->ds->data + addr) = value;
1033 *(uint16_t *) (s->vram + addr) = value;
1036 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1039 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1040 addr -= s->vram_base;
1041 if (addr < s->fb_size)
1042 *(uint32_t *) (s->ds->data + addr) = value;
1044 *(uint32_t *) (s->vram + addr) = value;
1047 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1053 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1060 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1062 qemu_put_be32(f, s->depth);
1063 qemu_put_be32(f, s->enable);
1064 qemu_put_be32(f, s->config);
1065 qemu_put_be32(f, s->cursor.id);
1066 qemu_put_be32(f, s->cursor.x);
1067 qemu_put_be32(f, s->cursor.y);
1068 qemu_put_be32(f, s->cursor.on);
1069 qemu_put_be32(f, s->index);
1070 qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1071 qemu_put_be32(f, s->new_width);
1072 qemu_put_be32(f, s->new_height);
1073 qemu_put_be32s(f, &s->guest);
1074 qemu_put_be32s(f, &s->svgaid);
1075 qemu_put_be32(f, s->syncing);
1076 qemu_put_be32(f, s->fb_size);
1079 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1082 depth=qemu_get_be32(f);
1083 s->enable=qemu_get_be32(f);
1084 s->config=qemu_get_be32(f);
1085 s->cursor.id=qemu_get_be32(f);
1086 s->cursor.x=qemu_get_be32(f);
1087 s->cursor.y=qemu_get_be32(f);
1088 s->cursor.on=qemu_get_be32(f);
1089 s->index=qemu_get_be32(f);
1090 qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1091 s->new_width=qemu_get_be32(f);
1092 s->new_height=qemu_get_be32(f);
1093 qemu_get_be32s(f, &s->guest);
1094 qemu_get_be32s(f, &s->svgaid);
1095 s->syncing=qemu_get_be32(f);
1096 s->fb_size=qemu_get_be32(f);
1098 if (s->enable && depth != s->depth) {
1099 printf("%s: need colour depth of %i bits to resume operation.\n",
1100 __FUNCTION__, depth);
1106 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1111 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1112 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1116 s->vram = vga_ram_base;
1117 s->vram_size = vga_ram_size;
1118 s->vram_offset = vga_ram_offset;
1120 s->scratch_size = SVGA_SCRATCH_SIZE;
1121 s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1125 graphic_console_init(ds, vmsvga_update_display,
1126 vmsvga_invalidate_display, vmsvga_screen_dump,
1127 vmsvga_text_update, s);
1130 vga_common_init((VGAState *) s, ds,
1131 vga_ram_base, vga_ram_offset, vga_ram_size);
1132 vga_init((VGAState *) s);
1136 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1138 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1139 pci_device_save(&s->card, f);
1140 vmsvga_save(&s->chip, f);
1143 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1145 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1148 ret = pci_device_load(&s->card, f);
1152 ret = vmsvga_load(&s->chip, f);
1159 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1160 uint32_t addr, uint32_t size, int type)
1162 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1163 struct vmsvga_state_s *s = &d->chip;
1165 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1166 1, 4, vmsvga_index_read, s);
1167 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1168 1, 4, vmsvga_index_write, s);
1169 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1170 1, 4, vmsvga_value_read, s);
1171 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1172 1, 4, vmsvga_value_write, s);
1173 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1174 1, 4, vmsvga_bios_read, s);
1175 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1176 1, 4, vmsvga_bios_write, s);
1179 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1180 uint32_t addr, uint32_t size, int type)
1182 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1183 struct vmsvga_state_s *s = &d->chip;
1186 s->vram_base = addr;
1188 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1189 vmsvga_vram_write, s);
1191 iomemtype = s->vram_offset | IO_MEM_RAM;
1193 cpu_register_physical_memory(s->vram_base, s->vram_size,
1197 #define PCI_VENDOR_ID_VMWARE 0x15ad
1198 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1199 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1200 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
1201 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1202 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1203 #define PCI_CLASS_BASE_DISPLAY 0x03
1204 #define PCI_CLASS_SUB_VGA 0x00
1205 #define PCI_CLASS_HEADERTYPE_00h 0x00
1207 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1208 unsigned long vga_ram_offset, int vga_ram_size)
1210 struct pci_vmsvga_state_s *s;
1212 /* Setup PCI configuration */
1213 s = (struct pci_vmsvga_state_s *)
1214 pci_register_device(bus, "QEMUware SVGA",
1215 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1216 s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1217 s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1218 s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1219 s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1220 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1221 s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
1222 s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
1223 s->card.config[0x0c] = 0x08; /* Cache line size */
1224 s->card.config[0x0d] = 0x40; /* Latency timer */
1225 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
1226 s->card.config[0x10] = ((SVGA_IO_BASE >> 0) & 0xff) | 1;
1227 s->card.config[0x11] = (SVGA_IO_BASE >> 8) & 0xff;
1228 s->card.config[0x12] = (SVGA_IO_BASE >> 16) & 0xff;
1229 s->card.config[0x13] = (SVGA_IO_BASE >> 24) & 0xff;
1230 s->card.config[0x18] = (SVGA_MEM_BASE >> 0) & 0xff;
1231 s->card.config[0x19] = (SVGA_MEM_BASE >> 8) & 0xff;
1232 s->card.config[0x1a] = (SVGA_MEM_BASE >> 16) & 0xff;
1233 s->card.config[0x1b] = (SVGA_MEM_BASE >> 24) & 0xff;
1234 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1235 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1236 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1237 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1238 s->card.config[0x3c] = 0xff; /* End */
1240 pci_register_io_region(&s->card, 0, 0x10,
1241 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1242 pci_register_io_region(&s->card, 1, vga_ram_size,
1243 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1245 vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1247 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);