2 * ARM Versatile Platform Baseboard System emulation.
4 * Copyright (c) 2005-2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
13 #define KERNEL_ARGS_ADDR 0x100
14 #define KERNEL_LOAD_ADDR 0x00010000
15 #define INITRD_LOAD_ADDR 0x00800000
17 /* Primary interrupt controller. */
19 typedef struct vpb_sic_state
21 arm_pic_handler handler;
30 static void vpb_sic_update(vpb_sic_state *s)
34 flags = s->level & s->mask;
35 pic_set_irq_new(s->parent, s->irq, flags != 0);
38 static void vpb_sic_update_pic(vpb_sic_state *s)
43 for (i = 21; i <= 30; i++) {
45 if (!(s->pic_enable & mask))
47 pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
51 static void vpb_sic_set_irq(void *opaque, int irq, int level)
53 vpb_sic_state *s = (vpb_sic_state *)opaque;
55 s->level |= 1u << irq;
57 s->level &= ~(1u << irq);
58 if (s->pic_enable & (1u << irq))
59 pic_set_irq_new(s->parent, irq, level);
63 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
65 vpb_sic_state *s = (vpb_sic_state *)opaque;
68 switch (offset >> 2) {
70 return s->level & s->mask;
77 case 8: /* PICENABLE */
80 printf ("vpb_sic_read: Bad register offset 0x%x\n", offset);
85 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
88 vpb_sic_state *s = (vpb_sic_state *)opaque;
91 switch (offset >> 2) {
98 case 4: /* SOFTINTSET */
102 case 5: /* SOFTINTCLR */
106 case 8: /* PICENSET */
107 s->pic_enable |= (value & 0x7fe00000);
108 vpb_sic_update_pic(s);
110 case 9: /* PICENCLR */
111 s->pic_enable &= ~value;
112 vpb_sic_update_pic(s);
115 printf ("vpb_sic_write: Bad register offset 0x%x\n", offset);
121 static CPUReadMemoryFunc *vpb_sic_readfn[] = {
127 static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
133 static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
138 s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
141 s->handler = vpb_sic_set_irq;
145 iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
147 cpu_register_physical_memory(base, 0x00000fff, iomemtype);
148 /* ??? Save/restore. */
154 /* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
155 static uint32_t bootloader[] = {
156 0xe3a00000, /* mov r0, #0 */
157 0xe3a01083, /* mov r1, #0x83 */
158 0xe3811c01, /* orr r1, r1, #0x100 */
159 0xe59f2000, /* ldr r2, [pc, #0] */
160 0xe59ff000, /* ldr pc, [pc, #0] */
161 0, /* Address of kernel args. Set by integratorcp_init. */
162 0 /* Kernel entry point. Set by integratorcp_init. */
165 static void set_kernel_args(uint32_t ram_size, int initrd_size,
166 const char *kernel_cmdline)
170 p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
173 stl_raw(p++, 0x54410001);
175 stl_raw(p++, 0x1000);
179 stl_raw(p++, 0x54410002);
180 stl_raw(p++, ram_size);
185 stl_raw(p++, 0x54420005);
186 stl_raw(p++, INITRD_LOAD_ADDR);
187 stl_raw(p++, initrd_size);
189 if (kernel_cmdline && *kernel_cmdline) {
193 cmdline_size = strlen(kernel_cmdline);
194 memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
195 cmdline_size = (cmdline_size >> 2) + 1;
196 stl_raw(p++, cmdline_size + 2);
197 stl_raw(p++, 0x54410009);
205 static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
206 DisplayState *ds, const char **fd_filename, int snapshot,
207 const char *kernel_filename, const char *kernel_cmdline,
208 const char *initrd_filename)
218 cpu_arm_set_model(env, ARM_CPUID_ARM926);
219 /* ??? RAM shoud repeat to fill physical memory space. */
220 /* SDRAM at address zero. */
221 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
223 pic = arm_pic_init_cpu(env);
224 pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
225 sic = vpb_sic_init(0x10003000, pic, 31);
226 pl050_init(0x10006000, sic, 3, 0);
227 pl050_init(0x10007000, sic, 4, 1);
229 /* TODO: Init PCI NICs. */
230 if (nd_table[0].vlan) {
231 if (nd_table[0].model == NULL
232 || strcmp(nd_table[0].model, "smc91c111") == 0) {
233 smc91c111_init(&nd_table[0], 0x10010000, sic, 25);
235 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
240 pl011_init(0x101f1000, pic, 12, serial_hds[0]);
241 pl011_init(0x101f2000, pic, 13, serial_hds[1]);
242 pl011_init(0x101f3000, pic, 14, serial_hds[2]);
243 pl011_init(0x10009000, sic, 6, serial_hds[3]);
245 pl080_init(0x10130000, pic, 17);
246 sp804_init(0x101e2000, pic, 4);
247 sp804_init(0x101e3000, pic, 5);
249 /* The versatile/PB actually has a modified Color LCD controller
250 that includes hardware cursor support from the PL111. */
251 pl110_init(ds, 0x10120000, pic, 16, 1);
253 /* 0x10000000 System registers. */
254 /* 0x10001000 PCI controller config registers. */
255 /* 0x10002000 Serial bus interface. */
256 /* 0x10003000 Secondary interrupt controller. */
257 /* 0x10004000 AACI (audio). */
258 /* 0x10005000 MMCI0. */
259 /* 0x10006000 KMI0 (keyboard). */
260 /* 0x10007000 KMI1 (mouse). */
261 /* 0x10008000 Character LCD Interface. */
262 /* 0x10009000 UART3. */
263 /* 0x1000a000 Smart card 1. */
264 /* 0x1000b000 MMCI1. */
265 /* 0x10010000 Ethernet. */
266 /* 0x10020000 USB. */
267 /* 0x10100000 SSMC. */
268 /* 0x10110000 MPMC. */
269 /* 0x10120000 CLCD Controller. */
270 /* 0x10130000 DMA Controller. */
271 /* 0x10140000 Vectored interrupt controller. */
272 /* 0x101d0000 AHB Monitor Interface. */
273 /* 0x101e0000 System Controller. */
274 /* 0x101e1000 Watchdog Interface. */
275 /* 0x101e2000 Timer 0/1. */
276 /* 0x101e3000 Timer 2/3. */
277 /* 0x101e4000 GPIO port 0. */
278 /* 0x101e5000 GPIO port 1. */
279 /* 0x101e6000 GPIO port 2. */
280 /* 0x101e7000 GPIO port 3. */
281 /* 0x101e8000 RTC. */
282 /* 0x101f0000 Smart card 0. */
283 /* 0x101f1000 UART0. */
284 /* 0x101f2000 UART1. */
285 /* 0x101f3000 UART2. */
286 /* 0x101f4000 SSPI. */
288 /* Load the kernel. */
289 if (!kernel_filename) {
290 fprintf(stderr, "Kernel image must be specified\n");
293 kernel_size = load_image(kernel_filename,
294 phys_ram_base + KERNEL_LOAD_ADDR);
295 if (kernel_size < 0) {
296 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
299 if (initrd_filename) {
300 initrd_size = load_image(initrd_filename,
301 phys_ram_base + INITRD_LOAD_ADDR);
302 if (initrd_size < 0) {
303 fprintf(stderr, "qemu: could not load initrd '%s'\n",
310 bootloader[5] = KERNEL_ARGS_ADDR;
311 bootloader[6] = KERNEL_LOAD_ADDR;
312 for (n = 0; n < sizeof(bootloader) / 4; n++)
313 stl_raw(phys_ram_base + (n * 4), bootloader[n]);
314 set_kernel_args(ram_size, initrd_size, kernel_cmdline);
317 QEMUMachine versatilepb_machine = {
319 "ARM Versatile/PB (ARM926EJ-S)",