2 * QEMU Sparc timer controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Registers of hardware timer in sun4m.
29 struct sun4m_timer_percpu {
30 volatile unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
31 volatile unsigned int l14_cur_count;
34 struct sun4m_timer_global {
35 volatile unsigned int l10_timer_limit;
36 volatile unsigned int l10_cur_count;
39 typedef struct TIMERState {
41 uint32_t timer_regs[2];
45 static uint32_t timer_mem_readl(void *opaque, target_phys_addr_t addr)
47 TIMERState *s = opaque;
50 saddr = (addr - s->addr) >> 2;
53 return s->timer_regs[saddr];
59 static void timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
61 TIMERState *s = opaque;
64 saddr = (addr - s->addr) >> 2;
67 s->timer_regs[saddr] = val;
72 static CPUReadMemoryFunc *timer_mem_read[3] = {
78 static CPUWriteMemoryFunc *timer_mem_write[3] = {
84 void timer_init(uint32_t addr, int irq)
89 s = qemu_mallocz(sizeof(TIMERState));
95 timer_io_memory = cpu_register_io_memory(0, timer_mem_read, timer_mem_write, s);
96 cpu_register_physical_memory(addr, 2, timer_io_memory);