2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #define TCX_DAC_NREGS 16
29 #define TCX_THC_NREGS_8 0x081c
30 #define TCX_THC_NREGS_24 0x1000
31 #define TCX_TEC_NREGS 0x1000
33 typedef struct TCXState {
34 target_phys_addr_t addr;
37 uint32_t *vram24, *cplane;
38 ram_addr_t vram_offset, vram24_offset, cplane_offset;
39 uint16_t width, height, depth;
40 uint8_t r[256], g[256], b[256];
41 uint32_t palette[256];
42 uint8_t dac_index, dac_state;
45 static void tcx_screen_dump(void *opaque, const char *filename);
46 static void tcx24_screen_dump(void *opaque, const char *filename);
48 /* XXX: unify with vga draw line functions */
49 static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
51 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
54 static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
56 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
59 static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
61 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
64 static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
66 return (r << 16) | (g << 8) | b;
69 static void update_palette_entries(TCXState *s, int start, int end)
72 for(i = start; i < end; i++) {
73 switch(s->ds->depth) {
76 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
79 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
82 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
85 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
91 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
92 const uint8_t *s, int width)
96 uint32_t *p = (uint32_t *)d;
98 for(x = 0; x < width; x++) {
100 *p++ = s1->palette[val];
104 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
105 const uint8_t *s, int width)
109 uint16_t *p = (uint16_t *)d;
111 for(x = 0; x < width; x++) {
113 *p++ = s1->palette[val];
117 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
118 const uint8_t *s, int width)
123 for(x = 0; x < width; x++) {
125 *d++ = s1->palette[val];
129 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
130 const uint8_t *s, int width,
131 const uint32_t *cplane,
136 uint32_t *p = (uint32_t *)d;
139 for(x = 0; x < width; x++, s++, s24++) {
140 if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct
141 dval = bswap32(*s24) & 0x00ffffff;
144 dval = s1->palette[val];
150 static inline int check_dirty(TCXState *ts, ram_addr_t page, ram_addr_t page24,
156 ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
157 for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
158 ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
159 ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
164 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
165 ram_addr_t page_max, ram_addr_t page24,
168 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
170 page_min -= ts->vram_offset;
171 page_max -= ts->vram_offset;
172 cpu_physical_memory_reset_dirty(page24 + page_min * 4,
173 page24 + page_max * 4 + TARGET_PAGE_SIZE,
175 cpu_physical_memory_reset_dirty(cpage + page_min * 4,
176 cpage + page_max * 4 + TARGET_PAGE_SIZE,
180 /* Fixed line length 1024 allows us to do nice tricks not possible on
182 static void tcx_update_display(void *opaque)
184 TCXState *ts = opaque;
185 ram_addr_t page, page_min, page_max;
186 int y, y_start, dd, ds;
188 void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width);
190 if (ts->ds->depth == 0)
192 page = ts->vram_offset;
194 page_min = 0xffffffff;
198 dd = ts->ds->linesize;
201 switch (ts->ds->depth) {
217 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
218 if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
225 f(ts, d, s, ts->width);
228 f(ts, d, s, ts->width);
231 f(ts, d, s, ts->width);
234 f(ts, d, s, ts->width);
239 /* flush to display */
240 dpy_update(ts->ds, 0, y_start,
241 ts->width, y - y_start);
249 /* flush to display */
250 dpy_update(ts->ds, 0, y_start,
251 ts->width, y - y_start);
253 /* reset modified pages */
254 if (page_min <= page_max) {
255 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
260 static void tcx24_update_display(void *opaque)
262 TCXState *ts = opaque;
263 ram_addr_t page, page_min, page_max, cpage, page24;
264 int y, y_start, dd, ds;
266 uint32_t *cptr, *s24;
268 if (ts->ds->depth != 32)
270 page = ts->vram_offset;
271 page24 = ts->vram24_offset;
272 cpage = ts->cplane_offset;
274 page_min = 0xffffffff;
280 dd = ts->ds->linesize;
283 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
284 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
285 if (check_dirty(ts, page, page24, cpage)) {
292 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
297 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
302 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
307 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
314 /* flush to display */
315 dpy_update(ts->ds, 0, y_start,
316 ts->width, y - y_start);
326 /* flush to display */
327 dpy_update(ts->ds, 0, y_start,
328 ts->width, y - y_start);
330 /* reset modified pages */
331 if (page_min <= page_max) {
332 reset_dirty(ts, page_min, page_max, page24, cpage);
336 static void tcx_invalidate_display(void *opaque)
338 TCXState *s = opaque;
341 for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
342 cpu_physical_memory_set_dirty(s->vram_offset + i);
346 static void tcx24_invalidate_display(void *opaque)
348 TCXState *s = opaque;
351 tcx_invalidate_display(s);
352 for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
353 cpu_physical_memory_set_dirty(s->vram24_offset + i);
354 cpu_physical_memory_set_dirty(s->cplane_offset + i);
358 static void tcx_save(QEMUFile *f, void *opaque)
360 TCXState *s = opaque;
362 qemu_put_be32s(f, (uint32_t *)&s->vram);
363 qemu_put_be32s(f, (uint32_t *)&s->vram24);
364 qemu_put_be32s(f, (uint32_t *)&s->cplane);
365 qemu_put_be16s(f, (uint16_t *)&s->height);
366 qemu_put_be16s(f, (uint16_t *)&s->width);
367 qemu_put_be16s(f, (uint16_t *)&s->depth);
368 qemu_put_buffer(f, s->r, 256);
369 qemu_put_buffer(f, s->g, 256);
370 qemu_put_buffer(f, s->b, 256);
371 qemu_put_8s(f, &s->dac_index);
372 qemu_put_8s(f, &s->dac_state);
375 static int tcx_load(QEMUFile *f, void *opaque, int version_id)
377 TCXState *s = opaque;
382 qemu_get_be32s(f, (uint32_t *)&s->vram);
383 qemu_get_be32s(f, (uint32_t *)&s->vram24);
384 qemu_get_be32s(f, (uint32_t *)&s->cplane);
385 qemu_get_be16s(f, (uint16_t *)&s->height);
386 qemu_get_be16s(f, (uint16_t *)&s->width);
387 qemu_get_be16s(f, (uint16_t *)&s->depth);
388 qemu_get_buffer(f, s->r, 256);
389 qemu_get_buffer(f, s->g, 256);
390 qemu_get_buffer(f, s->b, 256);
391 qemu_get_8s(f, &s->dac_index);
392 qemu_get_8s(f, &s->dac_state);
393 update_palette_entries(s, 0, 256);
394 tcx_invalidate_display(s);
399 static void tcx_reset(void *opaque)
401 TCXState *s = opaque;
403 /* Initialize palette */
404 memset(s->r, 0, 256);
405 memset(s->g, 0, 256);
406 memset(s->b, 0, 256);
407 s->r[255] = s->g[255] = s->b[255] = 255;
408 update_palette_entries(s, 0, 256);
409 memset(s->vram, 0, MAXX*MAXY);
410 cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
411 MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
416 static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
421 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
423 TCXState *s = opaque;
426 saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
429 s->dac_index = val >> 24;
433 switch (s->dac_state) {
435 s->r[s->dac_index] = val >> 24;
436 update_palette_entries(s, s->dac_index, s->dac_index + 1);
440 s->g[s->dac_index] = val >> 24;
441 update_palette_entries(s, s->dac_index, s->dac_index + 1);
445 s->b[s->dac_index] = val >> 24;
446 update_palette_entries(s, s->dac_index, s->dac_index + 1);
447 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
459 static CPUReadMemoryFunc *tcx_dac_read[3] = {
465 static CPUWriteMemoryFunc *tcx_dac_write[3] = {
471 static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
476 static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
481 static CPUReadMemoryFunc *tcx_dummy_read[3] = {
487 static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
493 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
494 unsigned long vram_offset, int vram_size, int width, int height,
498 int io_memory, dummy_memory;
501 s = qemu_mallocz(sizeof(TCXState));
506 s->vram_offset = vram_offset;
514 cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
518 io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
519 cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);
521 dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
523 cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
527 size = vram_size * 4;
528 s->vram24 = (uint32_t *)vram_base;
529 s->vram24_offset = vram_offset;
530 cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
535 size = vram_size * 4;
536 s->cplane = (uint32_t *)vram_base;
537 s->cplane_offset = vram_offset;
538 cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
539 graphic_console_init(s->ds, tcx24_update_display,
540 tcx24_invalidate_display, tcx24_screen_dump, s);
542 cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
544 graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
547 // NetBSD writes here even with 8-bit display
548 cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
551 register_savevm("tcx", addr, 3, tcx_save, tcx_load, s);
552 qemu_register_reset(tcx_reset, s);
554 dpy_resize(s->ds, width, height);
557 static void tcx_screen_dump(void *opaque, const char *filename)
559 TCXState *s = opaque;
564 f = fopen(filename, "wb");
567 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
569 for(y = 0; y < s->height; y++) {
571 for(x = 0; x < s->width; x++) {
584 static void tcx24_screen_dump(void *opaque, const char *filename)
586 TCXState *s = opaque;
589 uint32_t *s24, *cptr, dval;
592 f = fopen(filename, "wb");
595 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
599 for(y = 0; y < s->height; y++) {
601 for(x = 0; x < s->width; x++, d++, s24++) {
602 if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
603 dval = *s24 & 0x00ffffff;
604 fputc((dval >> 16) & 0xff, f);
605 fputc((dval >> 8) & 0xff, f);
606 fputc(dval & 0xff, f);