2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #define KERNEL_LOAD_ADDR 0x00004000
28 #define PROM_ADDR 0xffd00000
29 #define PROM_FILENAMEB "proll.bin"
30 #define PROM_FILENAMEE "proll.elf"
31 #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
32 #define PHYS_JJ_IDPROM_OFF 0x1FD8
33 #define PHYS_JJ_EEPROM_SIZE 0x2000
34 // IRQs are not PIL ones, but master interrupt controller register
36 #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
37 #define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */
38 #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */
39 #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
40 #define PHYS_JJ_LE_IRQ 16
41 #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
42 #define PHYS_JJ_CLOCK_IRQ 7
43 #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
44 #define PHYS_JJ_CLOCK1_IRQ 19
45 #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
46 #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
47 #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
48 #define PHYS_JJ_MS_KBD_IRQ 14
49 #define PHYS_JJ_SER 0x71100000 /* Serial */
50 #define PHYS_JJ_SER_IRQ 15
51 #define PHYS_JJ_SCSI_IRQ 18
52 #define PHYS_JJ_FDC 0x71400000 /* Floppy */
53 #define PHYS_JJ_FLOPPY_IRQ 22
57 uint64_t cpu_get_tsc()
59 return qemu_get_clock(vm_clock);
64 static m48t08_t *nvram;
66 static void nvram_init(m48t08_t *nvram, uint8_t *macaddr)
68 unsigned char tmp = 0;
72 m48t08_write(nvram, i++, 0x01);
73 m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
75 m48t08_write(nvram, i++, macaddr[j++]);
76 m48t08_write(nvram, i++, macaddr[j++]);
77 m48t08_write(nvram, i++, macaddr[j++]);
78 m48t08_write(nvram, i++, macaddr[j++]);
79 m48t08_write(nvram, i++, macaddr[j++]);
80 m48t08_write(nvram, i, macaddr[j]);
82 /* Calculate checksum */
83 for (i = 0x1fd8; i < 0x1fe7; i++) {
84 tmp ^= m48t08_read(nvram, i);
86 m48t08_write(nvram, 0x1fe7, tmp);
89 static void *slavio_intctl;
93 slavio_pic_info(slavio_intctl);
98 slavio_irq_info(slavio_intctl);
101 void pic_set_irq(int irq, int level)
103 slavio_pic_set_irq(slavio_intctl, irq, level);
108 void vga_update_display()
110 tcx_update_display(tcx);
113 void vga_invalidate_display()
115 tcx_invalidate_display(tcx);
118 void vga_screen_dump(const char *filename)
120 tcx_screen_dump(tcx, filename);
125 uint32_t iommu_translate(uint32_t addr)
127 return iommu_translate_local(iommu, addr);
130 /* Sun4m hardware initialisation */
131 void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
132 DisplayState *ds, const char **fd_filename, int snapshot,
133 const char *kernel_filename, const char *kernel_cmdline,
134 const char *initrd_filename)
138 unsigned long vram_size = 0x100000, prom_offset;
140 linux_boot = (kernel_filename != NULL);
143 cpu_register_physical_memory(0, ram_size, 0);
145 iommu = iommu_init(PHYS_JJ_IOMMU);
146 slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
147 tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size);
148 lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
149 nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
150 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr);
151 slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
152 slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
153 slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]);
154 fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
156 prom_offset = ram_size + vram_size;
158 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
159 ret = load_elf(buf, phys_ram_base + prom_offset);
161 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
162 ret = load_image(buf, phys_ram_base + prom_offset);
165 fprintf(stderr, "qemu: could not load prom '%s'\n",
169 cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
170 prom_offset | IO_MEM_ROM);
173 ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
175 ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
177 ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
179 fprintf(stderr, "qemu: could not load kernel '%s'\n",