2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Sun4m architecture was used in the following machines:
29 * SPARCserver 6xxMP/xx
30 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
31 * SPARCstation LX/ZX (4/30)
32 * SPARCstation Voyager
33 * SPARCstation 10/xx, SPARCserver 10/xx
34 * SPARCstation 5, SPARCserver 5
35 * SPARCstation 20/xx, SPARCserver 20
38 * See for example: http://www.sunhelp.org/faq/sunref1.html
41 #define KERNEL_LOAD_ADDR 0x00004000
42 #define CMDLINE_ADDR 0x007ff000
43 #define INITRD_LOAD_ADDR 0x00800000
44 #define PROM_SIZE_MAX (256 * 1024)
45 #define PROM_ADDR 0xffd00000
46 #define PROM_FILENAME "openbios-sparc32"
51 target_ulong iommu_base, slavio_base;
52 target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
54 target_ulong dma_base, esp_base, le_base;
55 target_ulong tcx_base, cs_base;
56 long vram_size, nvram_size;
57 // IRQ numbers are not PIL ones, but master interrupt controller register
59 int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
60 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
61 int machine_id; // For NVRAM
62 uint32_t intbit_to_level[32];
67 uint64_t cpu_get_tsc()
69 return qemu_get_clock(vm_clock);
72 int DMA_get_channel_mode (int nchan)
76 int DMA_read_memory (int nchan, void *buf, int pos, int size)
80 int DMA_write_memory (int nchan, void *buf, int pos, int size)
84 void DMA_hold_DREQ (int nchan) {}
85 void DMA_release_DREQ (int nchan) {}
86 void DMA_schedule(int nchan) {}
87 void DMA_run (void) {}
88 void DMA_init (int high_page_enable) {}
89 void DMA_register_channel (int nchan,
90 DMA_transfer_handler transfer_handler,
95 static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
97 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
98 m48t59_write(nvram, addr++, value & 0xff);
101 static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
103 m48t59_write(nvram, addr++, value >> 24);
104 m48t59_write(nvram, addr++, (value >> 16) & 0xff);
105 m48t59_write(nvram, addr++, (value >> 8) & 0xff);
106 m48t59_write(nvram, addr++, value & 0xff);
109 static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
110 const unsigned char *str, uint32_t max)
114 for (i = 0; i < max && str[i] != '\0'; i++) {
115 m48t59_write(nvram, addr + i, str[i]);
117 m48t59_write(nvram, addr + max - 1, '\0');
120 static m48t59_t *nvram;
122 extern int nographic;
124 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
125 int boot_device, uint32_t RAM_size,
126 uint32_t kernel_size,
127 int width, int height, int depth,
130 unsigned char tmp = 0;
133 // Try to match PPC NVRAM
134 nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
135 nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
136 // NVRAM_size, arch not applicable
137 m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
138 m48t59_write(nvram, 0x2E, 0);
139 m48t59_write(nvram, 0x2F, nographic & 0xff);
140 nvram_set_lword(nvram, 0x30, RAM_size);
141 m48t59_write(nvram, 0x34, boot_device & 0xff);
142 nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
143 nvram_set_lword(nvram, 0x3C, kernel_size);
145 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
146 nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
147 nvram_set_lword(nvram, 0x44, strlen(cmdline));
149 // initrd_image, initrd_size passed differently
150 nvram_set_word(nvram, 0x54, width);
151 nvram_set_word(nvram, 0x56, height);
152 nvram_set_word(nvram, 0x58, depth);
154 // Sun4m specific use
156 m48t59_write(nvram, i++, 0x01);
157 m48t59_write(nvram, i++, machine_id);
159 m48t59_write(nvram, i++, macaddr[j++]);
160 m48t59_write(nvram, i++, macaddr[j++]);
161 m48t59_write(nvram, i++, macaddr[j++]);
162 m48t59_write(nvram, i++, macaddr[j++]);
163 m48t59_write(nvram, i++, macaddr[j++]);
164 m48t59_write(nvram, i, macaddr[j]);
166 /* Calculate checksum */
167 for (i = 0x1fd8; i < 0x1fe7; i++) {
168 tmp ^= m48t59_read(nvram, i);
170 m48t59_write(nvram, 0x1fe7, tmp);
173 static void *slavio_intctl;
177 slavio_pic_info(slavio_intctl);
182 slavio_irq_info(slavio_intctl);
185 void pic_set_irq(int irq, int level)
187 slavio_pic_set_irq(slavio_intctl, irq, level);
190 void pic_set_irq_new(void *opaque, int irq, int level)
192 pic_set_irq(irq, level);
195 void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
197 slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
200 static void *slavio_misc;
202 void qemu_system_powerdown(void)
204 slavio_set_power_fail(slavio_misc, 1);
207 static void main_cpu_reset(void *opaque)
209 CPUState *env = opaque;
213 static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
214 DisplayState *ds, const char *cpu_model)
217 CPUState *env, *envs[MAX_CPUS];
219 void *iommu, *dma, *main_esp, *main_lance = NULL;
220 const sparc_def_t *def;
223 sparc_find_by_name(cpu_model, &def);
225 fprintf(stderr, "Unable to find Sparc CPU definition\n");
228 for(i = 0; i < smp_cpus; i++) {
230 cpu_sparc_register(env, def);
234 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
235 qemu_register_reset(main_cpu_reset, env);
238 cpu_register_physical_memory(0, ram_size, 0);
240 iommu = iommu_init(hwdef->iommu_base);
241 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
242 hwdef->intctl_base + 0x10000,
243 &hwdef->intbit_to_level[0]);
244 for(i = 0; i < smp_cpus; i++) {
245 slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
247 dma = sparc32_dma_init(hwdef->dma_base, hwdef->esp_irq,
248 hwdef->le_irq, iommu, slavio_intctl);
250 tcx_init(ds, hwdef->tcx_base, phys_ram_base + ram_size, ram_size,
251 hwdef->vram_size, graphic_width, graphic_height);
252 if (nd_table[0].vlan) {
253 if (nd_table[0].model == NULL
254 || strcmp(nd_table[0].model, "lance") == 0) {
255 main_lance = lance_init(&nd_table[0], hwdef->le_base, dma);
257 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
261 nvram = m48t59_init(0, hwdef->nvram_base, 0, hwdef->nvram_size, 8);
262 for (i = 0; i < MAX_CPUS; i++) {
263 slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE,
264 hwdef->clock_irq, 0, i);
266 slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2,
268 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, hwdef->ms_kb_irq);
269 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
270 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
271 slavio_serial_init(hwdef->serial_base, hwdef->ser_irq,
272 serial_hds[1], serial_hds[0]);
273 fdctrl_init(hwdef->fd_irq, 0, 1, hwdef->fd_base, fd_table);
274 main_esp = esp_init(bs_table, hwdef->esp_base, dma);
276 for (i = 0; i < MAX_DISKS; i++) {
278 esp_scsi_attach(main_esp, bs_table[i], i);
282 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->me_irq);
283 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
284 sparc32_dma_set_reset_data(dma, main_esp, main_lance);
287 static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,
288 const char *kernel_filename,
289 const char *kernel_cmdline,
290 const char *initrd_filename,
296 long prom_offset, initrd_size, kernel_size;
298 linux_boot = (kernel_filename != NULL);
300 prom_offset = ram_size + vram_size;
301 cpu_register_physical_memory(PROM_ADDR,
302 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
303 prom_offset | IO_MEM_ROM);
305 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
306 ret = load_elf(buf, 0, NULL);
308 fprintf(stderr, "qemu: could not load prom '%s'\n",
315 kernel_size = load_elf(kernel_filename, -0xf0000000, NULL);
317 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
319 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
320 if (kernel_size < 0) {
321 fprintf(stderr, "qemu: could not load kernel '%s'\n",
328 if (initrd_filename) {
329 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
330 if (initrd_size < 0) {
331 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
336 if (initrd_size > 0) {
337 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
338 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
339 == 0x48647253) { // HdrS
340 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
341 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
347 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
348 boot_device, ram_size, kernel_size, graphic_width,
349 graphic_height, graphic_depth, machine_id);
352 static const struct hwdef hwdefs[] = {
355 .iommu_base = 0x10000000,
356 .tcx_base = 0x50000000,
357 .cs_base = 0x6c000000,
358 .slavio_base = 0x71000000,
359 .ms_kb_base = 0x71000000,
360 .serial_base = 0x71100000,
361 .nvram_base = 0x71200000,
362 .fd_base = 0x71400000,
363 .counter_base = 0x71d00000,
364 .intctl_base = 0x71e00000,
365 .dma_base = 0x78400000,
366 .esp_base = 0x78800000,
367 .le_base = 0x78c00000,
368 .vram_size = 0x00100000,
369 .nvram_size = 0x2000,
381 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
382 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
386 /* XXX: Replace with real values */
388 .iommu_base = 0x10000000,
389 .tcx_base = 0x50000000,
390 .cs_base = 0x6c000000,
391 .slavio_base = 0x71000000,
392 .ms_kb_base = 0x71000000,
393 .serial_base = 0x71100000,
394 .nvram_base = 0x71200000,
395 .fd_base = 0x71400000,
396 .counter_base = 0x71d00000,
397 .intctl_base = 0x71e00000,
398 .dma_base = 0x78400000,
399 .esp_base = 0x78800000,
400 .le_base = 0x78c00000,
401 .vram_size = 0x00100000,
402 .nvram_size = 0x2000,
414 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
415 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
420 static void sun4m_common_init(int ram_size, int boot_device, DisplayState *ds,
421 const char *kernel_filename, const char *kernel_cmdline,
422 const char *initrd_filename, const char *cpu_model,
423 unsigned int machine)
425 sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);
427 sun4m_load_kernel(hwdefs[machine].vram_size, ram_size, boot_device,
428 kernel_filename, kernel_cmdline, initrd_filename,
429 hwdefs[machine].machine_id);
432 /* SPARCstation 5 hardware initialisation */
433 static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
434 DisplayState *ds, const char **fd_filename, int snapshot,
435 const char *kernel_filename, const char *kernel_cmdline,
436 const char *initrd_filename, const char *cpu_model)
438 if (cpu_model == NULL)
439 cpu_model = "Fujitsu MB86904";
440 sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
441 kernel_cmdline, initrd_filename, cpu_model,
445 /* SPARCstation 10 hardware initialisation */
446 static void ss10_init(int ram_size, int vga_ram_size, int boot_device,
447 DisplayState *ds, const char **fd_filename, int snapshot,
448 const char *kernel_filename, const char *kernel_cmdline,
449 const char *initrd_filename, const char *cpu_model)
451 if (cpu_model == NULL)
452 cpu_model = "TI SuperSparc II";
453 sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
454 kernel_cmdline, initrd_filename, cpu_model,
458 QEMUMachine ss5_machine = {
460 "Sun4m platform, SPARCstation 5",
464 QEMUMachine ss10_machine = {
466 "Sun4m platform, SPARCstation 10",