2 * QEMU Sun4m System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #define KERNEL_LOAD_ADDR 0x00004000
28 #define CMDLINE_ADDR 0x007ff000
29 #define INITRD_LOAD_ADDR 0x00800000
30 #define PROM_ADDR 0xffd00000
31 #define PROM_FILENAMEB "proll.bin"
32 #define PROM_FILENAMEE "proll.elf"
33 #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
34 #define PHYS_JJ_IDPROM_OFF 0x1FD8
35 #define PHYS_JJ_EEPROM_SIZE 0x2000
36 // IRQs are not PIL ones, but master interrupt controller register
38 #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
39 #define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */
40 #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */
41 #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
42 #define PHYS_JJ_LE_IRQ 16
43 #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
44 #define PHYS_JJ_CLOCK_IRQ 7
45 #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
46 #define PHYS_JJ_CLOCK1_IRQ 19
47 #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
48 #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
49 #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
50 #define PHYS_JJ_MS_KBD_IRQ 14
51 #define PHYS_JJ_SER 0x71100000 /* Serial */
52 #define PHYS_JJ_SER_IRQ 15
53 #define PHYS_JJ_SCSI_IRQ 18
54 #define PHYS_JJ_FDC 0x71400000 /* Floppy */
55 #define PHYS_JJ_FLOPPY_IRQ 22
59 uint64_t cpu_get_tsc()
61 return qemu_get_clock(vm_clock);
66 static m48t08_t *nvram;
68 static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline)
70 unsigned char tmp = 0;
77 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
78 m48t08_write(nvram, i++, CMDLINE_ADDR >> 24);
79 m48t08_write(nvram, i++, (CMDLINE_ADDR >> 16) & 0xff);
80 m48t08_write(nvram, i++, (CMDLINE_ADDR >> 8) & 0xff);
81 m48t08_write(nvram, i++, CMDLINE_ADDR & 0xff);
83 cmdline_len = strlen(cmdline);
84 m48t08_write(nvram, i++, cmdline_len >> 24);
85 m48t08_write(nvram, i++, (cmdline_len >> 16) & 0xff);
86 m48t08_write(nvram, i++, (cmdline_len >> 8) & 0xff);
87 m48t08_write(nvram, i++, cmdline_len & 0xff);
91 m48t08_write(nvram, i++, 0x01);
92 m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
94 m48t08_write(nvram, i++, macaddr[j++]);
95 m48t08_write(nvram, i++, macaddr[j++]);
96 m48t08_write(nvram, i++, macaddr[j++]);
97 m48t08_write(nvram, i++, macaddr[j++]);
98 m48t08_write(nvram, i++, macaddr[j++]);
99 m48t08_write(nvram, i, macaddr[j]);
101 /* Calculate checksum */
102 for (i = 0x1fd8; i < 0x1fe7; i++) {
103 tmp ^= m48t08_read(nvram, i);
105 m48t08_write(nvram, 0x1fe7, tmp);
108 static void *slavio_intctl;
112 slavio_pic_info(slavio_intctl);
117 slavio_irq_info(slavio_intctl);
120 void pic_set_irq(int irq, int level)
122 slavio_pic_set_irq(slavio_intctl, irq, level);
127 void vga_update_display()
129 tcx_update_display(tcx);
132 void vga_invalidate_display()
134 tcx_invalidate_display(tcx);
137 void vga_screen_dump(const char *filename)
139 tcx_screen_dump(tcx, filename);
144 uint32_t iommu_translate(uint32_t addr)
146 return iommu_translate_local(iommu, addr);
149 /* Sun4m hardware initialisation */
150 void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
151 DisplayState *ds, const char **fd_filename, int snapshot,
152 const char *kernel_filename, const char *kernel_cmdline,
153 const char *initrd_filename)
158 unsigned long vram_size = 0x100000, prom_offset, initrd_size;
160 linux_boot = (kernel_filename != NULL);
163 cpu_register_physical_memory(0, ram_size, 0);
165 iommu = iommu_init(PHYS_JJ_IOMMU);
166 slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
167 tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size);
168 lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
169 nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
170 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline);
171 slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
172 slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
173 slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]);
174 fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
176 prom_offset = ram_size + vram_size;
178 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
179 ret = load_elf(buf, phys_ram_base + prom_offset);
181 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
182 ret = load_image(buf, phys_ram_base + prom_offset);
185 fprintf(stderr, "qemu: could not load prom '%s'\n",
189 cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
190 prom_offset | IO_MEM_ROM);
193 ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
195 ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
197 ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
199 fprintf(stderr, "qemu: could not load kernel '%s'\n",
206 if (initrd_filename) {
207 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
208 if (initrd_size < 0) {
209 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
214 if (initrd_size > 0) {
215 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
216 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
217 == 0x48647253) { // HdrS
218 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
219 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);